Overall: 10792/26107 fields covered

ADC1

0x42028000: Analog-to-Digital Converter

181/182 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR[1]
0x64 OFR[2]
0x68 OFR[3]
0x6c OFR[4]
0x80 JDR[1]
0x84 JDR[2]
0x88 JDR[3]
0x8c JDR[4]
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
r/w1c
AWD[3]
r/w1c
AWD[2]
r/w1c
AWD[1]
r/w1c
JEOS
r/w1c
JEOC
r/w1c
OVR
r/w1c
EOS
r/w1c
EOC
r/w1c
EOSMP
r/w1c
ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
r/w1s
ADSTP
r/w1s
JADSTART
r/w1s
ADSTART
r/w1s
ADDIS
r/w1s
ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

DEEPPWD

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

ADCALDIF

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw
AWD1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
ALIGN
rw
RES
rw
DMACFG
rw
DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw
TOVS
rw
OVSS
rw
OVSR
rw
JOVSE
rw
ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

JOVSE

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

OVSR

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

OVSS

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

TOVS

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[9]
rw
SMP[8]
rw
SMP[7]
rw
SMP[6]
rw
SMP[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[5]
rw
SMP[4]
rw
SMP[3]
rw
SMP[2]
rw
SMP[1]
rw
SMP[0]
rw
Toggle fields

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[18]
rw
SMP[17]
rw
SMP[16]
rw
SMP[15]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[15]
rw
SMP[14]
rw
SMP[13]
rw
SMP[12]
rw
SMP[11]
rw
SMP[10]
rw
Toggle fields

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

Allowed values: 0x0-0xff

HT2

Bits 16-23: HT2.

Allowed values: 0x0-0xff

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

Allowed values: 0x0-0xff

HT3

Bits 16-23: HT3.

Allowed values: 0x0-0xff

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[4]
rw
SQ[3]
rw
SQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[2]
rw
SQ[1]
rw
L
rw
Toggle fields

L

Bits 0-3: L.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[9]
rw
SQ[8]
rw
SQ[7]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[7]
rw
SQ[6]
rw
SQ[5]
rw
Toggle fields

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[14]
rw
SQ[13]
rw
SQ[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[12]
rw
SQ[11]
rw
SQ[10]
rw
Toggle fields

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[16]
rw
SQ[15]
rw
Toggle fields

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

Allowed values: 0x0-0xffff

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ[4]
rw
JSQ[3]
rw
JSQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ[2]
rw
JSQ[1]
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle fields

JL

Bits 0-1: JL.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFR[1]

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[2]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[3]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[4]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

JDR[1]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[2]

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[3]

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[4]

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD2CH[0]

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD3CH[0]

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Toggle fields

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

ADC2

0x42028100: Analog-to-Digital Converter

181/182 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR[1]
0x64 OFR[2]
0x68 OFR[3]
0x6c OFR[4]
0x80 JDR[1]
0x84 JDR[2]
0x88 JDR[3]
0x8c JDR[4]
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
r/w1c
AWD[3]
r/w1c
AWD[2]
r/w1c
AWD[1]
r/w1c
JEOS
r/w1c
JEOC
r/w1c
OVR
r/w1c
EOS
r/w1c
EOC
r/w1c
EOSMP
r/w1c
ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
r/w1s
ADSTP
r/w1s
JADSTART
r/w1s
ADSTART
r/w1s
ADDIS
r/w1s
ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

DEEPPWD

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

ADCALDIF

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw
AWD1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
ALIGN
rw
RES
rw
DMACFG
rw
DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw
TOVS
rw
OVSS
rw
OVSR
rw
JOVSE
rw
ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

JOVSE

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

OVSR

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

OVSS

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

TOVS

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[9]
rw
SMP[8]
rw
SMP[7]
rw
SMP[6]
rw
SMP[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[5]
rw
SMP[4]
rw
SMP[3]
rw
SMP[2]
rw
SMP[1]
rw
SMP[0]
rw
Toggle fields

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[18]
rw
SMP[17]
rw
SMP[16]
rw
SMP[15]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[15]
rw
SMP[14]
rw
SMP[13]
rw
SMP[12]
rw
SMP[11]
rw
SMP[10]
rw
Toggle fields

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

Allowed values: 0x0-0xff

HT2

Bits 16-23: HT2.

Allowed values: 0x0-0xff

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

Allowed values: 0x0-0xff

HT3

Bits 16-23: HT3.

Allowed values: 0x0-0xff

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[4]
rw
SQ[3]
rw
SQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[2]
rw
SQ[1]
rw
L
rw
Toggle fields

L

Bits 0-3: L.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[9]
rw
SQ[8]
rw
SQ[7]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[7]
rw
SQ[6]
rw
SQ[5]
rw
Toggle fields

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[14]
rw
SQ[13]
rw
SQ[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[12]
rw
SQ[11]
rw
SQ[10]
rw
Toggle fields

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[16]
rw
SQ[15]
rw
Toggle fields

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

Allowed values: 0x0-0xffff

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ[4]
rw
JSQ[3]
rw
JSQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ[2]
rw
JSQ[1]
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle fields

JL

Bits 0-1: JL.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFR[1]

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[2]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[3]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[4]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

JDR[1]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[2]

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[3]

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[4]

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD2CH[0]

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD3CH[0]

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Toggle fields

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

ADC_Common

0x42028300: Analog-to-Digital Converter

33/33 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Toggle fields

ADRDY_MST

Bit 0: ADDRDY_MST.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_MST

Bit 1: EOSMP_MST.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_MST

Bit 2: EOC_MST.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_MST

Bit 3: EOS_MST.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_MST

Bit 4: OVR_MST.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_MST

Bit 5: JEOC_MST.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_MST

Bit 6: JEOS_MST.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_MST

Bit 7: AWD1_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_MST

Bit 8: AWD2_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_MST

Bit 9: AWD3_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_MST

Bit 10: JQOVF_MST.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDY_SLV

Bit 16: ADRDY_SLV.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_SLV

Bit 17: EOSMP_SLV.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_SLV

Bit 18: EOC_SLV.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_SLV

Bit 19: EOS_SLV.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_SLV

Bit 20: OVR_SLV.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_SLV

Bit 21: JEOC_SLV.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_SLV

Bit 22: JEOS_SLV.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_SLV

Bit 23: AWD1_SLV.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_SLV

Bit 24: AWD2_SLV.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_SLV

Bit 25: AWD3_SLV.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_SLV

Bit 26: JQOVF_SLV.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBATEN
rw
VSENSEEN
rw
VREFEN
rw
PRESC
rw
CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw
DMACFG
rw
DELAY
rw
DUAL
rw
Toggle fields

DUAL

Bits 0-4: DUAL.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

DELAY

Bits 8-11: DELAY.

Allowed values: 0x0-0xf

DMACFG

Bit 13: DMACFG.

Allowed values:
0: OneShotMode: DMA One Shot mode selected
1: CircularMode: DMA Circular mode selected

MDMA

Bits 14-15: MDMA.

Allowed values:
0: Disabled: MDMA mode disabled
1: Interleaved: Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)
2: Bits12_10: MDMA mode enabled for 12 and 10-bit resolution
3: Bits8_6: MDMA mode enabled for 8 and 6-bit resolution

CKMODE

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

PRESC

Bits 18-21: ADC prescaler.

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

VREFEN

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

VSENSEEN

Bit 23: Temperature sensor selection.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

VBATEN

Bit 24: VBAT selection.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

CDR

Common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: RDATA_MST.

Allowed values: 0x0-0xffff

RDATA_SLV

Bits 16-31: RDATA_SLV.

Allowed values: 0x0-0xffff

AES

0x420c0000: Advanced encryption standard hardware accelerator 1

40/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DINR
0xc DOUTR
0x10 KEYR0
0x14 KEYR1
0x18 KEYR2
0x1c KEYR3
0x20 IVR0
0x24 IVR1
0x28 IVR2
0x2c IVR3
0x30 KEYR4
0x34 KEYR5
0x38 KEYR6
0x3c KEYR7
0x40 SUSP0R
0x44 SUSP1R
0x48 SUSP2R
0x4c SUSP3R
0x50 SUSP4R
0x54 SUSP5R
0x58 SUSP6R
0x5c SUSP7R
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw
KEYSIZE
rw
CHMOD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GCMPH
rw
DMAOUTEN
rw
DMAINEN
rw
ERRIE
rw
CCFIE
rw
ERRC
rw
CCFC
rw
CHMOD
rw
MODE
rw
DATATYPE
rw
EN
rw
Toggle fields

EN

Bit 0: AES enable.

Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit

MODE

Bits 3-4: AES operating mode.

Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption

CHMOD

Bits 5-6: AES chaining mode selection Bit1 Bit0.

Allowed values:
0: ECB: Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
1: CBC: Cipher-block chaining (CBC)
2: CTR: Counter mode (CTR)
3: GCM: Galois counter mode (GCM) and Galois message authentication code (GMAC)

CCFC

Bit 7: Computation Complete Flag Clear.

Allowed values:
1: Clear: Clear computation complete flag

ERRC

Bit 8: Error clear.

Allowed values:
1: Clear: Clear RDERR and WRERR flags

CCFIE

Bit 9: CCF flag interrupt enable.

Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt

DMAINEN

Bit 11: Enable DMA management of data input phase.

Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

Allowed values:
0: Init: Init phase
1: Header: Header phase
2: Payload: Payload phase
3: Final: Final Phase

CHMOD2

Bit 16: AES chaining mode Bit2.

Allowed values:
0: CHMOD: Mode as per CHMOD (ECB, CBC, CTR, GCM)
1: CCM: Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)

KEYSIZE

Bit 18: Key size selection.

Allowed values:
0: AES128: 128
1: AES256: 256

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

Allowed values: 0x0-0xf

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
WRERR
r
RDERR
r
CCF
r
Toggle fields

CCF

Bit 0: Computation complete flag.

Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete

RDERR

Bit 1: Read error flag.

Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected

WRERR

Bit 2: Write error flag.

Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected

BUSY

Bit 3: Busy flag.

Allowed values:
0: Idle: Idle
1: Busy: Busy

DINR

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
rw
Toggle fields

DIN

Bits 0-31: Data Input Register.

Allowed values: 0x0-0xffffffff

DOUTR

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-31: Data output register.

Allowed values: 0x0-0xffffffff

KEYR0

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits[31:0].

Allowed values: 0x0-0xffffffff

KEYR1

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [63:32]).

Allowed values: 0x0-0xffffffff

KEYR2

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [95:64]).

Allowed values: 0x0-0xffffffff

KEYR3

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [127:96]).

Allowed values: 0x0-0xffffffff

IVR0

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: initialization vector register (LSB IVR [31:0]).

Allowed values: 0x0-0xffffffff

IVR1

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (IVR [63:32]).

Allowed values: 0x0-0xffffffff

IVR2

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (IVR [95:64]).

Allowed values: 0x0-0xffffffff

IVR3

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

Allowed values: 0x0-0xffffffff

KEYR4

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [159:128]).

Allowed values: 0x0-0xffffffff

KEYR5

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [191:160]).

Allowed values: 0x0-0xffffffff

KEYR6

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [223:192]).

Allowed values: 0x0-0xffffffff

KEYR7

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [255:224]).

Allowed values: 0x0-0xffffffff

SUSP0R

AES suspend register 0

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 0.

Allowed values: 0x0-0xffffffff

SUSP1R

AES suspend register 1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 1.

Allowed values: 0x0-0xffffffff

SUSP2R

AES suspend register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 2.

Allowed values: 0x0-0xffffffff

SUSP3R

AES suspend register 3

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 3.

Allowed values: 0x0-0xffffffff

SUSP4R

AES suspend register 4

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 4.

Allowed values: 0x0-0xffffffff

SUSP5R

AES suspend register 5

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 5.

Allowed values: 0x0-0xffffffff

SUSP6R

AES suspend register 6

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 6.

Allowed values: 0x0-0xffffffff

SUSP7R

AES suspend register 7

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 7.

Allowed values: 0x0-0xffffffff

COMP

0x40010200: Comparator

2/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 COMP1_CSR
0x4 COMP2_CSR
Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1_LOCK
w
COMP1_VALUE
r
COMP1_SCALEN
rw
COMP1_BRGEN
rw
COMP1_BLANKING
rw
COMP1_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1_POLARITY
rw
COMP1_INPSEL
rw
COMP1_INMSEL
rw
COMP1_PWRMODE
rw
COMP1_EN
rw
Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_PWRMODE

Bits 2-3: Power Mode of the comparator 1.

COMP1_INMSEL

Bits 4-6: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bit 7: Comparator1 input plus selection bit.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

COMP1_BRGEN

Bit 22: Scaler bridge enable.

COMP1_SCALEN

Bit 23: Voltage scaler enable bit.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

Toggle fields

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-6: Comparator 2 Input Minus connection configuration bit.

COMP2_INPSEL

Bit 7: Comparator 2 Input Plus connection configuration bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: COMP2_CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: General-purpose 8-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw
REV_IN
rw
POLYSIZE
rw
RESET
w
Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Polynomialcoefficients
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Polynomialcoefficients
rw
Toggle fields

Polynomialcoefficients

Bits 0-31: Programmable polynomial.

CRS

0x40006000: Clock recovery system

9/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 ISR
0xc ICR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00004000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
SWSYNC
rw
AUTOTRIMEN
rw
CEN
rw
ESYNCIE
rw
ERRIE
rw
SYNCWARNIE
rw
SYNCOKIE
rw
Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-14: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw
SYNCSRC
rw
SYNCDIV
rw
FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r
TRIMOVF
r
SYNCMISS
r
SYNCERR
r
ESYNCF
r
ERRF
r
SYNCWARNF
r
SYNCOKF
r
Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw
ERRC
rw
SYNCWARNC
rw
SYNCOKC
rw
Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DAC

0x40007400: DAC

49/49 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R[1]
0xc DHR12L[1]
0x10 DHR8R[1]
0x14 DHR12R[2]
0x18 DHR12L[2]
0x1c DHR8R[2]
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR[1]
0x30 DOR[2]
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR[1]
0x44 SHSR[2]
0x48 SHHR
0x4c SHRR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN[2]
rw
DMAUDRIE[2]
rw
DMAEN[2]
rw
MAMP[2]
rw
WAVE[2]
rw
TSEL2
rw
TEN[2]
rw
EN[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HFSEL
rw
CEN[1]
rw
DMAUDRIE[1]
rw
DMAEN[1]
rw
MAMP[1]
rw
WAVE[1]
rw
TSEL1
rw
TEN[1]
rw
EN[1]
rw
Toggle fields

EN[1]

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[1]

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL1

Bits 2-5: TSEL10.

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9

WAVE[1]

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[1]

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[1]

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[1]

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[1]

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

HFSEL

Bit 15: HFSEL.

Allowed values:
0: Disabled: High frequency interface mode disabled
1: Enabled: High frequency interface mode enabled

EN[2]

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[2]

Bit 17: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL2

Bits 18-21: TSEL20.

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9

WAVE[2]

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[2]

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[2]

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[2]

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[2]

Bit 30: DAC channel2 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG[2]
w
SWTRIG[1]
w
Toggle fields

SWTRIG[1]

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

SWTRIG[2]

Bit 1: DAC channel2 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

DHR12R[1]

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[1]

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[1]

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12R[2]

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[2]

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[2]

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[2]DHR
rw
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC[2]DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR[1]

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

DOR[2]

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST[2]
r
CAL_FLAG[2]
r
DMAUDR[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST[1]
r
CAL_FLAG[1]
r
DMAUDR[1]
rw
Toggle fields

DMAUDR[1]

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[1]

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[1]

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR[2]

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[2]

Bit 30: DAC channel2 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[2]

Bit 31: DAC channel2 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM[1]
rw
Toggle fields

OTRIM[1]

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

OTRIM[2]

Bits 16-20: DAC channel2 offset trimming value.

Allowed values: 0x0-0x1f

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE[1]
rw
Toggle fields

MODE[1]

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

MODE[2]

Bits 16-18: DAC channel2 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

SHSR[1]

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHSR[2]

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD[1]
rw
Toggle fields

THOLD[1]

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

THOLD[2]

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH[1]
rw
Toggle fields

TREFRESH[1]

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

TREFRESH[2]

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

DBGMCU

0xe0044000: MCU debug component

2/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDCODE
0x4 CR
0x8 APB1LFZR
0xc APB1HFZR
0x10 APB2FZR
Toggle registers

IDCODE

DBGMCU_IDCODE

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID
r
Toggle fields

DEV_ID

Bits 0-11: Device identifier.

REV_ID

Bits 16-31: Revision identifie.

CR

Debug MCU configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRACE_MODE
rw
TRACE_EN
rw
TRACE_IOEN
rw
DBG_STANDBY
rw
DBG_STOP
rw
Toggle fields

DBG_STOP

Bit 1: Debug Stop mode.

DBG_STANDBY

Bit 2: Debug Standby mode.

TRACE_IOEN

Bit 4: Trace pin assignment control.

TRACE_EN

Bit 5: trace port and clock enable.

TRACE_MODE

Bits 6-7: Trace pin assignment control.

APB1LFZR

Debug MCU APB1 freeze register1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

Toggle fields

DBG_TIM2_STOP

Bit 0: TIM2 counter stopped when core is halted.

DBG_TIM3_STOP

Bit 1: TIM3 stop in debug.

DBG_TIM4_STOP

Bit 2: TIM4 stop in debug.

DBG_TIM5_STOP

Bit 3: TIM5 stop in debug.

DBG_TIM6_STOP

Bit 4: TIM6 counter stopped when core is halted.

DBG_TIM7_STOP

Bit 5: TIM7 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_WWDG_STOP

Bit 11: Window watchdog counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: Independent watchdog counter stopped when core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout counter stopped when core is halted.

DBG_I2C2_STOP

Bit 22: I2C2 SMBUS timeout counter stopped when core is halted.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout counter stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

APB1HFZR

Debug MCU APB1 freeze register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPTIM3_STOP
rw
DBG_LPTIM2_STOP
rw
DBG_I2C4_STOP
rw
Toggle fields

DBG_I2C4_STOP

Bit 1: I2C4 stop in debug.

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

DBG_LPTIM3_STOP

Bit 6: LPTIM3 stop in debug.

APB2FZR

Debug MCU APB2 freeze register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_TIM17_STOP
rw
DBG_TIM16_STOP
rw
DBG_TIM15_STOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_TIM8_STOP
rw
DBG_TIM1_STOP
rw
Toggle fields

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM8_STOP

Bit 13: TIM8 stop in debug.

DBG_TIM15_STOP

Bit 16: TIM15 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: DBG_TIM17_STOP.

DCB

0xe000ee08: Debug Control Block

0/1 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DSCSR
Toggle registers

DSCSR

Debug Security Control and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CDS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CDS

Bit 16: Current domain Secure.

DFSDM1

0x40016000: Digital filter for sigma delta modulators

84/400 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CH0CFGR1
0x4 CH0CFGR2
0x8 CH0AWSCDR
0xc CH0WDATR
0x10 CH0DATINR
0x14 CH0DLYR
0x20 CH1CFGR1
0x24 CH1CFGR2
0x28 CH1AWSCDR
0x2c CH1WDATR
0x30 CH1DATINR
0x34 CH1DLYR
0x40 CH2CFGR1
0x44 CH2CFGR2
0x48 CH2AWSCDR
0x4c CH2WDATR
0x50 CH2DATINR
0x54 CH2DLYR
0x60 CH3CFGR1
0x64 CH3CFGR2
0x68 CH3AWSCDR
0x6c CH3WDATR
0x70 CH3DATINR
0x74 CH3DLYR
0x80 CH4CFGR1
0x84 CH4CFGR2
0x88 CH4AWSCDR
0x8c CH4WDATR
0x90 CH4DATINR
0x94 CH4DLYR
0xa0 CH5CFGR1
0xa4 CH5CFGR2
0xa8 CH5AWSCDR
0xac CH5WDATR
0xb0 CH5DATINR
0xb4 CH5DLYR
0xc0 CH6CFGR1
0xc4 CH6CFGR2
0xc8 CH6AWSCDR
0xcc CH6WDATR
0xd0 CH6DATINR
0xd4 CH6DLYR
0xe0 CH7CFGR1
0xe4 CH7CFGR2
0xe8 CH7AWSCDR
0xec CH7WDATR
0xf0 CH7DATINR
0xf4 CH7DLYR
0x100 FLT0CR1
0x104 FLT0CR2
0x108 FLT0ISR
0x10c FLT0ICR
0x110 FLT0JCHGR
0x114 FLT0FCR
0x118 FLT0JDATAR
0x11c FLT0RDATAR
0x120 FLT0AWHTR
0x124 FLT0AWLTR
0x128 FLT0AWSR
0x12c FLT0AWCFR
0x130 FLT0EXMAX
0x134 FLT0EXMIN
0x138 FLT0CNVTIMR
0x180 FLT1CR1
0x184 FLT1CR2
0x188 FLT1ISR
0x18c FLT1ICR
0x190 FLT1JCHGR
0x194 FLT1FCR
0x198 FLT1JDATAR
0x19c FLT1RDATAR
0x1a4 FLT1AWLTR
0x1a8 FLT1AWSR
0x1ac FLT1AWCFR
0x1ac FLT1AWHTR
0x1b0 FLT1EXMAX
0x1b4 FLT1EXMIN
0x1b8 FLT1CNVTIMR
0x200 FLT2CR1
0x204 FLT2CR2
0x208 FLT2ISR
0x20c FLT2ICR
0x210 FLT2JCHGR
0x214 FLT2FCR
0x218 FLT2JDATAR
0x21c FLT2RDATAR
0x220 FLT2AWHTR
0x224 FLT2AWLTR
0x228 FLT2AWSR
0x22c FLT2AWCFR
0x230 FLT2EXMAX
0x234 FLT2EXMIN
0x238 FLT2CNVTIMR
0x280 FLT3CR1
0x284 FLT3CR2
0x288 FLT3ISR
0x28c FLT3ICR
0x290 FLT3JCHGR
0x294 FLT3FCR
0x298 FLT3JDATAR
0x29c FLT3RDATAR
0x2a0 FLT3AWHTR
0x2a4 FLT3AWLTR
0x2a8 FLT3AWSR
0x2ac FLT3AWCFR
0x2b0 FLT3EXMAX
0x2b4 FLT3EXMIN
0x2b8 FLT3CNVTIMR
Toggle registers

CH0CFGR1

channel configuration y register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH0CFGR2

channel configuration y register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH0AWSCDR

analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH0WDATR

channel watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH0DATINR

channel data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH0DLYR

DFSDM channel y delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function.

CH1CFGR1

CHCFG1R1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH1CFGR2

CHCFG1R2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH1AWSCDR

AWSCD1R

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH1WDATR

CHWDAT1R

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH1DATINR

CHDATIN1R

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH1DLYR

DFSDM channel y delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH2CFGR1

CHCFG2R1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH2CFGR2

CHCFG2R2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH2AWSCDR

AWSCD2R

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH2WDATR

CHWDAT2R

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH2DATINR

CHDATIN2R

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH2DLYR

DFSDM channel y delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH3CFGR1

CHCFG3R1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH3CFGR2

CHCFG3R2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH3AWSCDR

AWSCD3R

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH3WDATR

CHWDAT3R

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH3DATINR

CHDATIN3R

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH3DLYR

DFSDM channel y delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH4CFGR1

CHCFG4R1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH4CFGR2

CHCFG4R2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH4AWSCDR

AWSCD4R

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH4WDATR

CHWDAT4R

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH4DATINR

CHDATIN4R

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH4DLYR

DFSDM channel y delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH5CFGR1

CHCFG5R1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH5CFGR2

CHCFG5R2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH5AWSCDR

AWSCD5R

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH5WDATR

CHWDAT5R

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH5DATINR

CHDATIN5R

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH5DLYR

DFSDM channel y delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: read-only.

CH6CFGR1

CHCFG6R1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH6CFGR2

CH6CFGR2

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH6AWSCDR

AWSCD6R

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH6WDATR

CHWDAT6R

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH6DATINR

CHDATIN6R

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH6DLYR

DFSDM channel y delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH7CFGR1

CHCFG7R1

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH7CFGR2

CHCFG7R2

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH7AWSCDR

AWSCD7R

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH7WDATR

CHWDAT7R

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH7DATINR

CHDATIN7R

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH7DLYR

DFSDM channel y delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

FLT0CR1

control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT0CR2

control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT0ISR

interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT0ICR

interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT0JCHGR

injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT0FCR

filter control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT0JDATAR

data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT0RDATAR

data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT0AWHTR

analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT0AWLTR

analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT0AWSR

analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT0AWCFR

analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT0EXMAX

Extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT0EXMIN

Extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT0CNVTIMR

conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT1CR1

control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT1CR2

control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT1ISR

interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT1ICR

interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT1JCHGR

injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT1FCR

filter control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT1JDATAR

data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT1RDATAR

data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT1AWLTR

analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT1AWSR

analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT1AWCFR

analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT1AWHTR

analog watchdog high threshold register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT1EXMAX

Extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT1EXMIN

Extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT1CNVTIMR

conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT2CR1

control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT2CR2

control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT2ISR

interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT2ICR

interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT2JCHGR

injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT2FCR

filter control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT2JDATAR

data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT2RDATAR

data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT2AWHTR

analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT2AWLTR

analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT2AWSR

analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT2AWCFR

analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT2EXMAX

Extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT2EXMIN

Extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT2CNVTIMR

conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT3CR1

control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT3CR2

control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT3ISR

interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT3ICR

interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT3JCHGR

injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT3FCR

filter control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT3JDATAR

data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT3RDATAR

data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT3AWHTR

analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT3AWLTR

analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT3AWSR

analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT3AWCFR

analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT3EXMAX

Extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT3EXMIN

Extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT3CNVTIMR

conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

DMA1

0x40020000: Direct memory access controller

168/240 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

DMA2

0x40020400: Direct memory access controller

168/240 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

DMAMUX1

0x40020800: Direct memory access Multiplexer

136/172 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR[0]
0x4 CCR[1]
0x8 CCR[2]
0xc CCR[3]
0x10 CCR[4]
0x14 CCR[5]
0x18 CCR[6]
0x1c CCR[7]
0x20 CCR[8]
0x24 CCR[9]
0x28 CCR[10]
0x2c CCR[11]
0x30 CCR[12]
0x34 CCR[13]
0x38 CCR[14]
0x3c CCR[15]
0x80 CSR
0x84 CCFR
0x100 RGCR[0]
0x104 RGCR[1]
0x108 RGCR[2]
0x10c RGCR[3]
0x140 RGSR
0x144 RGCFR
Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[14]

DMA Multiplexer Channel 14 Control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[15]

DMA Multiplexer Channel 15 Control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

DMA Multiplexer Channel Status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

SOF[0]

Bit 0: Synchronization Overrun Flag 0.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[1]

Bit 1: Synchronization Overrun Flag 1.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[2]

Bit 2: Synchronization Overrun Flag 2.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[3]

Bit 3: Synchronization Overrun Flag 3.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[4]

Bit 4: Synchronization Overrun Flag 4.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[5]

Bit 5: Synchronization Overrun Flag 5.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[6]

Bit 6: Synchronization Overrun Flag 6.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[7]

Bit 7: Synchronization Overrun Flag 7.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[8]

Bit 8: Synchronization Overrun Flag 8.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[9]

Bit 9: Synchronization Overrun Flag 9.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[10]

Bit 10: Synchronization Overrun Flag 10.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[11]

Bit 11: Synchronization Overrun Flag 11.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[12]

Bit 12: Synchronization Overrun Flag 12.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[13]

Bit 13: Synchronization Overrun Flag 13.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[14]

Bit 14: Synchronization Overrun Flag 14.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[15]

Bit 15: Synchronization Overrun Flag 15.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

CCFR

DMA Channel Clear Flag Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF[15]
r/w1c
CSOF[14]
r/w1c
CSOF[13]
r/w1c
CSOF[12]
r/w1c
CSOF[11]
r/w1c
CSOF[10]
r/w1c
CSOF[9]
r/w1c
CSOF[8]
r/w1c
CSOF[7]
r/w1c
CSOF[6]
r/w1c
CSOF[5]
r/w1c
CSOF[4]
r/w1c
CSOF[3]
r/w1c
CSOF[2]
r/w1c
CSOF[1]
r/w1c
CSOF[0]
r/w1c
Toggle fields

CSOF[0]

Bit 0: Synchronization Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[1]

Bit 1: Synchronization Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[2]

Bit 2: Synchronization Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[3]

Bit 3: Synchronization Clear Overrun Flag 3.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[4]

Bit 4: Synchronization Clear Overrun Flag 4.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[5]

Bit 5: Synchronization Clear Overrun Flag 5.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[6]

Bit 6: Synchronization Clear Overrun Flag 6.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[7]

Bit 7: Synchronization Clear Overrun Flag 7.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[8]

Bit 8: Synchronization Clear Overrun Flag 8.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[9]

Bit 9: Synchronization Clear Overrun Flag 9.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[10]

Bit 10: Synchronization Clear Overrun Flag 10.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[11]

Bit 11: Synchronization Clear Overrun Flag 11.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[12]

Bit 12: Synchronization Clear Overrun Flag 12.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[13]

Bit 13: Synchronization Clear Overrun Flag 13.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[14]

Bit 14: Synchronization Clear Overrun Flag 14.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[15]

Bit 15: Synchronization Clear Overrun Flag 15.

Allowed values:
1: Clear: Clear synchronization flag

RGCR[0]

DMA Request Generator 0 Control Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGCR[1]

DMA Request Generator 1 Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGCR[2]

DMA Request Generator 2 Control Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGCR[3]

DMA Request Generator 3 Control Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGSR

DMA Request Generator Status Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF[3]
r
OF[2]
r
OF[1]
r
OF[0]
r
Toggle fields

OF[0]

Bit 0: Generator Overrun Flag 0.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[1]

Bit 1: Generator Overrun Flag 1.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[2]

Bit 2: Generator Overrun Flag 2.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[3]

Bit 3: Generator Overrun Flag 3.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

RGCFR

DMA Request Generator Clear Flag Register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF[3]
r/w1c
COF[2]
r/w1c
COF[1]
r/w1c
COF[0]
r/w1c
Toggle fields

COF[0]

Bit 0: Generator Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear overrun flag

COF[1]

Bit 1: Generator Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear overrun flag

COF[2]

Bit 2: Generator Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear overrun flag

COF[3]

Bit 3: Generator Clear Overrun Flag 3.

Allowed values:
1: Clear: Clear overrun flag

EXTI

0x4002f400: External interrupt/event controller

0/302 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc RPR1
0x10 FPR1
0x14 SECCFGR1
0x18 PRIVCFGR1
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c RPR2
0x30 FPR2
0x34 PRIVCFGR2
0x38 SECCFGR2
0x60 EXTICR1
0x64 EXTICR2
0x68 EXTICR3
0x6c EXTICR4
0x70 LOCKRG
0x80 IMR1
0x84 EMR1
0x90 IMR2
0x94 EMR2
Toggle registers

RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT22
rw
RT21
rw
RT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15
rw
RT14
rw
RT13
rw
RT12
rw
RT11
rw
RT10
rw
RT9
rw
RT8
rw
RT7
rw
RT6
rw
RT5
rw
RT4
rw
RT3
rw
RT2
rw
RT1
rw
RT0
rw
Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable event input x.

RT1

Bit 1: Rising trigger event configuration bit of configurable event input x.

RT2

Bit 2: Rising trigger event configuration bit of configurable event input x.

RT3

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT4

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT5

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT6

Bit 6: Rising trigger event configuration bit of configurable event input x.

RT7

Bit 7: Rising trigger event configuration bit of configurable event input x.

RT8

Bit 8: Rising trigger event configuration bit of configurable event input x.

RT9

Bit 9: Rising trigger event configuration bit of configurable event input x.

RT10

Bit 10: Rising trigger event configuration bit of configurable event input x.

RT11

Bit 11: Rising trigger event configuration bit of configurable event input x.

RT12

Bit 12: Rising trigger event configuration bit of configurable event input x.

RT13

Bit 13: Rising trigger event configuration bit of configurable event input x.

RT14

Bit 14: Rising trigger event configuration bit of configurable event input x.

RT15

Bit 15: Rising trigger event configuration bit of configurable event input x.

RT16

Bit 16: Rising trigger event configuration bit of configurable event input x.

RT21

Bit 21: Rising trigger event configuration bit of configurable event input x.

RT22

Bit 22: Rising trigger event configuration bit of configurable event input x.

FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT22
rw
FT21
rw
FT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15
rw
FT14
rw
FT13
rw
FT12
rw
FT11
rw
FT10
rw
FT9
rw
FT8
rw
FT7
rw
FT6
rw
FT5
rw
FT4
rw
FT3
rw
FT2
rw
FT1
rw
FT0
rw
Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable event input x.

FT1

Bit 1: Falling trigger event configuration bit of configurable event input x.

FT2

Bit 2: Falling trigger event configuration bit of configurable event input x.

FT3

Bit 3: Falling trigger event configuration bit of configurable event input x.

FT4

Bit 4: Falling trigger event configuration bit of configurable event input x.

FT5

Bit 5: Falling trigger event configuration bit of configurable event input x.

FT6

Bit 6: Falling trigger event configuration bit of configurable event input x.

FT7

Bit 7: Falling trigger event configuration bit of configurable event input x.

FT8

Bit 8: Falling trigger event configuration bit of configurable event input x.

FT9

Bit 9: Falling trigger event configuration bit of configurable event input x.

FT10

Bit 10: Falling trigger event configuration bit of configurable event input x.

FT11

Bit 11: Falling trigger event configuration bit of configurable event input x.

FT12

Bit 12: Falling trigger event configuration bit of configurable event input x.

FT13

Bit 13: Falling trigger event configuration bit of configurable event input x.

FT14

Bit 14: Falling trigger event configuration bit of configurable event input x.

FT15

Bit 15: Falling trigger event configuration bit of configurable event input x.

FT16

Bit 16: Falling trigger event configuration bit of configurable event input x.

FT21

Bit 21: Falling trigger event configuration bit of configurable event input x.

FT22

Bit 22: Falling trigger event configuration bit of configurable event input x.

SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI22
rw
SWI21
rw
SWI16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI15
rw
SWI14
rw
SWI13
rw
SWI12
rw
SWI11
rw
SWI10
rw
SWI9
rw
SWI8
rw
SWI7
rw
SWI6
rw
SWI5
rw
SWI4
rw
SWI3
rw
SWI2
rw
SWI1
rw
SWI0
rw
Toggle fields

SWI0

Bit 0: Software interrupt on event x.

SWI1

Bit 1: Software interrupt on event x.

SWI2

Bit 2: Software interrupt on event x.

SWI3

Bit 3: Software interrupt on event x.

SWI4

Bit 4: Software interrupt on event x.

SWI5

Bit 5: Software interrupt on event x.

SWI6

Bit 6: Software interrupt on event x.

SWI7

Bit 7: Software interrupt on event x.

SWI8

Bit 8: Software interrupt on event x.

SWI9

Bit 9: Software interrupt on event x.

SWI10

Bit 10: Software interrupt on event x.

SWI11

Bit 11: Software interrupt on event x.

SWI12

Bit 12: Software interrupt on event x.

SWI13

Bit 13: Software interrupt on event x.

SWI14

Bit 14: Software interrupt on event x.

SWI15

Bit 15: Software interrupt on event x.

SWI16

Bit 16: Software interrupt on event x.

SWI21

Bit 21: Software interrupt on event x.

SWI22

Bit 22: Software interrupt on event x.

RPR1

EXTI rising edge pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPIF22
rw
RPIF21
rw
RPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF15
rw
RPIF14
rw
RPIF13
rw
RPIF12
rw
RPIF11
rw
RPIF10
rw
RPIF9
rw
RPIF8
rw
RPIF7
rw
RPIF6
rw
RPIF5
rw
RPIF4
rw
RPIF3
rw
RPIF2
rw
RPIF1
rw
RPIF0
rw
Toggle fields

RPIF0

Bit 0: configurable event inputs x rising edge pending bit.

RPIF1

Bit 1: configurable event inputs x rising edge pending bit.

RPIF2

Bit 2: configurable event inputs x rising edge pending bit.

RPIF3

Bit 3: configurable event inputs x rising edge pending bit.

RPIF4

Bit 4: configurable event inputs x rising edge pending bit.

RPIF5

Bit 5: configurable event inputs x rising edge pending bit.

RPIF6

Bit 6: configurable event inputs x rising edge pending bit.

RPIF7

Bit 7: configurable event inputs x rising edge pending bit.

RPIF8

Bit 8: configurable event inputs x rising edge pending bit.

RPIF9

Bit 9: configurable event inputs x rising edge pending bit.

RPIF10

Bit 10: configurable event inputs x rising edge pending bit.

RPIF11

Bit 11: configurable event inputs x rising edge pending bit.

RPIF12

Bit 12: configurable event inputs x rising edge pending bit.

RPIF13

Bit 13: configurable event inputs x rising edge pending bit.

RPIF14

Bit 14: configurable event inputs x rising edge pending bit.

RPIF15

Bit 15: configurable event inputs x rising edge pending bit.

RPIF16

Bit 16: configurable event inputs x rising edge pending bit.

RPIF21

Bit 21: configurable event inputs x rising edge pending bit.

RPIF22

Bit 22: configurable event inputs x rising edge pending bit.

FPR1

EXTI falling edge pending register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPIF22
rw
FPIF21
rw
FPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF15
rw
FPIF14
rw
FPIF13
rw
FPIF12
rw
FPIF11
rw
FPIF10
rw
FPIF9
rw
FPIF8
rw
FPIF7
rw
FPIF6
rw
FPIF5
rw
FPIF4
rw
FPIF3
rw
FPIF2
rw
FPIF1
rw
FPIF0
rw
Toggle fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit..

FPIF1

Bit 1: configurable event inputs x falling edge pending bit..

FPIF2

Bit 2: configurable event inputs x falling edge pending bit..

FPIF3

Bit 3: configurable event inputs x falling edge pending bit..

FPIF4

Bit 4: configurable event inputs x falling edge pending bit..

FPIF5

Bit 5: configurable event inputs x falling edge pending bit..

FPIF6

Bit 6: configurable event inputs x falling edge pending bit..

FPIF7

Bit 7: configurable event inputs x falling edge pending bit..

FPIF8

Bit 8: configurable event inputs x falling edge pending bit..

FPIF9

Bit 9: configurable event inputs x falling edge pending bit..

FPIF10

Bit 10: configurable event inputs x falling edge pending bit..

FPIF11

Bit 11: configurable event inputs x falling edge pending bit..

FPIF12

Bit 12: configurable event inputs x falling edge pending bit..

FPIF13

Bit 13: configurable event inputs x falling edge pending bit..

FPIF14

Bit 14: configurable event inputs x falling edge pending bit..

FPIF15

Bit 15: configurable event inputs x falling edge pending bit..

FPIF16

Bit 16: configurable event inputs x falling edge pending bit..

FPIF21

Bit 21: configurable event inputs x falling edge pending bit..

FPIF22

Bit 22: configurable event inputs x falling edge pending bit..

SECCFGR1

EXTI security configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEC31
rw
SEC30
rw
SEC29
rw
SEC28
rw
SEC27
rw
SEC26
rw
SEC25
rw
SEC24
rw
SEC23
rw
SEC22
rw
SEC21
rw
SEC20
rw
SEC19
rw
SEC18
rw
SEC17
rw
SEC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
rw
SEC14
rw
SEC13
rw
SEC12
rw
SEC11
rw
SEC10
rw
SEC9
rw
SEC8
rw
SEC7
rw
SEC6
rw
SEC5
rw
SEC4
rw
SEC3
rw
SEC2
rw
SEC1
rw
SEC0
rw
Toggle fields

SEC0

Bit 0: Security enable on event input x.

SEC1

Bit 1: Security enable on event input x.

SEC2

Bit 2: Security enable on event input x.

SEC3

Bit 3: Security enable on event input x.

SEC4

Bit 4: Security enable on event input x.

SEC5

Bit 5: Security enable on event input x.

SEC6

Bit 6: Security enable on event input x.

SEC7

Bit 7: Security enable on event input x.

SEC8

Bit 8: Security enable on event input x.

SEC9

Bit 9: Security enable on event input x.

SEC10

Bit 10: Security enable on event input x.

SEC11

Bit 11: Security enable on event input x.

SEC12

Bit 12: Security enable on event input x.

SEC13

Bit 13: Security enable on event input x.

SEC14

Bit 14: Security enable on event input x.

SEC15

Bit 15: Security enable on event input x.

SEC16

Bit 16: Security enable on event input x.

SEC17

Bit 17: Security enable on event input x.

SEC18

Bit 18: Security enable on event input x.

SEC19

Bit 19: Security enable on event input x.

SEC20

Bit 20: Security enable on event input x.

SEC21

Bit 21: Security enable on event input x.

SEC22

Bit 22: Security enable on event input x.

SEC23

Bit 23: Security enable on event input x.

SEC24

Bit 24: Security enable on event input x.

SEC25

Bit 25: Security enable on event input x.

SEC26

Bit 26: Security enable on event input x.

SEC27

Bit 27: Security enable on event input x.

SEC28

Bit 28: Security enable on event input x.

SEC29

Bit 29: Security enable on event input x.

SEC30

Bit 30: Security enable on event input x.

SEC31

Bit 31: Security enable on event input x.

PRIVCFGR1

EXTI privilege configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

PRIV0

Bit 0: Security enable on event input x.

PRIV1

Bit 1: Security enable on event input x.

PRIV2

Bit 2: Security enable on event input x.

PRIV3

Bit 3: Security enable on event input x.

PRIV4

Bit 4: Security enable on event input x.

PRIV5

Bit 5: Security enable on event input x.

PRIV6

Bit 6: Security enable on event input x.

PRIV7

Bit 7: Security enable on event input x.

PRIV8

Bit 8: Security enable on event input x.

PRIV9

Bit 9: Security enable on event input x.

PRIV10

Bit 10: Security enable on event input x.

PRIV11

Bit 11: Security enable on event input x.

PRIV12

Bit 12: Security enable on event input x.

PRIV13

Bit 13: Security enable on event input x.

PRIV14

Bit 14: Security enable on event input x.

PRIV15

Bit 15: Security enable on event input x.

PRIV16

Bit 16: Security enable on event input x.

PRIV17

Bit 17: Security enable on event input x.

PRIV18

Bit 18: Security enable on event input x.

PRIV19

Bit 19: Security enable on event input x.

PRIV20

Bit 20: Security enable on event input x.

PRIV21

Bit 21: Security enable on event input x.

PRIV22

Bit 22: Security enable on event input x.

PRIV23

Bit 23: Security enable on event input x.

PRIV24

Bit 24: Security enable on event input x.

PRIV25

Bit 25: Security enable on event input x.

PRIV26

Bit 26: Security enable on event input x.

PRIV27

Bit 27: Security enable on event input x.

PRIV28

Bit 28: Security enable on event input x.

PRIV29

Bit 29: Security enable on event input x.

PRIV30

Bit 30: Security enable on event input x.

PRIV31

Bit 31: Security enable on event input x.

RTSR2

EXTI rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT38
rw
RT37
rw
RT36
rw
RT35
rw
Toggle fields

RT35

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT36

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT37

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT38

Bit 6: Rising trigger event configuration bit of configurable event input x.

FTSR2

EXTI falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT38
rw
FT37
rw
FT36
rw
FT35
rw
Toggle fields

FT35

Bit 3: FT35.

FT36

Bit 4: FT36.

FT37

Bit 5: FT37.

FT38

Bit 6: FT38.

SWIER2

EXTI software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI38
rw
SWI37
rw
SWI36
rw
SWI35
rw
Toggle fields

SWI35

Bit 3: SWI35.

SWI36

Bit 4: SWI36.

SWI37

Bit 5: SWI37.

SWI38

Bit 6: SWI38.

RPR2

EXTI rising edge pending register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF38
rw
RPIF37
rw
RPIF36
rw
RPIF35
rw
Toggle fields

RPIF35

Bit 3: RPIF35.

RPIF36

Bit 4: RPIF36.

RPIF37

Bit 5: RPIF37.

RPIF38

Bit 6: RPIF38.

FPR2

EXTI falling edge pending register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF38
rw
FPIF37
rw
FPIF36
rw
FPIF35
rw
Toggle fields

FPIF35

Bit 3: FPIF35.

FPIF36

Bit 4: FPIF36.

FPIF37

Bit 5: FPIF37.

FPIF38

Bit 6: FPIF38.

PRIVCFGR2

EXTI security enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV42
rw
PRIV41
rw
PRIV40
rw
PRIV39
rw
PRIV38
rw
PRIV37
rw
PRIV36
rw
PRIV35
rw
PRIV34
rw
PRIV33
rw
PRIV32
rw
Toggle fields

PRIV32

Bit 0: PRIV32.

PRIV33

Bit 1: PRIV33.

PRIV34

Bit 2: PRIV34.

PRIV35

Bit 3: PRIV35.

PRIV36

Bit 4: PRIV36.

PRIV37

Bit 5: PRIV37.

PRIV38

Bit 6: PRIV38.

PRIV39

Bit 7: PRIV39.

PRIV40

Bit 8: PRIV40.

PRIV41

Bit 9: PRIV41.

PRIV42

Bit 10: PRIV42.

SECCFGR2

EXTI security enable register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC42
rw
SEC41
rw
SEC40
rw
SEC39
rw
SEC38
rw
SEC37
rw
SEC36
rw
SEC35
rw
SEC34
rw
SEC33
rw
SEC32
rw
Toggle fields

SEC32

Bit 0: SEC32.

SEC33

Bit 1: SEC33.

SEC34

Bit 2: SEC34.

SEC35

Bit 3: SEC35.

SEC36

Bit 4: SEC36.

SEC37

Bit 5: SEC37.

SEC38

Bit 6: SEC38.

SEC39

Bit 7: SEC39.

SEC40

Bit 8: SEC40.

SEC41

Bit 9: SEC41.

SEC42

Bit 10: SEC42.

EXTICR1

EXTI external interrupt selection register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI3
rw
EXTI2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI1
rw
EXTI0
rw
Toggle fields

EXTI0

Bits 0-7: EXTIm GPIO port selection.

EXTI1

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI2

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI3

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR2

EXTI external interrupt selection register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI7
rw
EXTI6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI5
rw
EXTI4
rw
Toggle fields

EXTI4

Bits 0-7: EXTIm GPIO port selection.

EXTI5

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI6

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI7

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR3

EXTI external interrupt selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI11
rw
EXTI10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI9
rw
EXTI8
rw
Toggle fields

EXTI8

Bits 0-7: EXTIm GPIO port selection.

EXTI9

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI10

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI11

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR4

EXTI external interrupt selection register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15
rw
EXTI14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI13
rw
EXTI12
rw
Toggle fields

EXTI12

Bits 0-7: EXTIm GPIO port selection.

EXTI13

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI14

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI15

Bits 24-31: EXTIm+3 GPIO port selection.

LOCKRG

EXTI lock register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
rw
Toggle fields

LOCK

Bit 0: LOCK.

IMR1

EXTI CPU wakeup with interrupt mask register

Offset: 0x80, size: 32, reset: 0xFF9E0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw
IM30
rw
IM29
rw
IM28
rw
IM27
rw
IM26
rw
IM25
rw
IM24
rw
IM23
rw
IM22
rw
IM21
rw
IM20
rw
IM19
rw
IM18
rw
IM17
rw
IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw
IM14
rw
IM13
rw
IM12
rw
IM11
rw
IM10
rw
IM9
rw
IM8
rw
IM7
rw
IM6
rw
IM5
rw
IM4
rw
IM3
rw
IM2
rw
IM1
rw
IM0
rw
Toggle fields

IM0

Bit 0: CPU wakeup with interrupt mask on event input.

IM1

Bit 1: CPU wakeup with interrupt mask on event input.

IM2

Bit 2: CPU wakeup with interrupt mask on event input.

IM3

Bit 3: CPU wakeup with interrupt mask on event input.

IM4

Bit 4: CPU wakeup with interrupt mask on event input.

IM5

Bit 5: CPU wakeup with interrupt mask on event input.

IM6

Bit 6: CPU wakeup with interrupt mask on event input.

IM7

Bit 7: CPU wakeup with interrupt mask on event input.

IM8

Bit 8: CPU wakeup with interrupt mask on event input.

IM9

Bit 9: CPU wakeup with interrupt mask on event input.

IM10

Bit 10: CPU wakeup with interrupt mask on event input.

IM11

Bit 11: CPU wakeup with interrupt mask on event input.

IM12

Bit 12: CPU wakeup with interrupt mask on event input.

IM13

Bit 13: CPU wakeup with interrupt mask on event input.

IM14

Bit 14: CPU wakeup with interrupt mask on event input.

IM15

Bit 15: CPU wakeup with interrupt mask on event input.

IM16

Bit 16: CPU wakeup with interrupt mask on event input.

IM17

Bit 17: CPU wakeup with interrupt mask on event input.

IM18

Bit 18: CPU wakeup with interrupt mask on event input.

IM19

Bit 19: CPU wakeup with interrupt mask on event input.

IM20

Bit 20: CPU wakeup with interrupt mask on event input.

IM21

Bit 21: CPU wakeup with interrupt mask on event input.

IM22

Bit 22: CPU wakeup with interrupt mask on event input.

IM23

Bit 23: CPU wakeup with interrupt mask on event input.

IM24

Bit 24: CPU wakeup with interrupt mask on event input.

IM25

Bit 25: CPU wakeup with interrupt mask on event input.

IM26

Bit 26: CPU wakeup with interrupt mask on event input.

IM27

Bit 27: CPU wakeup with interrupt mask on event input.

IM28

Bit 28: CPU wakeup with interrupt mask on event input.

IM29

Bit 29: CPU wakeup with interrupt mask on event input.

IM30

Bit 30: CPU wakeup with interrupt mask on event input.

IM31

Bit 31: CPU wakeup with interrupt mask on event input.

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM31
rw
EM30
rw
EM29
rw
EM28
rw
EM27
rw
EM26
rw
EM25
rw
EM24
rw
EM23
rw
EM22
rw
EM21
rw
EM20
rw
EM19
rw
EM18
rw
EM17
rw
EM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw
EM14
rw
EM13
rw
EM12
rw
EM11
rw
EM10
rw
EM9
rw
EM8
rw
EM7
rw
EM6
rw
EM5
rw
EM4
rw
EM3
rw
EM2
rw
EM1
rw
EM0
rw
Toggle fields

EM0

Bit 0: CPU wakeup with interrupt mask on event input.

EM1

Bit 1: CPU wakeup with interrupt mask on event input.

EM2

Bit 2: CPU wakeup with interrupt mask on event input.

EM3

Bit 3: CPU wakeup with interrupt mask on event input.

EM4

Bit 4: CPU wakeup with interrupt mask on event input.

EM5

Bit 5: CPU wakeup with interrupt mask on event input.

EM6

Bit 6: CPU wakeup with interrupt mask on event input.

EM7

Bit 7: CPU wakeup with interrupt mask on event input.

EM8

Bit 8: CPU wakeup with interrupt mask on event input.

EM9

Bit 9: CPU wakeup with interrupt mask on event input.

EM10

Bit 10: CPU wakeup with interrupt mask on event input.

EM11

Bit 11: CPU wakeup with interrupt mask on event input.

EM12

Bit 12: CPU wakeup with interrupt mask on event input.

EM13

Bit 13: CPU wakeup with interrupt mask on event input.

EM14

Bit 14: CPU wakeup with interrupt mask on event input.

EM15

Bit 15: CPU wakeup with interrupt mask on event input.

EM16

Bit 16: CPU wakeup with interrupt mask on event input.

EM17

Bit 17: CPU wakeup with interrupt mask on event input.

EM18

Bit 18: CPU wakeup with interrupt mask on event input.

EM19

Bit 19: CPU wakeup with interrupt mask on event input.

EM20

Bit 20: CPU wakeup with interrupt mask on event input.

EM21

Bit 21: CPU wakeup with interrupt mask on event input.

EM22

Bit 22: CPU wakeup with interrupt mask on event input.

EM23

Bit 23: CPU wakeup with interrupt mask on event input.

EM24

Bit 24: CPU wakeup with interrupt mask on event input.

EM25

Bit 25: CPU wakeup with interrupt mask on event input.

EM26

Bit 26: CPU wakeup with interrupt mask on event input.

EM27

Bit 27: CPU wakeup with interrupt mask on event input.

EM28

Bit 28: CPU wakeup with interrupt mask on event input.

EM29

Bit 29: CPU wakeup with interrupt mask on event input.

EM30

Bit 30: CPU wakeup with interrupt mask on event input.

EM31

Bit 31: CPU wakeup with interrupt mask on event input.

IMR2

EXTI CPUm wakeup with interrupt mask register

Offset: 0x90, size: 32, reset: 0x00000787, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM42
rw
IM41
rw
IM40
rw
IM38
rw
IM37
rw
IM36
rw
IM35
rw
IM34
rw
IM33
rw
IM32
rw
Toggle fields

IM32

Bit 0: CPU wakeup with interrupt mask on event input.

IM33

Bit 1: CPU wakeup with interrupt mask on event input.

IM34

Bit 2: CPU wakeup with interrupt mask on event input.

IM35

Bit 3: CPU wakeup with interrupt mask on event input.

IM36

Bit 4: CPU wakeup with interrupt mask on event input.

IM37

Bit 5: CPU wakeup with interrupt mask on event input.

IM38

Bit 6: CPU wakeup with interrupt mask on event input.

IM40

Bit 8: CPU wakeup with interrupt mask on event input.

IM41

Bit 9: CPU wakeup with interrupt mask on event input.

IM42

Bit 10: CPU wakeup with interrupt mask on event input.

EMR2

EXTI CPU wakeup with event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM42
rw
EM41
rw
EM40
rw
EM38
rw
EM37
rw
EM36
rw
EM35
rw
EM34
rw
EM33
rw
EM32
rw
Toggle fields

EM32

Bit 0: CPU wakeup with interrupt mask on event input.

EM33

Bit 1: CPU wakeup with interrupt mask on event input.

EM34

Bit 2: CPU wakeup with interrupt mask on event input.

EM35

Bit 3: CPU wakeup with interrupt mask on event input.

EM36

Bit 4: CPU wakeup with interrupt mask on event input.

EM37

Bit 5: CPU wakeup with interrupt mask on event input.

EM38

Bit 6: CPU wakeup with interrupt mask on event input.

EM40

Bit 8: CPU wakeup with interrupt mask on event input.

EM41

Bit 9: CPU wakeup with interrupt mask on event input.

EM42

Bit 10: CPU wakeup with interrupt mask on event input.

FDCAN1

0x4000a400: FDCAN1

36/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 ENDN
0xc DBTP
0x10 TEST
0x14 RWD
0x18 CCCR
0x1c NBTP
0x20 TSCC
0x24 TSCV
0x28 TOCC
0x2c TOCV
0x40 ECR
0x44 PSR
0x48 TDCR
0x50 IR
0x54 IE
0x58 ILS
0x5c ILE
0x80 RXGFC
0x84 XIDAM
0x88 HPMS
0x90 RXF0S
0x94 RXF0A
0x98 RXF1S
0x9c RXF1A
0xc0 TXBC
0xc4 TXFQS
0xc8 TXBRP
0xcc TXBAR
0xd0 TXBCR
0xd4 TXBTO
0xd8 TXBCF
0xdc TXBTIE
0xe0 TXBCIE
0xe4 TXEFS
0xe8 TXEFA
0x100 CKDIV
Toggle registers

CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r
STEP
r
SUBSTEP
r
YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r
DAY
r
Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

ENDN

FDCAN Core Release Register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw
DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw
DTSEG2
rw
DSJW
rw
Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000010, access: Unspecified

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r
TX
rw
LBCK
rw
Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r
WDC
rw
Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw
TXP
rw
EFBI
rw
PXHD
rw
BSE
rw
FDOE
rw
TEST
rw
DAR
rw
MON
rw
CSR
rw
CSA
rw
ASM
rw
CCE
rw
INIT
rw
Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw
NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw
TSEG2
rw
Toggle fields

TSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: NSJW: Nominal (Re)Synchronization Jump Width.

TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: Timestamp Counter.

TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw
ETOC
rw
Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: Timeout Counter.

ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
rw
REC
r
TEC
r
Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw
REDL
rw
RBRS
rw
RESI
rw
DLEC
rw
BO
r
EW
r
EP
r
ACT
r
LEC
rw
Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw
TDCF
rw
Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw
PED
rw
PEA
rw
WDI
rw
BO
rw
EW
rw
EP
rw
ELO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOO
rw
MRAF
rw
TSW
rw
TEFL
rw
TEFF
rw
TEFN
rw
TFE
rw
TCF
rw
TC
rw
HPM
rw
RF1L
rw
RF1F
rw
RF1N
rw
RF0L
rw
RF0F
rw
RF0N
rw
Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw
PEDE
rw
PEAE
rw
WDIE
rw
BOE
rw
EWE
rw
EPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELOE
rw
TOOE
rw
MRAFE
rw
TEFLE
rw
TEFFE
rw
TEFNE
rw
TEFE
rw
TCFE
rw
TCE
rw
HPME
rw
RF1LE
rw
RF1FE
rw
RF1NE
rw
RF0LE
rw
RF0FE
rw
RF0NE
rw
Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

MRAFE

Bit 13: Message RAM Access Failure Enable.

TOOE

Bit 14: Timeout Occurred Enable.

ELOE

Bit 15: Error Logging Overflow Enable.

EPE

Bit 16: Error Passive Enable.

EWE

Bit 17: Warning Status Enable.

BOE

Bit 18: Bus_Off Status Enable.

WDIE

Bit 19: Watchdog Interrupt Enable.

PEAE

Bit 20: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 21: Protocol Error in Data Phase Enable.

ARAE

Bit 22: Access to Reserved Address Enable.

ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERR
rw
BERR
rw
MISC
rw
TFERR
rw
SMSG
rw
RxFIFO1
rw
RxFIFO0
rw
Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw
EINT0
rw
Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw
LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0OM
rw
F1OM
rw
ANFS
rw
ANFE
rw
RRFS
rw
RRFE
rw
Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r
FIDX
r
MSI
r
BIDX
r
Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw
F0F
rw
F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw
F0FL
rw
Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF1L
r
F1F
r
F1PI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
r
F1FL
rw
Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r
TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r
TFFL
r
Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRP
r
Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-2: Add Request.

TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-2: Cancellation Request.

TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
r
Toggle fields

TO

Bits 0-2: Transmission Occurred..

TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-2: Cancellation Finished.

TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
rw
Toggle fields

CF

Bits 0-2: Cancellation Finished Interrupt Enable.

TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
r
EFF
r
EFPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
r
EFFL
r
Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

CKDIV

FDCAN TT Trigger Memory Configuration Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDIV
rw
Toggle fields

PDIV

Bits 0-3: PDIV.

FLASH

0x40022000: Flash

5/114 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 PDKEYR
0x8 NSKEYR
0xc SECKEYR
0x10 OPTKEYR
0x14 LVEKEYR
0x20 NSSR
0x24 SECSR
0x28 NSCR
0x2c SECCR
0x30 ECCR
0x40 OPTR
0x44 NSBOOTADD0R
0x48 NSBOOTADD1R
0x4c SECBOOTADD0R
0x50 SECWM1R1
0x54 SECWM1R2
0x58 WRP1AR
0x5c WRP1BR
0x60 SECWM2R1
0x64 SECWM2R2
0x68 WRP2AR
0x6c WRP2BR
0x80 SECBB1R[1]
0x84 SECBB1R[2]
0x88 SECBB1R[3]
0x8c SECBB1R[4]
0xa0 SECBB2R[1]
0xa4 SECBB2R[2]
0xa8 SECBB2R[3]
0xac SECBB2R[4]
0xc0 SECHDPCR
0xc4 PRIVCFGR
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEN
rw
SLEEP_PD
rw
RUN_PD
rw
LATENCY
rw
Toggle fields

LATENCY

Bits 0-3: Latency.

RUN_PD

Bit 13: Flash Power-down mode during Low-power run mode.

SLEEP_PD

Bit 14: Flash Power-down mode during Low-power sleep mode.

LVEN

Bit 15: LVEN.

PDKEYR

Power down key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle fields

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

NSKEYR

Flash non-secure key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSKEYR
w
Toggle fields

NSKEYR

Bits 0-31: NSKEYR.

SECKEYR

Flash secure key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECKEYR
w
Toggle fields

SECKEYR

Bits 0-31: SECKEYR.

OPTKEYR

Flash option key register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: OPTKEYR.

LVEKEYR

Flash low voltage key register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVEKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEKEYR
w
Toggle fields

LVEKEYR

Bits 0-31: LVEKEYR.

NSSR

Flash status register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw
OPTWERR
rw
NSPGSERR
rw
NSSIZERR
rw
NSPGAERR
rw
NSWRPERR
rw
NSPROGERR
rw
NSOPERR
rw
NSEOP
rw
Toggle fields

NSEOP

Bit 0: NSEOP.

NSOPERR

Bit 1: NSOPERR.

NSPROGERR

Bit 3: NSPROGERR.

NSWRPERR

Bit 4: NSWRPERR.

NSPGAERR

Bit 5: NSPGAERR.

NSSIZERR

Bit 6: NSSIZERR.

NSPGSERR

Bit 7: NSPGSERR.

OPTWERR

Bit 13: OPTWERR.

OPTVERR

Bit 15: OPTVERR.

NSBSY

Bit 16: NSBusy.

SECSR

Flash status register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECRDERR
rw
SECPGSERR
rw
SECSIZERR
rw
SECPGAERR
rw
SECWRPERR
rw
SECPROGERR
rw
SECOPERR
rw
SECEOP
rw
Toggle fields

SECEOP

Bit 0: SECEOP.

SECOPERR

Bit 1: SECOPERR.

SECPROGERR

Bit 3: SECPROGERR.

SECWRPERR

Bit 4: SECWRPERR.

SECPGAERR

Bit 5: SECPGAERR.

SECSIZERR

Bit 6: SECSIZERR.

SECPGSERR

Bit 7: SECPGSERR.

SECRDERR

Bit 14: Secure read protection error.

SECBSY

Bit 16: SECBusy.

NSCR

Flash non-secure control register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSLOCK
rw
OPTLOCK
rw
OBL_LAUNCH
rw
NSERRIE
rw
NSEOPIE
rw
OPTSTRT
rw
NSSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSMER2
rw
NSBKER
rw
NSPNB
rw
NSMER1
rw
NSPER
rw
NSPG
rw
Toggle fields

NSPG

Bit 0: NSPG.

NSPER

Bit 1: NSPER.

NSMER1

Bit 2: NSMER1.

NSPNB

Bits 3-9: NSPNB.

NSBKER

Bit 11: NSBKER.

NSMER2

Bit 15: NSMER2.

NSSTRT

Bit 16: Options modification start.

OPTSTRT

Bit 17: Options modification start.

NSEOPIE

Bit 24: NSEOPIE.

NSERRIE

Bit 25: NSERRIE.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

NSLOCK

Bit 31: NSLOCK.

SECCR

Flash secure control register

Offset: 0x2c, size: 32, reset: 0x80000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECLOCK
rw
SECINV
rw
SECRDERRIE
rw
SECERRIE
rw
SECEOPIE
rw
SECSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECMER2
rw
SECBKER
rw
SECPNB
rw
SECMER1
rw
SECPER
rw
SECPG
rw
Toggle fields

SECPG

Bit 0: SECPG.

SECPER

Bit 1: SECPER.

SECMER1

Bit 2: SECMER1.

SECPNB

Bits 3-9: SECPNB.

SECBKER

Bit 11: SECBKER.

SECMER2

Bit 15: SECMER2.

SECSTRT

Bit 16: SECSTRT.

SECEOPIE

Bit 24: SECEOPIE.

SECERRIE

Bit 25: SECERRIE.

SECRDERRIE

Bit 26: SECRDERRIE.

SECINV

Bit 29: SECINV.

SECLOCK

Bit 31: SECLOCK.

ECCR

Flash ECC register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw
ECCC
rw
ECCD2
rw
ECCC2
rw
ECCIE
rw
SYSF_ECC
r
BK_ECC
r
ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle fields

ADDR_ECC

Bits 0-18: ECC fail address.

BK_ECC

Bit 21: BK_ECC.

SYSF_ECC

Bit 22: SYSF_ECC.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC2

Bit 28: ECCC2.

ECCD2

Bit 29: ECCD2.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZEN
rw
PA15_PUPEN
rw
nBOOT0
rw
nSWBOOT0
rw
SRAM2_RST
rw
SRAM2_PE
rw
DBANK
rw
DB256K
rw
SWAP_BANK
rw
WWDG_SW
rw
IWDG_STDBY
rw
IWDG_STOP
rw
IWDG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_SHDW
rw
nRST_STDBY
rw
nRST_STOP
rw
BOR_LEV
rw
RDP
rw
Toggle fields

RDP

Bits 0-7: Read protection level.

BOR_LEV

Bits 8-10: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRST_SHDW.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

SWAP_BANK

Bit 20: SWAP_BANK.

DB256K

Bit 21: DB256K.

DBANK

Bit 22: DBANK.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: nSWBOOT0.

nBOOT0

Bit 27: nBOOT0.

PA15_PUPEN

Bit 28: PA15_PUPEN.

TZEN

Bit 31: TZEN.

NSBOOTADD0R

Flash non-secure boot address 0 register

Offset: 0x44, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD0
w
Toggle fields

NSBOOTADD0

Bits 7-31: NSBOOTADD0.

NSBOOTADD1R

Flash non-secure boot address 1 register

Offset: 0x48, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD1
w
Toggle fields

NSBOOTADD1

Bits 7-31: NSBOOTADD1.

SECBOOTADD0R

FFlash secure boot address 0 register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBOOTADD0
w
BOOT_LOCK
rw
Toggle fields

BOOT_LOCK

Bit 0: BOOT_LOCK.

SECBOOTADD0

Bits 7-31: SECBOOTADD0.

SECWM1R1

Flash bank 1 secure watermak1 register

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM1_PSTRT
rw
Toggle fields

SECWM1_PSTRT

Bits 0-6: SECWM1_PSTRT.

SECWM1_PEND

Bits 16-22: SECWM1_PEND.

SECWM1R2

Flash secure watermak1 register 2

Offset: 0x54, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP1EN
rw
HDP1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1EN
rw
PCROP1_PSTRT
rw
Toggle fields

PCROP1_PSTRT

Bits 0-6: PCROP1_PSTRT.

PCROP1EN

Bit 15: PCROP1EN.

HDP1_PEND

Bits 16-22: HDP1_PEND.

HDP1EN

Bit 31: HDP1EN.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x58, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_PSTRT
rw
Toggle fields

WRP1A_PSTRT

Bits 0-6: WRP1A_PSTRT.

WRP1A_PEND

Bits 16-22: WRP1A_PEND.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x5c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_PSTRT
rw
Toggle fields

WRP1B_PSTRT

Bits 0-6: WRP1B_PSTRT.

WRP1B_PEND

Bits 16-22: WRP1B_PEND.

SECWM2R1

Flash secure watermak2 register

Offset: 0x60, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM2_PSTRT
rw
Toggle fields

SECWM2_PSTRT

Bits 0-6: SECWM2_PSTRT.

SECWM2_PEND

Bits 16-22: SECWM2_PEND.

SECWM2R2

Flash secure watermak2 register2

Offset: 0x64, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP2EN
rw
HDP2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2EN
rw
PCROP2_PSTRT
rw
Toggle fields

PCROP2_PSTRT

Bits 0-6: PCROP2_PSTRT.

PCROP2EN

Bit 15: PCROP2EN.

HDP2_PEND

Bits 16-22: HDP2_PEND.

HDP2EN

Bit 31: HDP2EN.

WRP2AR

Flash WPR2 area A address register

Offset: 0x68, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2A_PSTRT
rw
Toggle fields

WRP2A_PSTRT

Bits 0-6: WRP2A_PSTRT.

WRP2A_PEND

Bits 16-22: WRP2A_PEND.

WRP2BR

Flash WPR2 area B address register

Offset: 0x6c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2B_PSTRT
rw
Toggle fields

WRP2B_PSTRT

Bits 0-6: WRP2B_PSTRT.

WRP2B_PEND

Bits 16-22: WRP2B_PEND.

SECBB1R[1]

FLASH secure block based bank 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[2]

FLASH secure block based bank 1

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[3]

FLASH secure block based bank 1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[4]

FLASH secure block based bank 1

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB2R[1]

FLASH secure block based bank 2

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[2]

FLASH secure block based bank 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[3]

FLASH secure block based bank 2

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[4]

FLASH secure block based bank 2

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECHDPCR

FLASH secure HDP control register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDP2_ACCDIS
rw
HDP1_ACCDIS
rw
Toggle fields

HDP1_ACCDIS

Bit 0: HDP1_ACCDIS.

HDP2_ACCDIS

Bit 1: HDP2_ACCDIS.

PRIVCFGR

Power privilege configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

FMC

0x44020000: FMC

130/143 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR[1]
0x8 BCR[2]
0xc BTR[2]
0x10 BCR[3]
0x14 BTR[3]
0x18 BCR[4]
0x1c BTR[4]
0x20 PCSCNTR
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x94 ECCR
0x104 BWTR[1]
0x10c BWTR[2]
0x114 BWTR[3]
0x11c BWTR[4]
Toggle registers

BCR1

FMC_BCR1

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

16/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
WFDIS
rw
CCLKEN
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

Allowed values:
0: Disabled: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set
1: Enabled: The FMC_CLK is only generated during the synchronous memory access (read/write transaction)

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

Allowed values:
0: Enabled: Write FIFO enabled
1: Disabled: Write FIFO disabled

NBLSET

Bits 22-23: NBLSET.

BTR[1]

SRAM/NOR-flash chip-select timing registers for bank 1

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

BCR[2]

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, size: 32, reset: 0x000030D2, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

NBLSET

Bits 22-23: NBLSET.

BTR[2]

SRAM/NOR-flash chip-select timing registers for bank 2

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

BCR[3]

SRAM/NOR-Flash chip-select control register 3

Offset: 0x10, size: 32, reset: 0x000030D2, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

NBLSET

Bits 22-23: NBLSET.

BTR[3]

SRAM/NOR-flash chip-select timing registers for bank 3

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

BCR[4]

SRAM/NOR-Flash chip-select control register 4

Offset: 0x18, size: 32, reset: 0x000030D2, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

NBLSET

Bits 22-23: NBLSET.

BTR[4]

SRAM/NOR-flash chip-select timing registers for bank 4

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin and (BUSTRUN + 2)KCK_FMC period ≥ tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period ≥ max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

PCSCNTR

PCSCNTR

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB[4]EN
rw
CNTB[3]EN
rw
CNTB[2]EN
rw
CNTB[1]EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT
rw
Toggle fields

CSCOUNT

Bits 0-15: Chip select counter.

CNTB[1]EN

Bit 16: Counter Bank 1 enable.

CNTB[2]EN

Bit 17: Counter Bank 2 enable.

CNTB[3]EN

Bit 18: Counter Bank 3 enable.

CNTB[4]EN

Bit 19: Counter Bank 4 enable.

PCR

NAND Flash control registers

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PTYP
rw
PBKEN
rw
PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:.

Allowed values:
0: Disabled: Wait feature disabled
1: Enabled: Wait feature enabled

PBKEN

Bit 2: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

PTYP

Bit 3: Memory type.

Allowed values:
1: NANDFlash: NAND Flash

PWID

Bits 4-5: Data bus width. These bits define the external memory device width..

Allowed values:
0: Bits8: External memory device width 8 bits
1: Bits16: External memory device width 16 bits

ECCEN

Bit 6: ECC computation logic enable bit.

Allowed values:
0: Disabled: ECC logic is disabled and reset
1: Enabled: ECC logic is enabled

TCLR

Bits 9-12: CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

Allowed values: 0x0-0xf

TAR

Bits 13-16: ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

Allowed values: 0x0-0xf

ECCPS

Bits 17-19: ECC page size. These bits define the page size for the extended ECC:.

Allowed values:
0: Bytes256: ECC page size 256 bytes
1: Bytes512: ECC page size 512 bytes
2: Bytes1024: ECC page size 1024 bytes
3: Bytes2048: ECC page size 2048 bytes
4: Bytes4096: ECC page size 4096 bytes
5: Bytes8192: ECC page size 8192 bytes

SR

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle fields

IRS

Bit 0: Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

Allowed values:
0: DidNotOccur: Interrupt rising edge did not occur
1: Occurred: Interrupt rising edge occurred

ILS

Bit 1: Interrupt high-level status The flag is set by hardware and reset by software..

Allowed values:
0: DidNotOccur: Interrupt high-level did not occur
1: Occurred: Interrupt high-level occurred

IFS

Bit 2: Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

Allowed values:
0: DidNotOccur: Interrupt falling edge did not occur
1: Occurred: Interrupt falling edge occurred

IREN

Bit 3: Interrupt rising edge detection enable bit.

Allowed values:
0: Disabled: Interrupt rising edge detection request disabled
1: Enabled: Interrupt rising edge detection request enabled

ILEN

Bit 4: Interrupt high-level detection enable bit.

Allowed values:
0: Disabled: Interrupt high-level detection request disabled
1: Enabled: Interrupt high-level detection request enabled

IFEN

Bit 5: Interrupt falling edge detection enable bit.

Allowed values:
0: Disabled: Interrupt falling edge detection request disabled
1: Enabled: Interrupt falling edge detection request enabled

FEMPT

Bit 6: FIFO empty. Read-only bit that provides the status of the FIFO.

Allowed values:
0: NotEmpty: FIFO not empty
1: Empty: FIFO empty

PMEM

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw
MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw
MEMSET
rw
Toggle fields

MEMSET

Bits 0-7: Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:.

Allowed values: 0x0-0xfe

MEMWAIT

Bits 8-15: Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

Allowed values: 0x1-0xfe

MEMHOLD

Bits 16-23: Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:.

Allowed values: 0x1-0xfe

MEMHIZ

Bits 24-31: Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:.

Allowed values: 0x0-0xfe

PATT

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw
ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw
ATTSET
rw
Toggle fields

ATTSET

Bits 0-7: Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

Allowed values: 0x0-0xfe

ATTWAIT

Bits 8-15: Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

Allowed values: 0x1-0xfe

ATTHOLD

Bits 16-23: Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

Allowed values: 0x1-0xfe

ATTHIZ

Bits 24-31: Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:.

Allowed values: 0x0-0xfe

ECCR

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle fields

ECC

Bits 0-31: ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields..

Allowed values: 0x0-0xffffffff

BWTR[1]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[2]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[3]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[4]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period ≥ tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

GPIOA

0x42020000: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOB

0x42020400: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOC

0x42020800: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOD

0x42020c00: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOE

0x42021000: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOF

0x42021400: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOG

0x42021800: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GPIOH

0x42021c00: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x0000000F, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

GTZC_MPCBB1

0x40032c00: GTZC_MPCBB1

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 LCKVTR1
0x14 LCKVTR2
0x100 VCTR[0]
0x104 VCTR[1]
0x108 VCTR[2]
0x10c VCTR[3]
0x110 VCTR[4]
0x114 VCTR[5]
0x118 VCTR[6]
0x11c VCTR[7]
0x120 VCTR[8]
0x124 VCTR[9]
0x128 VCTR[10]
0x12c VCTR[11]
0x130 VCTR[12]
0x134 VCTR[13]
0x138 VCTR[14]
0x13c VCTR[15]
0x140 VCTR[16]
0x144 VCTR[17]
0x148 VCTR[18]
0x14c VCTR[19]
0x150 VCTR[20]
0x154 VCTR[21]
0x158 VCTR[22]
0x15c VCTR[23]
0x160 VCTR[24]
0x164 VCTR[25]
0x168 VCTR[26]
0x16c VCTR[27]
0x170 VCTR[28]
0x174 VCTR[29]
0x178 VCTR[30]
0x17c VCTR[31]
0x180 VCTR[32]
0x184 VCTR[33]
0x188 VCTR[34]
0x18c VCTR[35]
0x190 VCTR[36]
0x194 VCTR[37]
0x198 VCTR[38]
0x19c VCTR[39]
0x1a0 VCTR[40]
0x1a4 VCTR[41]
0x1a8 VCTR[42]
0x1ac VCTR[43]
0x1b0 VCTR[44]
0x1b4 VCTR[45]
0x1b8 VCTR[46]
0x1bc VCTR[47]
0x1c0 VCTR[48]
0x1c4 VCTR[49]
0x1c8 VCTR[50]
0x1cc VCTR[51]
0x1d0 VCTR[52]
0x1d4 VCTR[53]
0x1d8 VCTR[54]
0x1dc VCTR[55]
0x1e0 VCTR[56]
0x1e4 VCTR[57]
0x1e8 VCTR[58]
0x1ec VCTR[59]
0x1f0 VCTR[60]
0x1f4 VCTR[61]
0x1f8 VCTR[62]
0x1fc VCTR[63]
Toggle registers

CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw
INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

VCTR[0]

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[1]

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[2]

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[3]

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[4]

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[5]

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[6]

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[7]

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[8]

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[9]

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[10]

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[11]

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[12]

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[13]

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[14]

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[15]

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[16]

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[17]

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[18]

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[19]

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[20]

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[21]

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[22]

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[23]

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[24]

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[25]

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[26]

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[27]

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[28]

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[29]

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[30]

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[31]

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[32]

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[33]

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[34]

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[35]

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[36]

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[37]

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[38]

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[39]

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[40]

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[41]

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[42]

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[43]

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[44]

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[45]

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[46]

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[47]

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[48]

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[49]

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[50]

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[51]

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[52]

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[53]

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[54]

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[55]

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[56]

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[57]

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[58]

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[59]

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[60]

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[61]

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[62]

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[63]

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

GTZC_MPCBB2

0x40033000: GTZC_MPCBB2

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 LCKVTR1
0x14 LCKVTR2
0x100 VCTR[0]
0x104 VCTR[1]
0x108 VCTR[2]
0x10c VCTR[3]
0x110 VCTR[4]
0x114 VCTR[5]
0x118 VCTR[6]
0x11c VCTR[7]
0x120 VCTR[8]
0x124 VCTR[9]
0x128 VCTR[10]
0x12c VCTR[11]
0x130 VCTR[12]
0x134 VCTR[13]
0x138 VCTR[14]
0x13c VCTR[15]
0x140 VCTR[16]
0x144 VCTR[17]
0x148 VCTR[18]
0x14c VCTR[19]
0x150 VCTR[20]
0x154 VCTR[21]
0x158 VCTR[22]
0x15c VCTR[23]
0x160 VCTR[24]
0x164 VCTR[25]
0x168 VCTR[26]
0x16c VCTR[27]
0x170 VCTR[28]
0x174 VCTR[29]
0x178 VCTR[30]
0x17c VCTR[31]
0x180 VCTR[32]
0x184 VCTR[33]
0x188 VCTR[34]
0x18c VCTR[35]
0x190 VCTR[36]
0x194 VCTR[37]
0x198 VCTR[38]
0x19c VCTR[39]
0x1a0 VCTR[40]
0x1a4 VCTR[41]
0x1a8 VCTR[42]
0x1ac VCTR[43]
0x1b0 VCTR[44]
0x1b4 VCTR[45]
0x1b8 VCTR[46]
0x1bc VCTR[47]
0x1c0 VCTR[48]
0x1c4 VCTR[49]
0x1c8 VCTR[50]
0x1cc VCTR[51]
0x1d0 VCTR[52]
0x1d4 VCTR[53]
0x1d8 VCTR[54]
0x1dc VCTR[55]
0x1e0 VCTR[56]
0x1e4 VCTR[57]
0x1e8 VCTR[58]
0x1ec VCTR[59]
0x1f0 VCTR[60]
0x1f4 VCTR[61]
0x1f8 VCTR[62]
0x1fc VCTR[63]
Toggle registers

CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw
INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

VCTR[0]

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[1]

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[2]

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[3]

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[4]

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[5]

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[6]

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[7]

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[8]

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[9]

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[10]

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[11]

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[12]

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[13]

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[14]

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[15]

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[16]

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[17]

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[18]

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[19]

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[20]

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[21]

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[22]

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[23]

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[24]

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[25]

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[26]

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[27]

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[28]

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[29]

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[30]

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[31]

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[32]

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[33]

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[34]

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[35]

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[36]

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[37]

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[38]

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[39]

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[40]

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[41]

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[42]

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[43]

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[44]

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[45]

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[46]

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[47]

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[48]

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[49]

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[50]

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[51]

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[52]

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[53]

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[54]

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[55]

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[56]

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[57]

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[58]

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[59]

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[60]

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[61]

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[62]

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[63]

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

GTZC_TZIC

0x40032800: GTZC_TZIC

32/210 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IER1
0x4 IER2
0x8 IER3
0x10 SR1
0x14 SR2
0x18 SR3
0x20 FCR1
0x24 FCR2
0x28 FCR3
Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

TIM2IE

Bit 0: TIM2IE.

TIM3IE

Bit 1: TIM3IE.

TIM4IE

Bit 2: TIM4IE.

TIM5IE

Bit 3: TIM5IE.

TIM6IE

Bit 4: TIM6IE.

TIM7IE

Bit 5: TIM7IE.

WWDGIE

Bit 6: WWDGIE.

IWDGIE

Bit 7: IWDGIE.

SPI2IE

Bit 8: SPI2IE.

SPI3IE

Bit 9: SPI3IE.

USART2IE

Bit 10: USART2IE.

USART3IE

Bit 11: USART3IE.

UART4IE

Bit 12: UART4IE.

UART5IE

Bit 13: UART5IE.

I2C1IE

Bit 14: I2C1IE.

I2C2IE

Bit 15: I2C2IE.

I2C3IE

Bit 16: I2C3IE.

CRSIE

Bit 17: CRSIE.

DACIE

Bit 18: DACIE.

OPAMPIE

Bit 19: OPAMPIE.

LPTIM1IE

Bit 20: LPTIM1IE.

LPUART1IE

Bit 21: LPUART1IE.

I2C4IE

Bit 22: I2C4IE.

LPTIM2IE

Bit 23: LPTIM2IE.

LPTIM3IE

Bit 24: LPTIM3IE.

FDCAN1IE

Bit 25: FDCAN1IE.

USBFSIE

Bit 26: USBFSIE.

UCPD1IE

Bit 27: UCPD1IE.

VREFBUFIE

Bit 28: VREFBUFIE.

COMPIE

Bit 29: COMPIE.

TIM1IE

Bit 30: TIM1IE.

SPI1IE

Bit 31: SPI1IE.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

Toggle fields

TIM8IE

Bit 0: TIM8IE.

USART1IE

Bit 1: USART1IE.

TIM15IE

Bit 2: TIM15IE.

TIM16IE

Bit 3: TIM16IE.

TIM17IE

Bit 4: TIM17IE.

SAI1IE

Bit 5: SAI1IE.

SAI2IE

Bit 6: SAI2IE.

DFSDM1IE

Bit 7: DFSDM1IE.

CRCIE

Bit 8: CRCIE.

TSCIE

Bit 9: TSCIE.

ICACHEIE

Bit 10: ICACHEIE.

ADCIE

Bit 11: ADCIE.

AESIE

Bit 12: AESIE.

HASHIE

Bit 13: HASHIE.

RNGIE

Bit 14: RNGIE.

PKAIE

Bit 15: PKAIE.

SDMMC1IE

Bit 16: SDMMC1IE.

FMC_REGIE

Bit 17: FMC_REGIE.

OCTOSPI1_REGIE

Bit 18: OCTOSPI1_REGIE.

RTCIE

Bit 19: RTCIE.

PWRIE

Bit 20: PWRIE.

SYSCFGIE

Bit 21: SYSCFGIE.

DMA1IE

Bit 22: DMA1IE.

DMA2IE

Bit 23: DMA2IE.

DMAMUX1IE

Bit 24: DMAMUX1IE.

RCCIE

Bit 25: RCCIE.

FLASHIE

Bit 26: FLASHIE.

FLASH_REGIE

Bit 27: FLASH_REGIE.

EXTIIE

Bit 28: EXTIIE.

OTFDEC1IE

Bit 29: OTFDEC1IE.

IER3

TZIC interrupt enable register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

Toggle fields

TZSCIE

Bit 0: TZSCIE.

TZICIE

Bit 1: TZICIE.

MPCWM1IE

Bit 2: MPCWM1IE.

MPCWM2IE

Bit 3: MPCWM2IE.

MPCBB1IE

Bit 4: MPCBB1IE.

MPCBB1_REGIE

Bit 5: MPCBB1_REGIE.

MPCBB2IE

Bit 6: MPCBB2IE.

MPCBB2_REGIE

Bit 7: MPCBB2_REGIE.

SR1

TZIC interrupt status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

TIM2F

Bit 0: TIM2F.

TIM3F

Bit 1: TIM3F.

TIM4F

Bit 2: TIM4F.

TIM5F

Bit 3: TIM5F.

TIM6F

Bit 4: TIM6F.

TIM7F

Bit 5: TIM7F.

WWDGF

Bit 6: WWDGF.

IWDGF

Bit 7: IWDGF.

SPI2F

Bit 8: SPI2F.

SPI3F

Bit 9: SPI3F.

USART2F

Bit 10: USART2F.

USART3F

Bit 11: USART3F.

UART4F

Bit 12: UART4F.

UART5F

Bit 13: UART5F.

I2C1F

Bit 14: I2C1F.

I2C2F

Bit 15: I2C2F.

I2C3F

Bit 16: I2C3F.

CRSF

Bit 17: CRSF.

DACF

Bit 18: DACF.

OPAMPF

Bit 19: OPAMPF.

LPTIM1F

Bit 20: LPTIM1F.

LPUART1F

Bit 21: LPUART1F.

I2C4F

Bit 22: I2C4F.

LPTIM2F

Bit 23: LPTIM2F.

LPTIM3F

Bit 24: LPTIM3F.

FDCAN1F

Bit 25: FDCAN1F.

USBFSF

Bit 26: USBFSF.

UCPD1F

Bit 27: UCPD1F.

VREFBUFF

Bit 28: VREFBUFF.

COMPF

Bit 29: COMPF.

TIM1F

Bit 30: TIM1F.

SPI1F

Bit 31: SPI1F.

SR2

TZIC interrupt status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

Toggle fields

TIM8F

Bit 0: TIM8F.

USART1F

Bit 1: USART1F.

TIM15F

Bit 2: TIM15F.

TIM16F

Bit 3: TIM16F.

TIM17F

Bit 4: TIM17F.

SAI1F

Bit 5: SAI1F.

SAI2F

Bit 6: SAI2F.

DFSDM1F

Bit 7: DFSDM1F.

CRCF

Bit 8: CRCF.

TSCF

Bit 9: TSCF.

ICACHEF

Bit 10: ICACHEF.

ADCF

Bit 11: ADCF.

AESF

Bit 12: AESF.

HASHF

Bit 13: HASHF.

RNGF

Bit 14: RNGF.

PKAF

Bit 15: PKAF.

SDMMC1F

Bit 16: SDMMC1F.

FMC_REGF

Bit 17: FMC_REGF.

OCTOSPI1_REGF

Bit 18: OCTOSPI1_REGF.

RTCF

Bit 19: RTCF.

PWRF

Bit 20: PWRF.

SYSCFGF

Bit 21: SYSCFGF.

DMA1F

Bit 22: DMA1F.

DMA2F

Bit 23: DMA2F.

DMAMUX1F

Bit 24: DMAMUX1F.

RCCF

Bit 25: RCCF.

FLASHF

Bit 26: FLASHF.

FLASH_REGF

Bit 27: FLASH_REGF.

EXTIF

Bit 28: EXTIF.

OTFDEC1F

Bit 29: OTFDEC1F.

SR3

TZIC interrupt status register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGF
rw
MPCBB2F
rw
MPCBB1_REGF
rw
MPCBB1F
rw
MPCWM2F
rw
MPCWM1F
rw
TZICF
rw
TZSCF
rw
Toggle fields

TZSCF

Bit 0: TZSCF.

TZICF

Bit 1: TZICF.

MPCWM1F

Bit 2: MPCWM1F.

MPCWM2F

Bit 3: MPCWM2F.

MPCBB1F

Bit 4: MPCBB1F.

MPCBB1_REGF

Bit 5: MPCBB1_REGF.

MPCBB2F

Bit 6: MPCBB2F.

MPCBB2_REGF

Bit 7: MPCBB2_REGF.

FCR1

TZIC interrupt clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

Toggle fields

TIM2FC

Bit 0: TIM2FC.

TIM3FC

Bit 1: TIM3FC.

TIM4FC

Bit 2: TIM4FC.

TIM5FC

Bit 3: TIM5FC.

TIM6FC

Bit 4: TIM6FC.

TIM7FC

Bit 5: TIM7FC.

WWDGFC

Bit 6: WWDGFC.

IWDGFC

Bit 7: IWDGFC.

SPI2FC

Bit 8: SPI2FC.

SPI3FC

Bit 9: SPI3FC.

USART2FC

Bit 10: USART2FC.

USART3FC

Bit 11: USART3FC.

UART4FC

Bit 12: UART4FC.

UART5FC

Bit 13: UART5FC.

I2C1FC

Bit 14: I2C1FC.

I2C2FC

Bit 15: I2C2FC.

I2C3FC

Bit 16: I2C3FC.

CRSFC

Bit 17: CRSFC.

DACFC

Bit 18: DACFC.

OPAMPFC

Bit 19: OPAMPFC.

LPTIM1FC

Bit 20: LPTIM1FC.

LPUART1FC

Bit 21: LPUART1FC.

I2C4FC

Bit 22: I2C4FC.

LPTIM2FC

Bit 23: LPTIM2FC.

LPTIM3FC

Bit 24: LPTIM3FC.

FDCAN1FC

Bit 25: FDCAN1FC.

USBFSFC

Bit 26: USBFSFC.

UCPD1FC

Bit 27: UCPD1FC.

VREFBUFFC

Bit 28: VREFBUFFC.

COMPFC

Bit 29: COMPFC.

TIM1FC

Bit 30: TIM1FC.

SPI1FC

Bit 31: SPI1FC.

FCR2

TZIC interrupt clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

Toggle fields

TIM8FC

Bit 0: TIM8FC.

USART1FC

Bit 1: USART1FC.

TIM15FC

Bit 2: TIM15FC.

TIM16FC

Bit 3: TIM16FC.

TIM17FC

Bit 4: TIM17FC.

SAI1FC

Bit 5: SAI1FC.

SAI2FC

Bit 6: SAI2FC.

DFSDM1FC

Bit 7: DFSDM1FC.

CRCFC

Bit 8: CRCFC.

TSCFC

Bit 9: TSCFC.

ICACHEFC

Bit 10: ICACHEFC.

ADCFC

Bit 11: ADCFC.

AESFC

Bit 12: AESFC.

HASHFC

Bit 13: HASHFC.

RNGFC

Bit 14: RNGFC.

PKAFC

Bit 15: PKAFC.

SDMMC1FC

Bit 16: SDMMC1FC.

FMC_REGFC

Bit 17: FMC_REGFC.

OCTOSPI1_REGFC

Bit 18: OCTOSPI1_REGFC.

RTCFC

Bit 19: RTCFC.

PWRFC

Bit 20: PWRFC.

SYSCFGFC

Bit 21: SYSCFGFC.

DMA1FC

Bit 22: DMA1FC.

DMA2FC

Bit 23: DMA2FC.

DMAMUX1FC

Bit 24: DMAMUX1FC.

RCCFC

Bit 25: RCCFC.

FLASHFC

Bit 26: FLASHFC.

FLASH_REGFC

Bit 27: FLASH_REGFC.

EXTIFC

Bit 28: EXTIFC.

OTFDEC1FC

Bit 29: OTFDEC1FC.

FCR3

TZIC interrupt clear register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

Toggle fields

TZSCFC

Bit 0: TZSCFC.

TZICFC

Bit 1: TZICFC.

MPCWM1FC

Bit 2: MPCWM1FC.

MPCWM2FC

Bit 3: MPCWM2FC.

MPCBB1FC

Bit 4: MPCBB1FC.

MPCBB1_REGFC

Bit 5: MPCBB1_REGFC.

MPCBB2FC

Bit 6: MPCBB2FC.

MPCBB2_REGFC

Bit 7: MPCBB2_REGFC.

GTZC_TZSC

0x40032400: GTZC_TZSC

0/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 SECCFGR1
0x14 SECCFGR2
0x20 PRIVCFGR1
0x24 PRIVCFGR2
0x30 MPCWM1_NSWMR1
0x34 MPCWM1_NSWMR2
0x38 MPCWM2_NSWMR1
0x3c MPCWM2_NSWMR2
0x40 MPCWM3_NSWMR1
Toggle registers

CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

TIM2SEC

Bit 0: TIM2SEC.

TIM3SEC

Bit 1: TIM3SEC.

TIM4SEC

Bit 2: TIM4SEC.

TIM5SEC

Bit 3: TIM5SEC.

TIM6SEC

Bit 4: TIM6SEC.

TIM7SEC

Bit 5: TIM7SEC.

WWDGSEC

Bit 6: WWDGSEC.

IWDGSEC

Bit 7: IWDGSEC.

SPI2SEC

Bit 8: SPI2SEC.

SPI3SEC

Bit 9: SPI3SEC.

USART2SEC

Bit 10: USART2SEC.

USART3SEC

Bit 11: USART3SEC.

UART4SEC

Bit 12: UART4SEC.

UART5SEC

Bit 13: UART5SEC.

I2C1SEC

Bit 14: I2C1SEC.

I2C2SEC

Bit 15: I2C2SEC.

I2C3SEC

Bit 16: I2C3SEC.

CRSSEC

Bit 17: CRSSEC.

DACSEC

Bit 18: DACSEC.

OPAMPSEC

Bit 19: OPAMPSEC.

LPTIM1SEC

Bit 20: LPTIM1SEC.

LPUART1SEC

Bit 21: LPUART1SEC.

I2C4SEC

Bit 22: I2C4SEC.

LPTIM2SEC

Bit 23: LPTIM2SEC.

LPTIM3SEC

Bit 24: LPTIM3SEC.

FDCAN1SEC

Bit 25: FDCAN1SEC.

USBFSSEC

Bit 26: USBFSSEC.

UCPD1SEC

Bit 27: UCPD1SEC.

VREFBUFSEC

Bit 28: VREFBUFSEC.

COMPSEC

Bit 29: COMPSEC.

TIM1SEC

Bit 30: TIM1SEC.

SPI1SEC

Bit 31: SPI1SEC.

SECCFGR2

TZSC secure configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

Toggle fields

TIM8SEC

Bit 0: TIM8SEC.

USART1SEC

Bit 1: USART1SEC.

TIM15SEC

Bit 2: TIM15SEC.

TIM16SEC

Bit 3: TIM16SEC.

TIM17SEC

Bit 4: TIM17SEC.

SAI1SEC

Bit 5: SAI1SEC.

SAI2SEC

Bit 6: SAI2SEC.

DFSDM1SEC

Bit 7: DFSDM1SEC.

CRCSEC

Bit 8: CRCSEC.

TSCSEC

Bit 9: TSCSEC.

ICACHESEC

Bit 10: ICACHESEC.

ADCSEC

Bit 11: ADCSEC.

AESSEC

Bit 12: AESSEC.

HASHSEC

Bit 13: HASHSEC.

RNGSEC

Bit 14: RNGSEC.

PKASEC

Bit 15: PKASEC.

SDMMC1SEC

Bit 16: SDMMC1SEC.

FSMC_REGSEC

Bit 17: FSMC_REGSEC.

OCTOSPI1_REGSEC

Bit 18: OCTOSPI1_REGSEC.

PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

TIM2PRIV

Bit 0: TIM2PRIV.

TIM3PRIV

Bit 1: TIM3PRIV.

TIM4PRIV

Bit 2: TIM4PRIV.

TIM5PRIV

Bit 3: TIM5PRIV.

TIM6PRIV

Bit 4: TIM6PRIV.

TIM7PRIV

Bit 5: TIM7PRIV.

WWDGPRIV

Bit 6: WWDGPRIV.

IWDGPRIV

Bit 7: IWDGPRIV.

SPI2PRIV

Bit 8: SPI2PRIV.

SPI3PRIV

Bit 9: SPI3PRIV.

USART2PRIV

Bit 10: USART2PRIV.

USART3PRIV

Bit 11: USART3PRIV.

UART4PRIV

Bit 12: UART4PRIV.

UART5PRIV

Bit 13: UART5PRIV.

I2C1PRIV

Bit 14: I2C1PRIV.

I2C2PRIV

Bit 15: I2C2PRIV.

I2C3PRIV

Bit 16: I2C3PRIV.

CRSPRIV

Bit 17: CRSPRIV.

DACPRIV

Bit 18: DACPRIV.

OPAMPPRIV

Bit 19: OPAMPPRIV.

LPTIM1PRIV

Bit 20: LPTIM1PRIV.

LPUART1PRIV

Bit 21: LPUART1PRIV.

I2C4PRIV

Bit 22: I2C4PRIV.

LPTIM2PRIV

Bit 23: LPTIM2PRIV.

LPTIM3PRIV

Bit 24: LPTIM3PRIV.

FDCAN1PRIV

Bit 25: FDCAN1PRIV.

USBFSPRIV

Bit 26: USBFSPRIV.

UCPD1PRIV

Bit 27: UCPD1PRIV.

VREFBUFPRIV

Bit 28: VREFBUFPRIV.

COMPPRIV

Bit 29: COMPPRIV.

TIM1PRIV

Bit 30: TIM1PRIV.

SPI1PRIV

Bit 31: SPI1PRIV.

PRIVCFGR2

TZSC privilege configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

Toggle fields

TIM8PRIV

Bit 0: TIM8PRIV.

USART1PRIV

Bit 1: USART1PRIV.

TIM15PRIV

Bit 2: TIM15PRIV.

TIM16PRIV

Bit 3: TIM16PRIV.

TIM17PRIV

Bit 4: TIM17PRIV.

SAI1PRIV

Bit 5: SAI1PRIV.

SAI2PRIV

Bit 6: SAI2PRIV.

DFSDM1PRIV

Bit 7: DFSDM1PRIV.

CRCPRIV

Bit 8: CRCPRIV.

TSCPRIV

Bit 9: TSCPRIV.

ICACHEPRIV

Bit 10: ICACHEPRIV.

ADCPRIV

Bit 11: ADCPRIV.

AESPRIV

Bit 12: AESPRIV.

HASHPRIV

Bit 13: HASHPRIV.

RNGPRIV

Bit 14: RNGPRIV.

PKAPRIV

Bit 15: PKAPRIV.

SDMMC1PRIV

Bit 16: SDMMC1PRIV.

FSMC_REGPRIV

Bit 17: FSMC_REGPRIV.

OCTOSPI1_REGPRIV

Bit 18: OCTOSPI1_REGRIV.

MPCWM1_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM1_NSWMR2

TZSC external memory non-secure watermark register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM2_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM2_NSWMR2

TZSC external memory non-secure watermark register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM3_NSWMR1

TZSC external memory non-secure watermark register 2

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

HASH

0x420c0400: Hash processor

17/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HRA0
0x10 HRA1
0x14 HRA2
0x18 HRA3
0x1c HRA4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x310 HR0
0x314 HR1
0x318 HR2
0x31c HR3
0x320 HR4
0x324 HR5
0x328 HR6
0x32c HR7
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw
LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw
DINNE
r
NBW
r
ALGO0
rw
MODE
rw
DATATYPE
rw
DMAE
rw
INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: Algorithm selection.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
rw
NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HRA0

HASH aliased digest register 0

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HRA1

HASH aliased digest register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HRA2

HASH aliased digest register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HRA3

HASH aliased digest register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HRA4

HASH aliased digest register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw
DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
DMAS
r
DCIS
rw
DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR0
rw
Toggle fields

CSR0

Bits 0-31: CSR0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR1
rw
Toggle fields

CSR1

Bits 0-31: CSR1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR2
rw
Toggle fields

CSR2

Bits 0-31: CSR2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR3
rw
Toggle fields

CSR3

Bits 0-31: CSR3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR4
rw
Toggle fields

CSR4

Bits 0-31: CSR4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR5
rw
Toggle fields

CSR5

Bits 0-31: CSR5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR6
rw
Toggle fields

CSR6

Bits 0-31: CSR6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR7
rw
Toggle fields

CSR7

Bits 0-31: CSR7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR8
rw
Toggle fields

CSR8

Bits 0-31: CSR8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR9
rw
Toggle fields

CSR9

Bits 0-31: CSR9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR10
rw
Toggle fields

CSR10

Bits 0-31: CSR10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR11
rw
Toggle fields

CSR11

Bits 0-31: CSR11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR12
rw
Toggle fields

CSR12

Bits 0-31: CSR12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR13
rw
Toggle fields

CSR13

Bits 0-31: CSR13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR14
rw
Toggle fields

CSR14

Bits 0-31: CSR14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR15
rw
Toggle fields

CSR15

Bits 0-31: CSR15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR16
rw
Toggle fields

CSR16

Bits 0-31: CSR16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR17
rw
Toggle fields

CSR17

Bits 0-31: CSR17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR18
rw
Toggle fields

CSR18

Bits 0-31: CSR18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR19
rw
Toggle fields

CSR19

Bits 0-31: CSR19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR20
rw
Toggle fields

CSR20

Bits 0-31: CSR20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR21
rw
Toggle fields

CSR21

Bits 0-31: CSR21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR22
rw
Toggle fields

CSR22

Bits 0-31: CSR22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR23
rw
Toggle fields

CSR23

Bits 0-31: CSR23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR24
rw
Toggle fields

CSR24

Bits 0-31: CSR24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR25
rw
Toggle fields

CSR25

Bits 0-31: CSR25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR26
rw
Toggle fields

CSR26

Bits 0-31: CSR26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR27
rw
Toggle fields

CSR27

Bits 0-31: CSR27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR28
rw
Toggle fields

CSR28

Bits 0-31: CSR28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR29
rw
Toggle fields

CSR29

Bits 0-31: CSR29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR30
rw
Toggle fields

CSR30

Bits 0-31: CSR30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR31
rw
Toggle fields

CSR31

Bits 0-31: CSR31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR32
rw
Toggle fields

CSR32

Bits 0-31: CSR32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR33
rw
Toggle fields

CSR33

Bits 0-31: CSR33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR34
rw
Toggle fields

CSR34

Bits 0-31: CSR34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR35
rw
Toggle fields

CSR35

Bits 0-31: CSR35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR36
rw
Toggle fields

CSR36

Bits 0-31: CSR36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR37
rw
Toggle fields

CSR37

Bits 0-31: CSR37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR38
rw
Toggle fields

CSR38

Bits 0-31: CSR38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR39
rw
Toggle fields

CSR39

Bits 0-31: CSR39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR40
rw
Toggle fields

CSR40

Bits 0-31: CSR40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR41
rw
Toggle fields

CSR41

Bits 0-31: CSR41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR42
rw
Toggle fields

CSR42

Bits 0-31: CSR42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR43
rw
Toggle fields

CSR43

Bits 0-31: CSR43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR44
rw
Toggle fields

CSR44

Bits 0-31: CSR44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR45
rw
Toggle fields

CSR45

Bits 0-31: CSR45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR46
rw
Toggle fields

CSR46

Bits 0-31: CSR46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR47
rw
Toggle fields

CSR47

Bits 0-31: CSR47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR48
rw
Toggle fields

CSR48

Bits 0-31: CSR48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR49
rw
Toggle fields

CSR49

Bits 0-31: CSR49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR50
rw
Toggle fields

CSR50

Bits 0-31: CSR50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR51
rw
Toggle fields

CSR51

Bits 0-31: CSR51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR52
rw
Toggle fields

CSR52

Bits 0-31: CSR52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR53
rw
Toggle fields

CSR53

Bits 0-31: CSR53.

HR0

digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

digest register 4

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

HR5

supplementary digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HR6

supplementary digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HR7

supplementary digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

I2C1

0x40005400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C2

0x40005800: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C3

0x40005c00: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

I2C4

0x40008400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

ICACHE

0x40030400: ICache

5/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 IER
0xc FCR
0x10 HMONR
0x14 MMONR
0x20 CRR[0]
0x24 CRR[1]
0x28 CRR[2]
0x2c CRR[3]
Toggle registers

CR

ICACHE control register

Offset: 0x0, size: 32, reset: 0x00000004, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISSMRST
rw
HITMRST
rw
MISSMEN
rw
HITMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAYSEL
rw
CACHEINV
rw
EN
rw
Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

WAYSEL

Bit 2: WAYSEL.

HITMEN

Bit 16: HITMEN.

MISSMEN

Bit 17: MISSMEN.

HITMRST

Bit 18: HITMRST.

MISSMRST

Bit 19: MISSMRST.

SR

ICACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRF
r
BSYENDF
r
BUSYF
r
Toggle fields

BUSYF

Bit 0: BUSYF.

BSYENDF

Bit 1: BSYENDF.

ERRF

Bit 2: ERRF.

IER

ICACHE interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
BSYENDIE
rw
Toggle fields

BSYENDIE

Bit 1: BSYENDIE.

ERRIE

Bit 2: ERRIE.

FCR

ICACHE flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CERRF
w
CBSYENDF
w
Toggle fields

CBSYENDF

Bit 1: CBSYENDF.

CERRF

Bit 2: CERRF.

HMONR

ICACHE hit monitor register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HITMON
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HITMON
r
Toggle fields

HITMON

Bits 0-31: HITMON.

MMONR

ICACHE miss monitor register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISSMON
r
Toggle fields

MISSMON

Bits 0-15: MISSMON.

CRR[0]

ICACHE region configuration register

Offset: 0x20, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[1]

ICACHE region configuration register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[2]

ICACHE region configuration register

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[3]

ICACHE region configuration register

Offset: 0x2c, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

IWDG

0x40003000: Independent watchdog

3/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) KR
0x4 (16-bit) PR
0x8 (16-bit) RLR
0xc (16-bit) SR
0x10 (16-bit) WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 16, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r
RVU
r
PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

LPTIM1

0x40007c00: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r
UE
r
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw
UEIE
rw
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw
RSTARE
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw
OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

LPTIM2

0x40009400: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r
UE
r
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw
UEIE
rw
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw
RSTARE
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw
OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

LPTIM3

0x40009800: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r
UE
r
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw
UEIE
rw
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw
RSTARE
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw
OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

LPUART1

0x40008000: Universal synchronous asynchronous receiver transmitter

84/84 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: DEDT.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: DEAT.

Allowed values: 0x0-0x1f

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
STOP
rw
ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bit

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
HDSEL
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

Allowed values: 0x0-0xfffff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
Toggle fields

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: TXFRQ.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r
CTSIF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w1c
TCCF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div6: /6
4: Div8: /8
5: Div10: /10
6: Div12: /12
7: Div16: /16
8: Div32: /32
9: Div64: /64
10: Div128: /128
11: Div256: /256

OCTOSPI1

0x44021000: OctoSPI

0/97 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x14 DCR4
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x140 WPCCR
0x148 WPTCR
0x150 WPIR
0x160 WPABR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw
PMM
rw
APMS
rw
TOIE
rw
SMIE
rw
FTIE
rw
TCIE
rw
TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw
FSEL
rw
DQM
rw
TCEN
rw
DMAEN
rw
ABORT
rw
EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw
DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw
DLYBYP
rw
FRCK
rw
CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

DLYBYP

Bit 3: Delay block bypass.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-25: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CSBOUND

Bits 16-20: CS boundary.

DCR4

device configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFRESH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw
Toggle fields

REFRESH

Bits 0-31: REFRESH.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
rw
BUSY
rw
TOF
rw
SMF
rw
FTF
rw
TCF
rw
TEF
rw
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w
CSMF
w
CTCF
w
CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

CCR

communication configuration

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WPCCR

wrap communication configuration register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPTCR

wrap timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPIR

wrap instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPABR

wrap alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WCCR

WCCR

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: IMODE.

IDTR

Bit 3: IDTR.

ISIZE

Bits 4-5: ISIZE.

ADMODE

Bits 8-10: ADMODE.

ADDTR

Bit 11: ADDTR.

ADSIZE

Bits 12-13: ADSIZE.

ABMODE

Bits 16-18: ABMODE.

ABDTR

Bit 19: ABDTR.

ABSIZE

Bits 20-21: ABSIZE.

DMODE

Bits 24-26: DMODE.

DDTR

Bit 27: DDTR.

DQSE

Bit 29: DQSE.

WTCR

WTCR

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: DCYC.

WIR

WIR

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

HLCR

HyperBus latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw
WZL
rw
LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

OPAMP

0x40007800: Operational amplifiers

0/29 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OPAMP1_CSR
0x4 OPAMP1_OTR
0x8 OPAMP1_LPOTR
0x10 OPAMP2_CRS
0x14 OPAMP2_OTR
0x18 OPAMP2_LPOTR
Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw
USERTRIM
rw
CALSEL
rw
CALON
rw
VP_SEL
rw
VM_SEL
rw
PGA_GAIN
rw
OPAMODE
rw
OPALPM
rw
OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPA_RANGE

Bit 31: Operational amplifier power supply range for stability.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-powe mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CRS

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw
USERTRIM
rw
CALSEL
rw
CALON
rw
VP_SEL
rw
VM_SEL
rw
PGA_GAIN
rw
OPAMODE
rw
OPALPM
rw
OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OTFDEC1

0x420c5000: On-The-Fly Decryption engine

7/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x20 R1CFGR
0x24 R1STARTADDR
0x28 R1ENDADDR
0x2c R1NONCER0
0x30 R1NONCER1
0x34 R1KEYR0
0x38 R1KEYR1
0x3c R1KEYR2
0x40 R1KEYR3
0x50 R2CFGR
0x54 R2STARTADDR
0x58 R2ENDADDR
0x5c R2NONCER0
0x60 R2NONCER1
0x64 R2KEYR0
0x68 R2KEYR1
0x6c R2KEYR2
0x70 R2KEYR3
0x80 R3CFGR
0x84 R3STARTADDR
0x88 R3ENDADDR
0x8c R3NONCER0
0x90 R3NONCER1
0x94 R3KEYR0
0x98 R3KEYR1
0x9c R3KEYR2
0xa0 R3KEYR3
0xb0 R4CFGR
0xb4 R4STARTADDR
0xb8 R4ENDADDR
0xbc R4NONCER0
0xc0 R4NONCER1
0xc4 R4KEYR0
0xc8 R4KEYR1
0xcc R4KEYR2
0xd0 R4KEYR3
0x300 ISR
0x304 ICR
0x308 IER
Toggle registers

CR

OTFDEC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENC
rw
Toggle fields

ENC

Bit 0: Encryption mode bit.

R1CFGR

OTFDEC region x configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R1STARTADDR

OTFDEC region x start address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R1ENDADDR

OTFDEC region x end address register

Offset: 0x28, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R1NONCER0

OTFDEC region x nonce register 0

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R1NONCER1

OTFDEC region x nonce register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce.

R1KEYR0

OTFDEC region x key register 0

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR1

OTFDEC region x key register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR2

OTFDEC region x key register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR3

OTFDEC region x key register 3

Offset: 0x40, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2CFGR

OTFDEC region x configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R2STARTADDR

OTFDEC region x start address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R2ENDADDR

OTFDEC region x end address register

Offset: 0x58, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R2NONCER0

OTFDEC region x nonce register 0

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R2NONCER1

OTFDEC region x nonce register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce, bits [63:32]REGx_NONCE[63:32].

R2KEYR0

OTFDEC region x key register 0

Offset: 0x64, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR1

OTFDEC region x key register 1

Offset: 0x68, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR2

OTFDEC region x key register 2

Offset: 0x6c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY_
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY_
w
Toggle fields

REGx_KEY_

Bits 0-31: REGx_KEY.

R2KEYR3

OTFDEC region x key register 3

Offset: 0x70, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3CFGR

OTFDEC region x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R3STARTADDR

OTFDEC region x start address register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R3ENDADDR

OTFDEC region x end address register

Offset: 0x88, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R3NONCER0

OTFDEC region x nonce register 0

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R3NONCER1

OTFDEC region x nonce register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R3KEYR0

OTFDEC region x key register 0

Offset: 0x94, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR1

OTFDEC region x key register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR2

OTFDEC region x key register 2

Offset: 0x9c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR3

OTFDEC region x key register 3

Offset: 0xa0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4CFGR

OTFDEC region x configuration register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R4STARTADDR

OTFDEC region x start address register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R4ENDADDR

OTFDEC region x end address register

Offset: 0xb8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R4NONCER0

OTFDEC region x nonce register 0

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4NONCER1

OTFDEC region x nonce register 1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4KEYR0

OTFDEC region x key register 0

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR1

OTFDEC region x key register 1

Offset: 0xc8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR2

OTFDEC region x key register 2

Offset: 0xcc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR3

OTFDEC region x key register 3

Offset: 0xd0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

ISR

OTFDEC interrupt status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
r
XONEIF
r
SEIF
r
Toggle fields

SEIF

Bit 0: Security Error Interrupt Flag status.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag status.

KEIF

Bit 2: Key Error Interrupt Flag status.

ICR

OTFDEC interrupt clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
w
XONEIF
w
SEIF
w
Toggle fields

SEIF

Bit 0: SEIF.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag clear.

KEIF

Bit 2: KEIF.

IER

OTFDEC interrupt enable register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIE
rw
XONEIE
rw
SEIE
rw
Toggle fields

SEIE

Bit 0: Security Error Interrupt Enable.

XONEIE

Bit 1: XONEIE.

KEIE

Bit 2: KEIE.

PKA

0x420c2000: PKA

4/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 CLRFR
Toggle registers

CR

PKA control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRIE
rw
RAMERRIE
rw
PROCENDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw
START
rw
EN
rw
Toggle fields

EN

Bit 0: PKA Enable.

START

Bit 1: Start the operation.

MODE

Bits 8-13: PKA operation code.

PROCENDIE

Bit 17: End of operation interrupt enable.

RAMERRIE

Bit 19: RAM error interrupt enable.

ADDRERRIE

Bit 20: Address error interrupt enable.

SR

PKA status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRF
r
RAMERRF
r
PROCENDF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BUSY

Bit 16: PKA operation in progress.

PROCENDF

Bit 17: PKA end of operation flag.

RAMERRF

Bit 19: PKA ram error flag.

ADDRERRF

Bit 20: address er flag.

CLRFR

PKA clear flag register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRFC
w
RAMERRFC
w
PROCENDFC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PROCENDFC

Bit 17: clear PKA end of operation flag.

RAMERRFC

Bit 19: CLEAR PKA RAM ERROR FLAG.

ADDRERRFC

Bit 20: clear address error flag.

PWR

0x40007000: Power control

17/322 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc CR4
0x10 SR1
0x14 SR2
0x18 SCR
0x20 PUCRA
0x24 PDCRA
0x28 PUCRB
0x2c PDCRB
0x30 PUCRC
0x34 PDCRC
0x38 PUCRD
0x3c PDCRD
0x40 PUCRE
0x44 PDCRE
0x48 PUCRF
0x4c PDCRF
0x50 PUCRG
0x54 PDCRG
0x58 PUCRH
0x5c PDCRH
0x78 SECCFGR
0x80 PRIVCFGR
Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000400, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw
VOS
rw
DBP
rw
LPMS
rw
Toggle fields

LPMS

Bits 0-2: Low-power mode selection.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USV
rw
IOSV
rw
PVME4
rw
PVME3
rw
PVME2
rw
PVME1
rw
PLS
rw
PVDE
rw
Toggle fields

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME2

Bit 5: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

PVME4

Bit 7: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V.

IOSV

Bit 9: VDDIO2 Independent I/Os supply valid.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCPD_DBDIS
rw
UCPD_STDBY
rw
ULPMEN
rw
APC
rw
RRS
rw
EWUP5
rw
EWUP4
rw
EWUP3
rw
EWUP2
rw
EWUP1
rw
Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

RRS

Bits 8-9: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

ULPMEN

Bit 11: ULPMEN.

UCPD_STDBY

Bit 13: UCPD_STDBY.

UCPD_DBDIS

Bit 14: UCPD_DBDIS.

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSLPEN
rw
SMPSFSTEN
rw
EXTSMPSEN
rw
SMPSBYP
rw
VBRS
rw
VBE
rw
WUPP5
rw
WUPP4
rw
WUPP3
rw
WUPP2
rw
WUPP1
rw
Toggle fields

WUPP1

Bit 0: Wakeup pin WKUP1 polarity.

WUPP2

Bit 1: Wakeup pin WKUP2 polarity.

WUPP3

Bit 2: Wakeup pin WKUP3 polarity.

WUPP4

Bit 3: Wakeup pin WKUP4 polarity.

WUPP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SMPSBYP

Bit 12: SMPSBYP.

EXTSMPSEN

Bit 13: EXTSMPSEN.

SMPSFSTEN

Bit 14: SMPSFSTEN.

SMPSLPEN

Bit 15: SMPSLPEN.

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSHPRDY
r
EXTSMPSRDY
r
SMPSBYPRDY
r
SBF
r
WUF5
r
WUF4
r
WUF3
r
WUF2
r
WUF1
r
Toggle fields

WUF1

Bit 0: Wakeup flag 1.

WUF2

Bit 1: Wakeup flag 2.

WUF3

Bit 2: Wakeup flag 3.

WUF4

Bit 3: Wakeup flag 4.

WUF5

Bit 4: Wakeup flag 5.

SBF

Bit 8: Standby flag.

SMPSBYPRDY

Bit 12: SMPSBYPRDY.

EXTSMPSRDY

Bit 13: EXTSMPSRDY.

SMPSHPRDY

Bit 15: SMPSHPRDY.

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO4
r
PVMO3
r
PVMO2
r
PVMO1
r
PVDO
r
VOSF
r
REGLPF
r
REGLPS
r
Toggle fields

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO2

Bit 13: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

PVMO4

Bit 15: Peripheral voltage monitoring output: VDDA vs. 2.2 V.

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSBF
w
CWUF5
w
CWUF4
w
CWUF3
w
CWUF2
w
CWUF1
w
Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CSBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PU5

Bit 5: Port E pull-up bit y (y=0..15).

PU6

Bit 6: Port E pull-up bit y (y=0..15).

PU7

Bit 7: Port E pull-up bit y (y=0..15).

PU8

Bit 8: Port E pull-up bit y (y=0..15).

PU9

Bit 9: Port E pull-up bit y (y=0..15).

PU10

Bit 10: Port E pull-up bit y (y=0..15).

PU11

Bit 11: Port E pull-up bit y (y=0..15).

PU12

Bit 12: Port E pull-up bit y (y=0..15).

PU13

Bit 13: Port E pull-up bit y (y=0..15).

PU14

Bit 14: Port E pull-up bit y (y=0..15).

PU15

Bit 15: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PD5

Bit 5: Port E pull-down bit y (y=0..15).

PD6

Bit 6: Port E pull-down bit y (y=0..15).

PD7

Bit 7: Port E pull-down bit y (y=0..15).

PD8

Bit 8: Port E pull-down bit y (y=0..15).

PD9

Bit 9: Port E pull-down bit y (y=0..15).

PD10

Bit 10: Port E pull-down bit y (y=0..15).

PD11

Bit 11: Port E pull-down bit y (y=0..15).

PD12

Bit 12: Port E pull-down bit y (y=0..15).

PD13

Bit 13: Port E pull-down bit y (y=0..15).

PD14

Bit 14: Port E pull-down bit y (y=0..15).

PD15

Bit 15: Port E pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PU3

Bit 3: Port F pull-up bit y (y=0..15).

PU4

Bit 4: Port F pull-up bit y (y=0..15).

PU5

Bit 5: Port F pull-up bit y (y=0..15).

PU6

Bit 6: Port F pull-up bit y (y=0..15).

PU7

Bit 7: Port F pull-up bit y (y=0..15).

PU8

Bit 8: Port F pull-up bit y (y=0..15).

PU9

Bit 9: Port F pull-up bit y (y=0..15).

PU10

Bit 10: Port F pull-up bit y (y=0..15).

PU11

Bit 11: Port F pull-up bit y (y=0..15).

PU12

Bit 12: Port F pull-up bit y (y=0..15).

PU13

Bit 13: Port F pull-up bit y (y=0..15).

PU14

Bit 14: Port F pull-up bit y (y=0..15).

PU15

Bit 15: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

PD3

Bit 3: Port F pull-down bit y (y=0..15).

PD4

Bit 4: Port F pull-down bit y (y=0..15).

PD5

Bit 5: Port F pull-down bit y (y=0..15).

PD6

Bit 6: Port F pull-down bit y (y=0..15).

PD7

Bit 7: Port F pull-down bit y (y=0..15).

PD8

Bit 8: Port F pull-down bit y (y=0..15).

PD9

Bit 9: Port F pull-down bit y (y=0..15).

PD10

Bit 10: Port F pull-down bit y (y=0..15).

PD11

Bit 11: Port F pull-down bit y (y=0..15).

PD12

Bit 12: Port F pull-down bit y (y=0..15).

PD13

Bit 13: Port F pull-down bit y (y=0..15).

PD14

Bit 14: Port F pull-down bit y (y=0..15).

PD15

Bit 15: Port F pull-down bit y (y=0..15).

PUCRG

Power Port G pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRG

Power Port G pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

SECCFGR

Power secure configuration register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APCSEC
rw
VBSEC
rw
VDMSEC
rw
LPMSEC
rw
WUP5SEC
rw
WUP4SEC
rw
WUP3SEC
rw
WUP2SEC
rw
WUP1SEC
rw
Toggle fields

WUP1SEC

Bit 0: WKUP1 pin security.

WUP2SEC

Bit 1: WKUP2 pin security.

WUP3SEC

Bit 2: WKUP3 pin security.

WUP4SEC

Bit 3: WKUP4 pin security.

WUP5SEC

Bit 4: WKUP5 pin security.

LPMSEC

Bit 8: LPMSEC.

VDMSEC

Bit 9: VDMSEC.

VBSEC

Bit 10: VBSEC.

APCSEC

Bit 11: APCSEC.

PRIVCFGR

Power privilege configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

RCC

0x40021000: Reset and clock control

245/421 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc PLLCFGR
0x10 PLLSAI1CFGR
0x14 PLLSAI2CFGR
0x18 CIER
0x1c CIFR
0x20 CICR
0x28 AHB1RSTR
0x2c AHB2RSTR
0x30 AHB3RSTR
0x38 APB1RSTR1
0x3c APB1RSTR2
0x40 APB2RSTR
0x48 AHB1ENR
0x4c AHB2ENR
0x50 AHB3ENR
0x58 APB1ENR1
0x5c APB1ENR2
0x60 APB2ENR
0x68 AHB1SMENR
0x6c AHB2SMENR
0x70 AHB3SMENR
0x78 APB1SMENR1
0x7c APB1SMENR2
0x80 APB2SMENR
0x88 CCIPR1
0x90 BDCR
0x94 CSR
0x98 CRRCR
0x9c CCIPR2
0xb8 SECCFGR
0xbc SECSR
0xe8 AHB1SECSR
0xec AHB2SECSR
0xf0 AHB3SECSR
0xf8 APB1SECSR1
0xfc APB1SECSR2
0x100 APB2SECSR
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000063, access: Unspecified

11/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
PLLSAI2RDY
r
PLLSAI2ON
rw
PLLSAI1RDY
r
PLLSAI1ON
rw
PLLRDY
r
PLLON
rw
CSSON
w
HSEBYP
rw
HSERDY
r
HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIASFS
rw
HSIRDY
r
HSIKERON
rw
HSION
rw
MSIRANGE
rw
MSIRGSEL
w
MSIPLLEN
rw
MSIRDY
r
MSION
rw
Toggle fields

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI clock range selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSIASFS

Bit 11: HSI automatic start from Stop.

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE crystal oscillator bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock security system enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: Main PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: Main PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI2ON

Bit 28: SAI2 PLL enable.

PLLSAI2RDY

Bit 29: SAI2 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PRIV

Bit 31: PRIV.

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw
HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw
MSICAL
r
Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
r
MCOSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw
PPRE2
rw
PPRE1
rw
HPRE
rw
SWS
r
SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: MSI: MSI selected as system clock
1: HSI: HSI selected as system clock
2: HSE: HSE selected as system clock
3: PLL: PLL selected as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI: HSI oscillator used as system clock
2: HSE: HSE used as system clock
3: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

Allowed values:
0: MSI: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI: HSI oscillator selected as wakeup from stop clock and CSS backup clock

MCOSEL

Bits 24-27: Microcontroller clock output.

Allowed values:
0: None: MCO output disabled, no clock on MCO
1: SYSCLK: SYSCLK system clock selected
2: MSI: MSI clock selected
3: HSI: HSI clock selected
4: HSE: HSE clock selected
5: PLL: Main PLL clock selected
6: LSI: LSI clock selected
7: LSE: LSE clock selected
8: HSI48: Internal HSI48 clock selected

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: MCO divided by 1
1: Div2: MCO divided by 2
2: Div4: MCO divided by 4
3: Div8: MCO divided by 8
4: Div16: MCO divided by 16

PLLCFGR

PLL configuration register

Offset: 0xc, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV
rw
PLLR
rw
PLLREN
rw
PLLQ
rw
PLLQEN
rw
PLLP
rw
PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw
PLLM
rw
PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-7: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLSAI3CLK output enable.

PLLP

Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).

PLLQEN

Bit 20: Main PLL PLLUSB1CLK output enable.

PLLQ

Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).

PLLREN

Bit 24: Main PLL PLLCLK output enable.

PLLR

Bits 25-26: Main PLL division factor for PLLCLK (system clock).

PLLPDIV

Bits 27-31: Main PLL division factor for PLLSAI2CLK.

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1PDIV
rw
PLLSAI1R
rw
PLLSAI1REN
rw
PLLSAI1Q
rw
PLLSAI1QEN
rw
PLLSAI1P
rw
PLLSAI1PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI1N
rw
PLLSAI1M
rw
PLLSAI1SRC
rw
Toggle fields

PLLSAI1SRC

Bits 0-1: PLLSAI1SRC.

PLLSAI1M

Bits 4-7: Division factor for PLLSAI1 input clock.

PLLSAI1N

Bits 8-14: SAI1PLL multiplication factor for VCO.

PLLSAI1PEN

Bit 16: SAI1PLL PLLSAI1CLK output enable.

PLLSAI1P

Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).

PLLSAI1QEN

Bit 20: SAI1PLL PLLUSB2CLK output enable.

PLLSAI1Q

Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).

PLLSAI1REN

Bit 24: PLLSAI1 PLLADC1CLK output enable.

PLLSAI1R

Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).

PLLSAI1PDIV

Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.

PLLSAI2CFGR

PLLSAI2 configuration register

Offset: 0x14, size: 32, reset: 0x00001000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2PDIV
rw
PLLSAI2P
rw
PLLSAI2PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2N
rw
PLLSAI2M
rw
PLLSAI2SRC
rw
Toggle fields

PLLSAI2SRC

Bits 0-1: PLLSAI2SRC.

PLLSAI2M

Bits 4-7: Division factor for PLLSAI2 input clock.

PLLSAI2N

Bits 8-14: SAI2PLL multiplication factor for VCO.

PLLSAI2PEN

Bit 16: SAI2PLL PLLSAI2CLK output enable.

PLLSAI2P

Bit 17: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).

PLLSAI2PDIV

Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK.

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

PLLSAI2RDYIE

Bit 7: PLLSAI2 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

PLLSAI2RDYF

Bit 7: PLLSAI2 ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

PLLSAI2RDYC

Bit 7: PLLSAI2 ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 oscillator ready interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCRST
rw
TSCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw
FLASHRST
rw
DMAMUX1RST
rw
DMA2RST
rw
DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 reset.

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 1: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

DMAMUX1RST

Bit 2: DMAMUXRST.

Allowed values:
1: Reset: Reset the selected module

FLASHRST

Bit 8: Flash memory interface reset.

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the selected module

TSCRST

Bit 16: Touch Sensing Controller reset.

Allowed values:
1: Reset: Reset the selected module

GTZCRST

Bit 22: GTZC reset.

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1RST
rw
OTFDEC1RST
rw
PKARST
rw
RNGRST
rw
HASHRST
rw
AESRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCRST
rw
GPIOHRST
rw
GPIOGRST
rw
GPIOFRST
rw
GPIOERST
rw
GPIODRST
rw
GPIOCRST
rw
GPIOBRST
rw
GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

GPIOFRST

Bit 5: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

GPIOGRST

Bit 6: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 13: ADC reset.

Allowed values:
1: Reset: Reset the selected module

AESRST

Bit 16: AES hardware accelerator reset.

Allowed values:
1: Reset: Reset the selected module

HASHRST

Bit 17: Hash reset.

Allowed values:
1: Reset: Reset the selected module

RNGRST

Bit 18: Random number generator reset.

Allowed values:
1: Reset: Reset the selected module

PKARST

Bit 19: PKARST.

Allowed values:
1: Reset: Reset the selected module

OTFDEC1RST

Bit 21: OTFDEC1RST.

Allowed values:
1: Reset: Reset the selected module

SDMMC1RST

Bit 22: SDMMC1 reset.

Allowed values:
1: Reset: Reset the selected module

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1RST
rw
FMCRST
rw
Toggle fields

FMCRST

Bit 0: Flexible memory controller reset.

Allowed values:
1: Reset: Reset the selected module

OSPI1RST

Bit 8: OSPI1RST.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw
OPAMPRST
rw
DAC1RST
rw
PWRRST
rw
CRSRST
rw
I2C3RST
rw
I2C2RST
rw
I2C1RST
rw
UART5RST
rw
UART4RST
rw
USART3RST
rw
USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw
SPI2RST
rw
TIM7RST
rw
TIM6RST
rw
TIM5RST
rw
TIM4RST
rw
TIM3RST
rw
TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: TIM6 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: TIM7 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: UART4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: UART5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
1: Reset: Reset the selected module

CRSRST

Bit 24: CRS reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DAC1RST

Bit 29: DAC1 interface reset.

Allowed values:
1: Reset: Reset the selected module

OPAMPRST

Bit 30: OPAMP interface reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1RST
rw
USBFSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1RST
rw
LPTIM3RST
rw
LPTIM2RST
rw
I2C4RST
rw
LPUART1RST
rw
Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C4RST

Bit 1: I2C4 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM2RST

Bit 5: Low-power timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM3RST

Bit 6: LPTIM3RST.

Allowed values:
1: Reset: Reset the selected module

FDCAN1RST

Bit 9: FDCAN1RST.

Allowed values:
1: Reset: Reset the selected module

USBFSRST

Bit 21: USBFSRST.

Allowed values:
1: Reset: Reset the selected module

UCPD1RST

Bit 23: UCPD1RST.

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST
rw
SAI2RST
rw
SAI1RST
rw
TIM17RST
rw
TIM16RST
rw
TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw
TIM8RST
rw
SPI1RST
rw
TIM1RST
rw
SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: System configuration (SYSCFG) reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 13: TIM8 timer reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 timer reset.

Allowed values:
1: Reset: Reset the selected module

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

Allowed values:
1: Reset: Reset the selected module

SAI2RST

Bit 22: Serial audio interface 2 (SAI2) reset.

Allowed values:
1: Reset: Reset the selected module

DFSDM1RST

Bit 24: Digital filters for sigma-delata modulators (DFSDM) reset.

Allowed values:
1: Reset: Reset the selected module

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000100, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCEN
rw
TSCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw
FLASHEN
rw
DMAMUX1EN
rw
DMA2EN
rw
DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMAMUX1EN

Bit 2: DMAMUX clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLASHEN

Bit 8: Flash memory interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TSCEN

Bit 16: Touch Sensing Controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GTZCEN

Bit 22: GTZCEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1EN
rw
OTFDEC1EN
rw
PKAEN
rw
RNGEN
rw
HASHEN
rw
AESEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCEN
rw
GPIOHEN
rw
GPIOGEN
rw
GPIOFEN
rw
GPIOEEN
rw
GPIODEN
rw
GPIOCEN
rw
GPIOBEN
rw
GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOFEN

Bit 5: IO port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOGEN

Bit 6: IO port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: IO port H clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADCEN

Bit 13: ADC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AESEN

Bit 16: AES accelerator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HASHEN

Bit 17: HASH clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RNGEN

Bit 18: Random Number Generator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PKAEN

Bit 19: PKAEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTFDEC1EN

Bit 21: OTFDEC1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDMMC1EN

Bit 22: SDMMC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1EN
rw
FMCEN
rw
Toggle fields

FMCEN

Bit 0: Flexible memory controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OSPI1EN

Bit 8: OSPI1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR1

APB1ENR1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw
OPAMPEN
rw
DAC1EN
rw
PWREN
rw
CRSEN
rw
I2C3EN
rw
I2C2EN
rw
I2C1EN
rw
UART5EN
rw
UART4EN
rw
USART3EN
rw
USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3EN
rw
SPI2EN
rw
WWDGEN
rw
RTCAPBEN
rw
TIM7EN
rw
TIM6EN
rw
TIM5EN
rw
TIM4EN
rw
TIM3EN
rw
TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: TIM6 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: TIM7 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RTCAPBEN

Bit 10: RTC APB clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SP3EN

Bit 15: SPI3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRSEN

Bit 24: Clock Recovery System clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC1EN

Bit 29: DAC1 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OPAMPEN

Bit 30: OPAMP interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM1EN

Bit 31: Low power timer 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1EN
rw
USBFSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1EN
rw
LPTIM3EN
rw
LPTIM2EN
rw
I2C4EN
rw
LPUART1EN
rw
Toggle fields

LPUART1EN

Bit 0: Low power UART 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C4EN

Bit 1: I2C4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM2EN

Bit 5: LPTIM2EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM3EN

Bit 6: LPTIM3EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FDCAN1EN

Bit 9: FDCAN1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USBFSEN

Bit 21: USBFSEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UCPD1EN

Bit 23: UCPD1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2ENR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1EN
rw
SAI2EN
rw
SAI1EN
rw
TIM17EN
rw
TIM16EN
rw
TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw
TIM8EN
rw
SPI1EN
rw
TIM1EN
rw
SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 13: TIM8 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI1EN

Bit 21: SAI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI2EN

Bit 22: SAI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DFSDM1EN

Bit 24: DFSDM timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, size: 32, reset: 0x00C11307, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESMEN
rw
GTZCSMEN
rw
TSCSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw
SRAM1SMEN
rw
FLASHSMEN
rw
DMAMUX1SMEN
rw
DMA2SMEN
rw
DMA1SMEN
rw
Toggle fields

DMA1SMEN

Bit 0: DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: DMA2 clocks enable during Sleep and Stop modes.

DMAMUX1SMEN

Bit 2: DMAMUX clock enable during Sleep and Stop modes.

FLASHSMEN

Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CRCSMEN.

TSCSMEN

Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.

GTZCSMEN

Bit 22: GTZCSMEN.

ICACHESMEN

Bit 23: ICACHESMEN.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6c, size: 32, reset: 0x006F22FF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SMEN
rw
OTFDEC1SMEN
rw
PKASMEN
rw
RNGSMEN
rw
HASHSMEN
rw
AESSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCFSSMEN
rw
SRAM2SMEN
rw
GPIOHSMEN
rw
GPIOGSMEN
rw
GPIOFSMEN
rw
GPIOESMEN
rw
GPIODSMEN
rw
GPIOCSMEN
rw
GPIOBSMEN
rw
GPIOASMEN
rw
Toggle fields

GPIOASMEN

Bit 0: IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: IO port E clocks enable during Sleep and Stop modes.

GPIOFSMEN

Bit 5: IO port F clocks enable during Sleep and Stop modes.

GPIOGSMEN

Bit 6: IO port G clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: IO port H clocks enable during Sleep and Stop modes.

SRAM2SMEN

Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: ADC clocks enable during Sleep and Stop modes.

AESSMEN

Bit 16: AES accelerator clocks enable during Sleep and Stop modes.

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes.

RNGSMEN

Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.

PKASMEN

Bit 19: PKASMEN.

OTFDEC1SMEN

Bit 21: OTFDEC1SMEN.

SDMMC1SMEN

Bit 22: SDMMC1 clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x00000101, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SMEN
rw
FMCSMEN
rw
Toggle fields

FMCSMEN

Bit 0: Flexible memory controller clocks enable during Sleep and Stop modes.

OSPI1SMEN

Bit 8: OSPI1SMEN.

APB1SMENR1

APB1SMENR1

Offset: 0x78, size: 32, reset: 0xF1FECC3F, access: read-write

0/22 fields covered.

Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.

TIM3SMEN

Bit 1: TIM3 timer clocks enable during Sleep and Stop modes.

TIM4SMEN

Bit 2: TIM4 timer clocks enable during Sleep and Stop modes.

TIM5SMEN

Bit 3: TIM5 timer clocks enable during Sleep and Stop modes.

TIM6SMEN

Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.

TIM7SMEN

Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep and Stop modes.

WWDGSMEN

Bit 11: Window watchdog clocks enable during Sleep and Stop modes.

SPI2SMEN

Bit 14: SPI2 clocks enable during Sleep and Stop modes.

SP3SMEN

Bit 15: SPI3 clocks enable during Sleep and Stop modes.

USART2SMEN

Bit 17: USART2 clocks enable during Sleep and Stop modes.

USART3SMEN

Bit 18: USART3 clocks enable during Sleep and Stop modes.

UART4SMEN

Bit 19: UART4 clocks enable during Sleep and Stop modes.

UART5SMEN

Bit 20: UART5 clocks enable during Sleep and Stop modes.

I2C1SMEN

Bit 21: I2C1 clocks enable during Sleep and Stop modes.

I2C2SMEN

Bit 22: I2C2 clocks enable during Sleep and Stop modes.

I2C3SMEN

Bit 23: I2C3 clocks enable during Sleep and Stop modes.

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes.

PWRSMEN

Bit 28: Power interface clocks enable during Sleep and Stop modes.

DAC1SMEN

Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.

OPAMPSMEN

Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7c, size: 32, reset: 0x00A00223, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SMEN
rw
USBFSSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SMEN
rw
LPTIM3SMEN
rw
LPTIM2SMEN
rw
I2C4SMEN
rw
LPUART1SMEN
rw
Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during Sleep and Stop modes.

I2C4SMEN

Bit 1: I2C4 clocks enable during Sleep and Stop modes.

LPTIM2SMEN

Bit 5: LPTIM2SMEN.

LPTIM3SMEN

Bit 6: LPTIM3SMEN.

FDCAN1SMEN

Bit 9: FDCAN1SMEN.

USBFSSMEN

Bit 21: USBFSSMEN.

UCPD1SMEN

Bit 23: UCPD1SMEN.

APB2SMENR

APB2SMENR

Offset: 0x80, size: 32, reset: 0x01677801, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SMEN
rw
SAI2SMEN
rw
SAI1SMEN
rw
TIM17SMEN
rw
TIM16SMEN
rw
TIM15SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw
TIM8SMEN
rw
SPI1SMEN
rw
TIM1SMEN
rw
SYSCFGSMEN
rw
Toggle fields

SYSCFGSMEN

Bit 0: SYSCFG clocks enable during Sleep and Stop modes.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.

SPI1SMEN

Bit 12: SPI1 clocks enable during Sleep and Stop modes.

TIM8SMEN

Bit 13: TIM8 timer clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 14: USART1clocks enable during Sleep and Stop modes.

TIM15SMEN

Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during Sleep and Stop modes.

SAI1SMEN

Bit 21: SAI1 clocks enable during Sleep and Stop modes.

SAI2SMEN

Bit 22: SAI2 clocks enable during Sleep and Stop modes.

DFSDM1SMEN

Bit 24: DFSDM timer clocks enable during Sleep and Stop modes.

CCIPR1

CCIPR1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCSEL
rw
CLK48MSEL
rw
FDCANSEL
rw
LPTIM3SEL
rw
LPTIM2SEL
rw
LPTIM1SEL
rw
I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw
I2C1SEL
rw
LPUART1SEL
rw
UART5SEL
rw
UART4SEL
rw
USART3SEL
rw
USART2SEL
rw
USART1SEL
rw
Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

USART3SEL

Bits 4-5: USART3 clock source selection.

UART4SEL

Bits 6-7: UART4 clock source selection.

UART5SEL

Bits 8-9: UART5 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C2SEL

Bits 14-15: I2C2 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

LPTIM3SEL

Bits 22-23: Low-power timer 3 clock source selection.

FDCANSEL

Bits 24-25: FDCAN clock source selection.

CLK48MSEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

BDCR

BDCR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw
LSCOEN
rw
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw
LSESYSRDY
rw
RTCSEL
rw
LSESYSEN
rw
LSECSSD
r
LSECSSON
rw
LSEDRV
rw
LSEBYP
rw
LSERDY
r
LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: LSE oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: LSE oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEDRV

Bits 3-4: SE oscillator drive capability.

Allowed values:
0: Lower: 'Xtal mode' lower driving capability
1: MediumLow: 'Xtal mode' medium low driving capability
2: MediumHigh: 'Xtal mode' medium high driving capability
3: Higher: 'Xtal mode' higher driving capability

LSECSSON

Bit 5: LSECSSON.

Allowed values:
0: Off: CSS on LSE (32 kHz external oscillator) OFF
1: On: CSS on LSE (32 kHz external oscillator) ON

LSECSSD

Bit 6: LSECSSD.

Allowed values:
0: NoFailure: No failure detected on LSE (32 kHz oscillator)
1: Failure: Failure detected on LSE (32 kHz oscillator)

LSESYSEN

Bit 7: LSESYSEN.

Allowed values:
0: Disabled: LSESYS only enabled when requested by a peripheral or system function
1: Enabled: LSESYS enabled always generated by RCC

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

LSESYSRDY

Bit 11: LSESYSRDY.

Allowed values:
0: NotReady: LSESYS clock not ready
1: Ready: LSESYS clock ready

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

LSCOEN

Bit 24: Low speed clock output enable.

Allowed values:
0: Disabled: LSCO disabled
1: Enabled: LSCO enabled

LSCOSEL

Bit 25: Low speed clock output selection.

Allowed values:
0: LSI: LSI clock selected"
1: LSE: LSE clock selected

CSR

CSR

Offset: 0x94, size: 32, reset: 0x0C000600, access: Unspecified

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
r
WWDGRSTF
r
IWWDGRSTF
r
SFTRSTF
r
BORRSTF
r
PINRSTF
r
OBLRSTF
r
RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSISRANGE
rw
LSIPREDIV
rw
LSIRDY
r
LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: LSI oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

LSIPREDIV

Bit 4: LSIPREDIV.

MSISRANGE

Bits 8-11: SI range after Standby mode.

RMVF

Bit 23: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PINRSTF

Bit 26: Pin reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

BORRSTF

Bit 27: BOR flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWWDGRSTF

Bit 29: Independent window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

CRRCR

Clock recovery RC register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r
HSI48RDY
r
HSI48ON
rw
Toggle fields

HSI48ON

Bit 0: HSI48 clock enable.

HSI48RDY

Bit 1: HSI48 clock ready flag.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

CCIPR2

Peripherals independent clock configuration register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPISEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMCSEL
rw
SAI2SEL
rw
SAI1SEL
rw
ADFSDMSEL
rw
DFSDMSEL
rw
I2C4SEL
rw
Toggle fields

I2C4SEL

Bits 0-1: I2C4 clock source selection.

DFSDMSEL

Bit 2: Digital filter for sigma delta modulator kernel clock source selection.

ADFSDMSEL

Bits 3-4: Digital filter for sigma delta modulator audio clock source selection.

SAI1SEL

Bits 5-7: SAI1 clock source selection.

SAI2SEL

Bits 8-10: SAI2 clock source selection.

SDMMCSEL

Bit 14: SDMMC clock selection.

OSPISEL

Bits 20-21: Octospi clock source selection.

SECCFGR

RCC secure configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

Toggle fields

HSISEC

Bit 0: HSISEC.

HSESEC

Bit 1: HSESEC.

MSISEC

Bit 2: MSISEC.

LSISEC

Bit 3: LSISEC.

LSESEC

Bit 4: LSESEC.

SYSCLKSEC

Bit 5: SYSCLKSEC.

PRESCSEC

Bit 6: PRESCSEC.

PLLSEC

Bit 7: PLLSEC.

PLLSAI1SEC

Bit 8: PLLSAI1SEC.

PLLSAI2SEC

Bit 9: PLLSAI2SEC.

CLK48MSEC

Bit 10: CLK48MSEC.

HSI48SEC

Bit 11: HSI48SEC.

RMVFSEC

Bit 12: RMVFSEC.

SECSR

RCC secure status register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

Toggle fields

HSISECF

Bit 0: HSISECF.

HSESECF

Bit 1: HSESECF.

MSISECF

Bit 2: MSISECF.

LSISECF

Bit 3: LSISECF.

LSESECF

Bit 4: LSESECF.

SYSCLKSECF

Bit 5: SYSCLKSECF.

PRESCSECF

Bit 6: PRESCSECF.

PLLSECF

Bit 7: PLLSECF.

PLLSAI1SECF

Bit 8: PLLSAI1SECF.

PLLSAI2SECF

Bit 9: PLLSAI2SECF.

CLK48MSECF

Bit 10: CLK48MSECF.

HSI48SECF

Bit 11: HSI48SECF.

RMVFSECF

Bit 12: RMVFSECF.

AHB1SECSR

RCC AHB1 security status register

Offset: 0xe8, size: 32, reset: 0x00400300, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESECF
r
GTZCSECF
r
TSCSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSECF
r
SRAM1SECF
r
FLASHSECF
r
DMAMUX1SECF
r
DMA2SECF
r
DMA1SECF
r
Toggle fields

DMA1SECF

Bit 0: DMA1SECF.

DMA2SECF

Bit 1: DMA2SECF.

DMAMUX1SECF

Bit 2: DMAMUX1SECF.

FLASHSECF

Bit 8: FLASHSECF.

SRAM1SECF

Bit 9: SRAM1SECF.

CRCSECF

Bit 12: CRCSECF.

TSCSECF

Bit 16: TSCSECF.

GTZCSECF

Bit 22: GTZCSECF.

ICACHESECF

Bit 23: ICACHESECF.

AHB2SECSR

RCC AHB2 security status register

Offset: 0xec, size: 32, reset: 0x002002FF, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SECF
r
OTFDEC1SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2SECF
r
GPIOHSECF
r
GPIOGSECF
r
GPIOFSECF
r
GPIOESECF
r
GPIODSECF
r
GPIOCSECF
r
GPIOBSECF
r
GPIOASECF
r
Toggle fields

GPIOASECF

Bit 0: GPIOASECF.

GPIOBSECF

Bit 1: GPIOBSECF.

GPIOCSECF

Bit 2: GPIOCSECF.

GPIODSECF

Bit 3: GPIODSECF.

GPIOESECF

Bit 4: GPIOESECF.

GPIOFSECF

Bit 5: GPIOFSECF.

GPIOGSECF

Bit 6: GPIOGSECF.

GPIOHSECF

Bit 7: GPIOHSECF.

SRAM2SECF

Bit 9: SRAM2SECF.

OTFDEC1SECF

Bit 21: OTFDEC1SECF.

SDMMC1SECF

Bit 22: SDMMC1SECF.

AHB3SECSR

RCC AHB3 security status register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SECF
r
FSMCSECF
r
Toggle fields

FSMCSECF

Bit 0: FSMCSECF.

OSPI1SECF

Bit 8: OSPI1SECF.

APB1SECSR1

RCC APB1 security status register 1

Offset: 0xf8, size: 32, reset: 0x00000400, access: read-only

22/22 fields covered.

Toggle fields

TIM2SECF

Bit 0: TIM2SECF.

TIM3SECF

Bit 1: TIM3SECF.

TIM4SECF

Bit 2: TIM4SECF.

TIM5SECF

Bit 3: TIM5SECF.

TIM6SECF

Bit 4: TIM6SECF.

TIM7SECF

Bit 5: TIM7SECF.

RTCAPBSECF

Bit 10: RTCAPBSECF.

WWDGSECF

Bit 11: WWDGSECF.

SPI2SECF

Bit 14: SPI2SECF.

SPI3SECF

Bit 15: SPI3SECF.

UART2SECF

Bit 17: UART2SECF.

UART3SECF

Bit 18: UART3SECF.

UART4SECF

Bit 19: UART4SECF.

UART5SECF

Bit 20: UART5SECF.

I2C1SECF

Bit 21: I2C1SECF.

I2C2SECF

Bit 22: I2C2SECF.

I2C3SECF

Bit 23: I2C3SECF.

CRSSECF

Bit 24: CRSSECF.

PWRSECF

Bit 28: PWRSECF.

DACSECF

Bit 29: DACSECF.

OPAMPSECF

Bit 30: OPAMPSECF.

LPTIM1SECF

Bit 31: LPTIM1SECF.

APB1SECSR2

RCC APB1 security status register 2

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SECF
r
USBFSSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SECF
r
LPTIM3SECF
r
LPTIM2SECF
r
I2C4SECF
r
LPUART1SECF
r
Toggle fields

LPUART1SECF

Bit 0: LPUART1SECF.

I2C4SECF

Bit 1: I2C4SECF.

LPTIM2SECF

Bit 5: LPTIM2SECF.

LPTIM3SECF

Bit 6: LPTIM3SECF.

FDCAN1SECF

Bit 9: FDCAN1SECF.

USBFSSECF

Bit 21: USBFSSECF.

UCPD1SECF

Bit 23: UCPD1SECF.

APB2SECSR

RCC APB2 security status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SECF
r
SAI2SECF
r
SAI1SECF
r
TIM17SECF
r
TIM16SECF
r
TIM15SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SECF
r
TIM8SECF
r
SPI1SECF
r
TIM1SECF
r
SYSCFGSECF
r
Toggle fields

SYSCFGSECF

Bit 0: SYSCFGSECF.

TIM1SECF

Bit 11: TIM1SECF.

SPI1SECF

Bit 12: SPI1SECF.

TIM8SECF

Bit 13: TIM8SECF.

USART1SECF

Bit 14: USART1SECF.

TIM15SECF

Bit 16: TIM15SECF.

TIM16SECF

Bit 17: TIM16SECF.

TIM17SECF

Bit 18: TIM17SECF.

SAI1SECF

Bit 21: SAI1SECF.

SAI2SECF

Bit 22: SAI2SECF.

DFSDM1SECF

Bit 24: DFSDM1SECF.

RNG

0x420c0800: RNG

4/17 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x10 HTCR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFIGLOCK
rw
CONDRST
rw
RNG_CONFIG1
rw
CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2
rw
NISTC
rw
RNG_CONFIG3
rw
CED
rw
IE
rw
RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

CED

Bit 5: Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled..

RNG_CONFIG3

Bits 8-11: RNG configuration 3.

NISTC

Bit 12: Non NIST compliant.

RNG_CONFIG2

Bits 13-15: RNG configuration 2.

CLKDIV

Bits 16-19: Clock divider factor.

RNG_CONFIG1

Bits 20-25: RNG configuration 1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: RNG Config Lock.

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw
CEIS
rw
SECS
r
CECS
r
DRDY
r
Toggle fields

DRDY

Bit 0: Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated..

CECS

Bit 1: Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SECS

Bit 2: Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01).

CEIS

Bit 5: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SEIS

Bit 6: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register..

DR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data 32-bit random data which are valid when DRDY=1..

HTCR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x10, size: 32, reset: 0x000CAA74, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG
rw
Toggle fields

HTCFG

Bits 0-31: health test configuration.

RTC

0x40002800: Real-time clock

129/147 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x1c PRIVCR
0x20 SMCR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x58 SMISR
0x5c SCR
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

Allowed values: 0x0-0xffff

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
INITF
r
RSF
r/w0c
INITS
r
SHPF
rw
WUTWF
r
ALR[B]WF
r
ALR[A]WF
r
Toggle fields

ALR[A]WF

Bit 0: Alarm A write flag.

ALR[B]WF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: Shift operation pending.

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: Initialization status flag.

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: Registers synchronization flag.

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: Initialization flag.

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: Initialization mode.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

RECALPF

Bit 16: Recalibration pending Flag.

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

Allowed values: 0x0-0x7f

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUTOCLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

Allowed values: 0x0-0xffff

WUTOCLR

Bits 16-31: WUTOCLR.

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw
TAMPALRM_TYPE
rw
TAMPALRM_PU
rw
TAMPOE
rw
TAMPTS
rw
ITSE
rw
COE
rw
OSEL
rw
POL
rw
COSEL
rw
BKP
rw
SUB1H
rw
ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw
WUTIE
rw
ALR[B]IE
rw
ALR[A]IE
rw
TSE
rw
WUTE
rw
ALR[B]E
rw
ALR[A]E
rw
FMT
rw
BYPSHAD
rw
REFCKON
rw
TSEDGE
rw
WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: TSEDGE.

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: REFCKON.

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: BYPSHAD.

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: FMT.

Allowed values:
0: TwentyFourHour: 24 hour/day format
1: AmPm: AM/PM hour format

ALR[A]E

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

ALR[B]E

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

WUTE

Bit 10: WUTE.

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: TSE.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALR[A]IE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

ALR[B]IE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

WUTIE

Bit 14: WUTIE.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: TSIE.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: ADD1H.

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: SUB1H.

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: BKP.

Allowed values:
0: DSTNotChanged: Daylight Saving Time change has not been performed
1: DSTChanged: Daylight Saving Time change has been performed

COSEL

Bit 19: COSEL.

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: POL.

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: OSEL.

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: COE.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ITSE

Bit 24: ITSE.

Allowed values:
0: Disabled: Internal event timestamp disabled
1: Enabled: Internal event timestamp enabled

TAMPTS

Bit 25: TAMPTS.

Allowed values:
0: Disabled: Tamper detection event does not cause a RTC timestamp to be saved
1: Enabled: Save RTC timestamp on tamper detection event

TAMPOE

Bit 26: TAMPOE.

Allowed values:
0: Disabled: The tamper flag is not routed on TAMPALRM
1: Enabled: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

Allowed values:
0: NoPullUp: No pull-up is applied on TAMPALRM output
1: PullUp: A pull-up is applied on TAMPALRM output

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

Allowed values:
0: PushPull: TAMPALRM is push-pull output
1: OpenDrain: TAMPALRM is open-drain output

OUT2EN

Bit 31: OUT2EN.

Allowed values:
0: Disabled: RTC output 2 disable
1: Enabled: RTC output 2 enable

PRIVCR

RTC privilege mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
INITPRIV
rw
CALPRIV
rw
TSPRIV
rw
WUTPRIV
rw
ALRBPRIV
rw
ALRAPRIV
rw
Toggle fields

ALRAPRIV

Bit 0: ALRAPRIV.

ALRBPRIV

Bit 1: ALRBPRIV.

WUTPRIV

Bit 2: WUTPRIV.

TSPRIV

Bit 3: TSPRIV.

CALPRIV

Bit 13: CALPRIV.

INITPRIV

Bit 14: INITPRIV.

PRIV

Bit 15: PRIV.

SMCR

RTC secure mode control register

Offset: 0x20, size: 32, reset: 0x0000E00F, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT
rw
INITDPROT
rw
CALDPROT
rw
TSDPROT
rw
WUTDPROT
rw
ALRBDPROT
rw
ALRADPROT
rw
Toggle fields

ALRADPROT

Bit 0: ALRADPROT.

ALRBDPROT

Bit 1: ALRBDPROT.

WUTDPROT

Bit 2: WUTDPROT.

TSDPROT

Bit 3: TSDPROT.

CALDPROT

Bit 13: CALDPROT.

INITDPROT

Bit 14: INITDPROT.

DECPROT

Bit 15: DECPROT.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

Allowed values:
0: Activate: Activate write protection (any value that is not the keys)
83: Deactivate2: Key 2
202: Deactivate1: Key 1

CALR

calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw
CALW8
rw
CALW16
rw
LPCAL
rw
CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

Allowed values: 0x0-0x1ff

LPCAL

Bit 12: LPCAL.

CALW16

Bit 13: Use a 16-second calibration cycle period.

Allowed values:
1: SixteenSeconds: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: Use an 8-second calibration cycle period.

Allowed values:
1: EightSeconds: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: Add one second.

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

Allowed values: 0x0-0xffff

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSF
r
TSOVF
r
TSF
r
WUTF
r
ALR[B]F
r
ALR[A]F
r
Toggle fields

ALR[A]F

Bit 0: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

ALR[B]F

Bit 1: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

WUTF

Bit 2: WUTF.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 3: TSF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 4: TSOVF.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSF

Bit 5: ITSF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r
TSOVMF
r
TSMF
r
WUTMF
r
ALR[B]MF
r
ALR[A]MF
r
Toggle fields

ALR[A]MF

Bit 0: Alarm A masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

ALR[B]MF

Bit 1: Alarm B masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

WUTMF

Bit 2: WUTMF.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSMF

Bit 3: TSMF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVMF

Bit 4: TSOVMF.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSMF

Bit 5: ITSMF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

SMISR

RTC secure masked interrupt status register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r
TSOVMF
r
TSMF
r
WUTMF
r
ALRBMF
r
ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITSF
w
CTSOVF
w
CTSF
w
CWUTF
w
CALRBF
w
CALRAF
w
Toggle fields

CALRAF

Bit 0: CALRAF.

Allowed values:
1: Clear: Clear interrupt flag

CALRBF

Bit 1: CALRBF.

Allowed values:
1: Clear: Clear interrupt flag

CWUTF

Bit 2: CWUTF.

Allowed values:
1: Clear: Clear interrupt flag

CTSF

Bit 3: CTSF.

Allowed values:
1: Clear: Clear interrupt flag

CTSOVF

Bit 4: CTSOVF.

Allowed values:
1: Clear: Clear interrupt flag

CITSF

Bit 5: CITSF.

Allowed values:
1: Clear: Clear interrupt flag

SAI1

0x40015400: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw
SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw
CKEN1
rw
MICNBR
rw
PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw
DLYM[4]L
rw
DLYM[3]R
rw
DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw
DLYM[2]L
rw
DLYM[1]R
rw
DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SAI2

0x40015800: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw
SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw
CKEN1
rw
MICNBR
rw
PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw
DLYM[4]L
rw
DLYM[3]R
rw
DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw
DLYM[2]L
rw
DLYM[1]R
rw
DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SDMMC1

0x420c8000: SDMMC1

38/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASE0R
0x5c IDMABASE1R
0x80 FIFOR
0x3f4 VER
0x3f8 ID
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw
VSWITCHEN
rw
VSWITCH
rw
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11..

VSWITCH

Bit 2: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:.

VSWITCHEN

Bit 3: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:.

DIRPOL

Bit 4: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)..

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw
BUSSPEED
rw
DDR
rw
HWFC_EN
rw
NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw
PWRSAV
rw
CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc...

PWRSAV

Bit 12: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:.

WIDBUS

Bits 14-15: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

NEGEDGE

Bit 16: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge..

HWFC_EN

Bit 17: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11..

DDR

Bit 18: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0).

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SELCLKRX

Bits 20-21: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register..

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw
BOOTMODE
rw
DTHOLD
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDSTOP
rw
CMDTRANS
rw
CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message..

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent..

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent..

WAITRESP

Bits 8-9: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response..

WAITINT

Bit 10: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode..

WAITPEND

Bit 11: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card..

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0..

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state..

BOOTMODE

Bit 14: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).

BOOTEN

Bit 15: Enable boot mode procedure..

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1..

RESPCMDR

SDMMC command response register

Offset: 0x10, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: see Table 432.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: see Table404..

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: see Table404..

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: see Table404..

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods..

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0..

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw
BOOTACKEN
rw
SDIOEN
rw
RWMOD
rw
RWSTOP
rw
RWSTART
rw
DBLOCKSIZE
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards..

DTDIR

Bit 1: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DTMODE

Bits 2-3: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DBLOCKSIZE

Bits 4-7: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered).

RWSTART

Bit 8: Read wait start. If this bit is set, read wait operation starts..

RWSTOP

Bit 9: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state..

RWMOD

Bit 10: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDIOEN

Bit 11: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation..

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

FIFORST

Bit 13: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs..

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect..

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

Toggle fields

CCRCFAIL

Bit 0: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CTIMEOUT

Bit 2: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods..

DTIMEOUT

Bit 3: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

TXUNDERR

Bit 4: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

RXOVERR

Bit 5: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDSENT

Bit 7: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DATAEND

Bit 8: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DHOLD

Bit 9: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DBCKEND

Bit 10: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DABORT

Bit 11: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

TXFIFOHE

Bit 14: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full..

RXFIFOHF

Bit 15: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty..

TXFIFOF

Bit 16: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty..

RXFIFOF

Bit 17: Receive FIFO full This bit is cleared when one FIFO location becomes empty..

TXFIFOE

Bit 18: Transmit FIFO empty This bit is cleared when one FIFO location becomes full..

RXFIFOE

Bit 19: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full..

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt..

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDIOIT

Bit 22: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

VSWEND

Bit 25: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMATE

Bit 27: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMABTC

Bit 28: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

Toggle fields

CCRCFAILC

Bit 0: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag..

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag..

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag..

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag..

TXUNDERRC

Bit 4: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag..

RXOVERRC

Bit 5: RXOVERR flag clear bit Set by software to clear the RXOVERR flag..

CMDRENDC

Bit 6: CMDREND flag clear bit Set by software to clear the CMDREND flag..

CMDSENTC

Bit 7: CMDSENT flag clear bit Set by software to clear the CMDSENT flag..

DATAENDC

Bit 8: DATAEND flag clear bit Set by software to clear the DATAEND flag..

DHOLDC

Bit 9: DHOLD flag clear bit Set by software to clear the DHOLD flag..

DBCKENDC

Bit 10: DBCKEND flag clear bit Set by software to clear the DBCKEND flag..

DABORTC

Bit 11: DABORT flag clear bit Set by software to clear the DABORT flag..

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag..

SDIOITC

Bit 22: SDIOIT flag clear bit Set by software to clear the SDIOIT flag..

ACKFAILC

Bit 23: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag..

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag..

VSWENDC

Bit 25: VSWEND flag clear bit Set by software to clear the VSWEND flag..

CKSTOPC

Bit 26: CKSTOP flag clear bit Set by software to clear the CKSTOP flag..

IDMATEC

Bit 27: IDMA transfer error clear bit Set by software to clear the IDMATE flag..

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag..

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure..

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure..

CTIMEOUTIE

Bit 2: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout..

DTIMEOUTIE

Bit 3: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout..

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error..

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error..

CMDRENDIE

Bit 6: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response..

CMDSENTIE

Bit 7: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command..

DATAENDIE

Bit 8: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end..

DHOLDIE

Bit 9: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state..

DBCKENDIE

Bit 10: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end..

DABORTIE

Bit 11: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted..

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty..

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full..

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full..

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty..

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response..

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt..

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail..

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout..

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion..

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped..

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer..

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods..

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABACT
rw
IDMABMODE
rw
IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABMODE

Bit 1: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABACT

Bit 2: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware..

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-12: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABASE0R

The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE0
rw
Toggle fields

IDMABASE0

Bits 0-31: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)..

IDMABASE1R

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE1
rw
Toggle fields

IDMABASE1

Bits 0-31: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)..

FIFOR

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words..

VER

SDMMC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r
MINREV
r
Toggle fields

MINREV

Bits 0-3: IP minor revision number..

MAJREV

Bits 4-7: IP major revision number..

ID

SDMMC IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: SDMMC IP identification..

SEC_ADC1

0x52028000: Analog-to-Digital Converter

181/182 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR[1]
0x64 OFR[2]
0x68 OFR[3]
0x6c OFR[4]
0x80 JDR[1]
0x84 JDR[2]
0x88 JDR[3]
0x8c JDR[4]
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
r/w1c
AWD[3]
r/w1c
AWD[2]
r/w1c
AWD[1]
r/w1c
JEOS
r/w1c
JEOC
r/w1c
OVR
r/w1c
EOS
r/w1c
EOC
r/w1c
EOSMP
r/w1c
ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
r/w1s
ADSTP
r/w1s
JADSTART
r/w1s
ADSTART
r/w1s
ADDIS
r/w1s
ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

DEEPPWD

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

ADCALDIF

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw
AWD1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
ALIGN
rw
RES
rw
DMACFG
rw
DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw
TOVS
rw
OVSS
rw
OVSR
rw
JOVSE
rw
ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

JOVSE

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

OVSR

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

OVSS

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

TOVS

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[9]
rw
SMP[8]
rw
SMP[7]
rw
SMP[6]
rw
SMP[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[5]
rw
SMP[4]
rw
SMP[3]
rw
SMP[2]
rw
SMP[1]
rw
SMP[0]
rw
Toggle fields

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[18]
rw
SMP[17]
rw
SMP[16]
rw
SMP[15]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[15]
rw
SMP[14]
rw
SMP[13]
rw
SMP[12]
rw
SMP[11]
rw
SMP[10]
rw
Toggle fields

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

Allowed values: 0x0-0xff

HT2

Bits 16-23: HT2.

Allowed values: 0x0-0xff

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

Allowed values: 0x0-0xff

HT3

Bits 16-23: HT3.

Allowed values: 0x0-0xff

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[4]
rw
SQ[3]
rw
SQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[2]
rw
SQ[1]
rw
L
rw
Toggle fields

L

Bits 0-3: L.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[9]
rw
SQ[8]
rw
SQ[7]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[7]
rw
SQ[6]
rw
SQ[5]
rw
Toggle fields

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[14]
rw
SQ[13]
rw
SQ[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[12]
rw
SQ[11]
rw
SQ[10]
rw
Toggle fields

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[16]
rw
SQ[15]
rw
Toggle fields

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

Allowed values: 0x0-0xffff

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ[4]
rw
JSQ[3]
rw
JSQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ[2]
rw
JSQ[1]
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle fields

JL

Bits 0-1: JL.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFR[1]

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[2]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[3]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[4]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

JDR[1]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[2]

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[3]

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[4]

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD2CH[0]

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD3CH[0]

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Toggle fields

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

SEC_ADC2

0x52028100: Analog-to-Digital Converter

181/182 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x20 TR1
0x24 TR2
0x28 TR3
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR[1]
0x64 OFR[2]
0x68 OFR[3]
0x6c OFR[4]
0x80 JDR[1]
0x84 JDR[2]
0x88 JDR[3]
0x8c JDR[4]
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 DIFSEL
0xb4 CALFACT
Toggle registers

ISR

interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
r/w1c
AWD[3]
r/w1c
AWD[2]
r/w1c
AWD[1]
r/w1c
JEOS
r/w1c
JEOC
r/w1c
OVR
r/w1c
EOS
r/w1c
EOC
r/w1c
EOSMP
r/w1c
ADRDY
r/w1c
Toggle fields

ADRDY

Bit 0: ADRDY.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP

Bit 1: EOSMP.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC

Bit 2: EOC.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS

Bit 3: EOS.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR

Bit 4: OVR.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC

Bit 5: JEOC.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS

Bit 6: JEOS.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD[1]

Bit 7: Analog watchdog 1 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[2]

Bit 8: Analog watchdog 2 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD[3]

Bit 9: Analog watchdog 3 flag.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF

Bit 10: JQOVF.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

Allowed values:
0: Disabled: ADC ready interrupt disabled
1: Enabled: ADC ready interrupt enabled

EOSMPIE

Bit 1: EOSMPIE.

Allowed values:
0: Disabled: End of regular conversion sampling phase interrupt disabled
1: Enabled: End of regular conversion sampling phase interrupt enabled

EOCIE

Bit 2: EOCIE.

Allowed values:
0: Disabled: End of regular conversion interrupt disabled
1: Enabled: End of regular conversion interrupt enabled

EOSIE

Bit 3: EOSIE.

Allowed values:
0: Disabled: End of regular sequence interrupt disabled
1: Enabled: End of regular sequence interrupt enabled

OVRIE

Bit 4: OVRIE.

Allowed values:
0: Disabled: Overrun interrupt disabled
1: Enabled: Overrun interrupt enabled

JEOCIE

Bit 5: JEOCIE.

Allowed values:
0: Disabled: End of injected conversion interrupt disabled
1: Enabled: End of injected conversion interrupt enabled

JEOSIE

Bit 6: JEOSIE.

Allowed values:
0: Disabled: End of injected sequence interrupt disabled
1: Enabled: End of injected sequence interrupt enabled

AWD[1]IE

Bit 7: Analog watchdog 1 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[2]IE

Bit 8: Analog watchdog 2 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

AWD[3]IE

Bit 9: Analog watchdog 3 interrupt enable.

Allowed values:
0: Disabled: Analog watchdog interrupt disabled
1: Enabled: Analog watchdog interrupt enabled

JQOVFIE

Bit 10: JQOVFIE.

Allowed values:
0: Disabled: Injected context queue overflow interrupt disabled
1: Enabled: Injected context queue overflow interrupt enabled

CR

control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
r/w1s
ADCALDIF
rw
DEEPPWD
rw
ADVREGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADSTP
r/w1s
ADSTP
r/w1s
JADSTART
r/w1s
ADSTART
r/w1s
ADDIS
r/w1s
ADEN
r/w1s
Toggle fields

ADEN

Bit 0: ADEN.

Allowed values:
0: Disabled: ADC disabled
1: Enabled: ADC enabled

ADDIS

Bit 1: ADDIS.

Allowed values:
0: NotDisabling: No disable command active
1: Disabling: ADC disabling

ADSTART

Bit 2: ADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

JADSTART

Bit 3: JADSTART.

Allowed values:
0: NotActive: No conversion ongoing
1: Active: ADC operating and may be converting

ADSTP

Bit 4: ADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

JADSTP

Bit 5: JADSTP.

Allowed values:
0: NotStopping: No stop command active
1: Stopping: ADC stopping conversion

ADVREGEN

Bit 28: ADVREGEN.

Allowed values:
0: Disabled: ADC Voltage regulator disabled
1: Enabled: ADC Voltage regulator enabled

DEEPPWD

Bit 29: DEEPPWD.

Allowed values:
0: NotDeepPowerDown: ADC not in Deep-power down
1: DeepPowerDown: ADC in Deep-power-down (default reset state)

ADCALDIF

Bit 30: ADCALDIF.

Allowed values:
0: SingleEnded: Calibration for single-ended mode
1: Differential: Calibration for differential mode

ADCAL

Bit 31: ADCAL.

Allowed values:
0: NotCalibrating: ADC calibration either not yet performed or completed
1: Calibrating: ADC calibration in progress

CFGR

configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

18/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw
AWD1CH
rw
JAUTO
rw
JAWD1EN
rw
AWD1EN
rw
AWD1SGL
rw
JQM
rw
JDISCEN
rw
DISCNUM
rw
DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw
CONT
rw
OVRMOD
rw
EXTEN
rw
EXTSEL
rw
ALIGN
rw
RES
rw
DMACFG
rw
DMAEN
rw
Toggle fields

DMAEN

Bit 0: DMAEN.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

DMACFG

Bit 1: DMACFG.

Allowed values:
0: OneShot: DMA One Shot mode selected
1: Circular: DMA Circular mode selected

RES

Bits 3-4: RES.

Allowed values:
0: Bits12: 12-bit
1: Bits10: 10-bit
2: Bits8: 8-bit
3: Bits6: 6-bit

ALIGN

Bit 5: ALIGN.

Allowed values:
0: Right: Right alignment
1: Left: Left alignment

EXTSEL

Bits 6-9: EXTSEL.

Allowed values:
0: TIM1_CC1: Timer 1 CC1 event
1: TIM1_CC2: Timer 1 CC2 event
2: TIM1_CC3: Timer 1 CC3 event
3: TIM2_CC2: Timer 2 CC2 event
4: TIM3_TRGO: Timer 3 TRGO event
6: EXTI11: EXTI line 11
9: TIM1_TRGO: Timer 1 TRGO event
10: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM2_TRGO: Timer 2 TRGO event
13: TIM6_TRGO: Timer 6 TRGO event
14: TIM15_TRGO: Timer 15 TRGO event
15: TIM3_CC4: Timer 3 CC4 event

EXTEN

Bits 10-11: EXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

OVRMOD

Bit 12: OVRMOD.

Allowed values:
0: Preserve: Preserve DR register when an overrun is detected
1: Overwrite: Overwrite DR register when an overrun is detected

CONT

Bit 13: CONT.

Allowed values:
0: Single: Single conversion mode
1: Continuous: Continuous conversion mode

AUTDLY

Bit 14: AUTDLY.

Allowed values:
0: Off: Auto delayed conversion mode off
1: On: Auto delayed conversion mode on

DISCEN

Bit 16: DISCEN.

Allowed values:
0: Disabled: Discontinuous mode on regular channels disabled
1: Enabled: Discontinuous mode on regular channels enabled

DISCNUM

Bits 17-19: DISCNUM.

Allowed values: 0x0-0x7

JDISCEN

Bit 20: JDISCEN.

Allowed values:
0: Disabled: Discontinuous mode on injected channels disabled
1: Enabled: Discontinuous mode on injected channels enabled

JQM

Bit 21: JQM.

Allowed values:
0: Mode0: JSQR Mode 0: Queue maintains the last written configuration into JSQR
1: Mode1: JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence

AWD1SGL

Bit 22: AWD1SGL.

Allowed values:
0: All: Analog watchdog 1 enabled on all channels
1: Single: Analog watchdog 1 enabled on single channel selected in AWD1CH

AWD1EN

Bit 23: AWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on regular channels
1: Enabled: Analog watchdog 1 enabled on regular channels

JAWD1EN

Bit 24: JAWD1EN.

Allowed values:
0: Disabled: Analog watchdog 1 disabled on injected channels
1: Enabled: Analog watchdog 1 enabled on injected channels

JAUTO

Bit 25: JAUTO.

Allowed values:
0: Disabled: Automatic injected group conversion disabled
1: Enabled: Automatic injected group conversion enabled

AWD1CH

Bits 26-30: AWDCH1CH.

Allowed values: 0x0-0x12

JQDIS

Bit 31: JQDIS.

CFGR2

configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROVSM
rw
TOVS
rw
OVSS
rw
OVSR
rw
JOVSE
rw
ROVSE
rw
Toggle fields

ROVSE

Bit 0: DMAEN.

Allowed values:
0: Disabled: Regular Oversampling disabled
1: Enabled: Regular Oversampling enabled

JOVSE

Bit 1: DMACFG.

Allowed values:
0: Disabled: Injected Oversampling disabled
1: Enabled: Injected Oversampling enabled

OVSR

Bits 2-4: RES.

Allowed values:
0: Ratio2: 2x
1: Ratio4: 4x
2: Ratio8: 8x
3: Ratio16: 16x
4: Ratio32: 32x
5: Ratio64: 64x
6: Ratio128: 128x
7: Ratio256: 256x

OVSS

Bits 5-8: ALIGN.

Allowed values:
0: NoShift: No Shift
1: Shift1Bit: Shift 1-bit
2: Shift2Bit: Shift 2-bit
3: Shift3Bit: Shift 3-bit
4: Shift4Bit: Shift 4-bit
5: Shift5Bit: Shift 5-bit
6: Shift6Bit: Shift 6-bit
7: Shift7Bit: Shift 7-bit
8: Shift8Bit: Shift 8-bit

TOVS

Bit 9: EXTSEL.

Allowed values:
0: All: All oversampled conversions for a channel are done consecutively following a trigger
1: Single: Each oversampled conversion for a channel needs a new trigger

ROVSM

Bit 10: EXTEN.

Allowed values:
0: ContinuedMode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)
1: ResumedMode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)

SMPR1

sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[9]
rw
SMP[8]
rw
SMP[7]
rw
SMP[6]
rw
SMP[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[5]
rw
SMP[4]
rw
SMP[3]
rw
SMP[2]
rw
SMP[1]
rw
SMP[0]
rw
Toggle fields

SMP[0]

Bits 0-2: Channel 0 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[1]

Bits 3-5: Channel 1 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[2]

Bits 6-8: Channel 2 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[3]

Bits 9-11: Channel 3 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[4]

Bits 12-14: Channel 4 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[5]

Bits 15-17: Channel 5 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[6]

Bits 18-20: Channel 6 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[7]

Bits 21-23: Channel 7 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[8]

Bits 24-26: Channel 8 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[9]

Bits 27-29: Channel 9 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMPR2

sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP[18]
rw
SMP[17]
rw
SMP[16]
rw
SMP[15]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP[15]
rw
SMP[14]
rw
SMP[13]
rw
SMP[12]
rw
SMP[11]
rw
SMP[10]
rw
Toggle fields

SMP[10]

Bits 0-2: Channel 10 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[11]

Bits 3-5: Channel 11 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[12]

Bits 6-8: Channel 12 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[13]

Bits 9-11: Channel 13 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[14]

Bits 12-14: Channel 14 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[15]

Bits 15-17: Channel 15 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[16]

Bits 18-20: Channel 16 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[17]

Bits 21-23: Channel 17 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

SMP[18]

Bits 24-26: Channel 18 sample time selection.

Allowed values:
0: Cycles2_5: 2.5 ADC clock cycles
1: Cycles6_5: 6.5 ADC clock cycles
2: Cycles12_5: 12.5 ADC clock cycles
3: Cycles24_5: 24.5 ADC clock cycles
4: Cycles47_5: 47.5 ADC clock cycles
5: Cycles92_5: 92.5 ADC clock cycles
6: Cycles247_5: 247.5 ADC clock cycles
7: Cycles640_5: 640.5 ADC clock cycles

TR1

watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT1
rw
Toggle fields

LT1

Bits 0-11: LT1.

Allowed values: 0x0-0xfff

HT1

Bits 16-27: HT1.

Allowed values: 0x0-0xfff

TR2

watchdog threshold register

Offset: 0x24, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT2
rw
Toggle fields

LT2

Bits 0-7: LT2.

Allowed values: 0x0-0xff

HT2

Bits 16-23: HT2.

Allowed values: 0x0-0xff

TR3

watchdog threshold register 3

Offset: 0x28, size: 32, reset: 0x0FFF0000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT3
rw
Toggle fields

LT3

Bits 0-7: LT3.

Allowed values: 0x0-0xff

HT3

Bits 16-23: HT3.

Allowed values: 0x0-0xff

SQR1

regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[4]
rw
SQ[3]
rw
SQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[2]
rw
SQ[1]
rw
L
rw
Toggle fields

L

Bits 0-3: L.

Allowed values: 0x0-0xf

SQ[1]

Bits 6-10: 1 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[2]

Bits 12-16: 2 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[3]

Bits 18-22: 3 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[4]

Bits 24-28: 4 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR2

regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[9]
rw
SQ[8]
rw
SQ[7]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[7]
rw
SQ[6]
rw
SQ[5]
rw
Toggle fields

SQ[5]

Bits 0-4: 5 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[6]

Bits 6-10: 6 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[7]

Bits 12-16: 7 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[8]

Bits 18-22: 8 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[9]

Bits 24-28: 9 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR3

regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ[14]
rw
SQ[13]
rw
SQ[12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[12]
rw
SQ[11]
rw
SQ[10]
rw
Toggle fields

SQ[10]

Bits 0-4: 10 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[11]

Bits 6-10: 11 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[12]

Bits 12-16: 12 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[13]

Bits 18-22: 13 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[14]

Bits 24-28: 14 conversion in regular sequence.

Allowed values: 0x0-0x12

SQR4

regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ[16]
rw
SQ[15]
rw
Toggle fields

SQ[15]

Bits 0-4: 15 conversion in regular sequence.

Allowed values: 0x0-0x12

SQ[16]

Bits 6-10: 16 conversion in regular sequence.

Allowed values: 0x0-0x12

DR

regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-15: regularDATA.

Allowed values: 0x0-0xffff

JSQR

injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ[4]
rw
JSQ[3]
rw
JSQ[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ[2]
rw
JSQ[1]
rw
JEXTEN
rw
JEXTSEL
rw
JL
rw
Toggle fields

JL

Bits 0-1: JL.

Allowed values: 0x0-0x3

JEXTSEL

Bits 2-5: JEXTSEL.

Allowed values:
0: TIM1_TRGO: Timer 1 TRGO event
1: TIM1_CC4: Timer 1 CC4 event
2: TIM2_TRGO: Timer 2 TRGO event
3: TIM2_CC1: Timer 2 CC1 event
4: TIM3_CC4: Timer 3 CC4 event
6: EXTI15: EXTI line 15
8: TIM1_TRGO2: Timer 1 TRGO2 event
11: TIM3_CC3: Timer 3 CC3 event
12: TIM3_TRGO: Timer 3 TRGO event
13: TIM3_CC1: Timer 3 CC1 event
14: TIM6_TRGO: Timer 6 TRGO event
15: TIM15_TRGO: Timer 15 TRGO event

JEXTEN

Bits 6-7: JEXTEN.

Allowed values:
0: Disabled: Trigger detection disabled
1: RisingEdge: Trigger detection on the rising edge
2: FallingEdge: Trigger detection on the falling edge
3: BothEdges: Trigger detection on both the rising and falling edges

JSQ[1]

Bits 8-12: 1 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[2]

Bits 14-18: 2 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[3]

Bits 20-24: 3 conversion in injected sequence.

Allowed values: 0x0-0x13

JSQ[4]

Bits 26-30: 4 conversion in injected sequence.

Allowed values: 0x0-0x13

OFR[1]

offset register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[2]

offset register 2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[3]

offset register 3

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

OFR[4]

offset register 4

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET_EN
rw
OFFSET_CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
Toggle fields

OFFSET

Bits 0-11: Data offset X for the channel programmed into bits OFFSET_CH.

Allowed values: 0x0-0xfff

OFFSET_CH

Bits 26-30: Channel selection for the data offset X.

Allowed values: 0x0-0x1f

OFFSET_EN

Bit 31: Offset X Enable.

Allowed values:
0: Disabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]
1: Enabled: This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]

JDR[1]

injected data register 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[2]

injected data register 2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[3]

injected data register 3

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

JDR[4]

injected data register 4

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-15: JDATA1.

Allowed values: 0x0-0xffff

AWD2CR

Analog Watchdog 2 Configuration Register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD2CH[0]

Bit 0: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[1]

Bit 1: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[2]

Bit 2: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[3]

Bit 3: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[4]

Bit 4: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[5]

Bit 5: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[6]

Bit 6: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[7]

Bit 7: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[8]

Bit 8: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[9]

Bit 9: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[10]

Bit 10: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[11]

Bit 11: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[12]

Bit 12: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[13]

Bit 13: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[14]

Bit 14: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[15]

Bit 15: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[16]

Bit 16: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[17]

Bit 17: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD2CH[18]

Bit 18: AWD2CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CR

Analog Watchdog 3 Configuration Register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

Toggle fields

AWD3CH[0]

Bit 0: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[1]

Bit 1: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[2]

Bit 2: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[3]

Bit 3: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[4]

Bit 4: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[5]

Bit 5: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[6]

Bit 6: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[7]

Bit 7: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[8]

Bit 8: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[9]

Bit 9: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[10]

Bit 10: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[11]

Bit 11: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[12]

Bit 12: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[13]

Bit 13: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[14]

Bit 14: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[15]

Bit 15: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[16]

Bit 16: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[17]

Bit 17: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

AWD3CH[18]

Bit 18: AWD3CH.

Allowed values:
0: NotMonitored: Input channel not monitored by AWDx
1: Monitored: Input channel monitored by AWDx

DIFSEL

Differential Mode Selection Register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

19/19 fields covered.

Toggle fields

DIFSEL[0]

Bit 0: Differential mode for channel 0.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[1]

Bit 1: Differential mode for channel 1.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[2]

Bit 2: Differential mode for channel 2.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[3]

Bit 3: Differential mode for channel 3.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[4]

Bit 4: Differential mode for channel 4.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[5]

Bit 5: Differential mode for channel 5.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[6]

Bit 6: Differential mode for channel 6.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[7]

Bit 7: Differential mode for channel 7.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[8]

Bit 8: Differential mode for channel 8.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[9]

Bit 9: Differential mode for channel 9.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[10]

Bit 10: Differential mode for channel 10.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[11]

Bit 11: Differential mode for channel 11.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[12]

Bit 12: Differential mode for channel 12.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[13]

Bit 13: Differential mode for channel 13.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[14]

Bit 14: Differential mode for channel 14.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[15]

Bit 15: Differential mode for channel 15.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[16]

Bit 16: Differential mode for channel 16.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[17]

Bit 17: Differential mode for channel 17.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

DIFSEL[18]

Bit 18: Differential mode for channel 18.

Allowed values:
0: SingleEnded: Input channel is configured in single-ended mode
1: Differential: Input channel is configured in differential mode

CALFACT

Calibration Factors

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-6: CALFACT_S.

Allowed values: 0x0-0x7f

CALFACT_D

Bits 16-22: CALFACT_D.

Allowed values: 0x0-0x7f

SEC_ADC_Common

0x52028300: Analog-to-Digital Converter

33/33 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

Toggle fields

ADRDY_MST

Bit 0: ADDRDY_MST.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_MST

Bit 1: EOSMP_MST.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_MST

Bit 2: EOC_MST.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_MST

Bit 3: EOS_MST.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_MST

Bit 4: OVR_MST.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_MST

Bit 5: JEOC_MST.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_MST

Bit 6: JEOS_MST.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_MST

Bit 7: AWD1_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_MST

Bit 8: AWD2_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_MST

Bit 9: AWD3_MST.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_MST

Bit 10: JQOVF_MST.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

ADRDY_SLV

Bit 16: ADRDY_SLV.

Allowed values:
0: NotReady: ADC is not ready to start conversion
1: Ready: ADC is ready to start conversion

EOSMP_SLV

Bit 17: EOSMP_SLV.

Allowed values:
0: NotEnded: End of sampling phase no yet reached
1: Ended: End of sampling phase reached

EOC_SLV

Bit 18: EOC_SLV.

Allowed values:
0: NotComplete: Regular conversion is not complete
1: Complete: Regular conversion complete

EOS_SLV

Bit 19: EOS_SLV.

Allowed values:
0: NotComplete: Regular sequence is not complete
1: Complete: Regular sequence complete

OVR_SLV

Bit 20: OVR_SLV.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

JEOC_SLV

Bit 21: JEOC_SLV.

Allowed values:
0: NotComplete: Injected conversion is not complete
1: Complete: Injected conversion complete

JEOS_SLV

Bit 22: JEOS_SLV.

Allowed values:
0: NotComplete: Injected sequence is not complete
1: Complete: Injected sequence complete

AWD1_SLV

Bit 23: AWD1_SLV.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD2_SLV

Bit 24: AWD2_SLV.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

AWD3_SLV

Bit 25: AWD3_SLV.

Allowed values:
0: NoEvent: No analog watchdog event occurred
1: Event: Analog watchdog event occurred

JQOVF_SLV

Bit 26: JQOVF_SLV.

Allowed values:
0: NoOverflow: No injected context queue overflow has occurred
1: Overflow: Injected context queue overflow has occurred

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VBATEN
rw
VSENSEEN
rw
VREFEN
rw
PRESC
rw
CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw
DMACFG
rw
DELAY
rw
DUAL
rw
Toggle fields

DUAL

Bits 0-4: DUAL.

Allowed values:
0: Independent: Independent mode
1: DualRJ: Dual, combined regular simultaneous + injected simultaneous mode
2: DualRA: Dual, combined regular simultaneous + alternate trigger mode
3: DualIJ: Dual, combined interleaved mode + injected simultaneous mode
5: DualJ: Dual, injected simultaneous mode only
6: DualR: Dual, regular simultaneous mode only
7: DualI: Dual, interleaved mode only
9: DualA: Dual, alternate trigger mode only

DELAY

Bits 8-11: DELAY.

Allowed values: 0x0-0xf

DMACFG

Bit 13: DMACFG.

Allowed values:
0: OneShotMode: DMA One Shot mode selected
1: CircularMode: DMA Circular mode selected

MDMA

Bits 14-15: MDMA.

Allowed values:
0: Disabled: MDMA mode disabled
1: Interleaved: Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)
2: Bits12_10: MDMA mode enabled for 12 and 10-bit resolution
3: Bits8_6: MDMA mode enabled for 8 and 6-bit resolution

CKMODE

Bits 16-17: ADC clock mode.

Allowed values:
0: Asynchronous: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
1: SyncDiv1: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
2: SyncDiv2: Use AHB clock rcc_hclk3 divided by 2
3: SyncDiv4: Use AHB clock rcc_hclk3 divided by 4

PRESC

Bits 18-21: ADC prescaler.

Allowed values:
0: Div1: Input ADC clock not divided
1: Div2: Input ADC clock divided by 2
2: Div4: Input ADC clock divided by 4
3: Div6: Input ADC clock divided by 6
4: Div8: Input ADC clock divided by 8
5: Div10: Input ADC clock divided by 10
6: Div12: Input ADC clock divided by 12
7: Div16: Input ADC clock divided by 16
8: Div32: Input ADC clock divided by 32
9: Div64: Input ADC clock divided by 64
10: Div128: Input ADC clock divided by 128
11: Div256: Input ADC clock divided by 256

VREFEN

Bit 22: VREFINT enable.

Allowed values:
0: Disabled: V_REFINT channel disabled
1: Enabled: V_REFINT channel enabled

VSENSEEN

Bit 23: Temperature sensor selection.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

VBATEN

Bit 24: VBAT selection.

Allowed values:
0: Disabled: The selected ADC channel disabled
1: Enabled: The selected ADC channel enabled

CDR

Common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: RDATA_MST.

Allowed values: 0x0-0xffff

RDATA_SLV

Bits 16-31: RDATA_SLV.

Allowed values: 0x0-0xffff

SEC_AES

0x520c0000: Advanced encryption standard hardware accelerator 1

40/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DINR
0xc DOUTR
0x10 KEYR0
0x14 KEYR1
0x18 KEYR2
0x1c KEYR3
0x20 IVR0
0x24 IVR1
0x28 IVR2
0x2c IVR3
0x30 KEYR4
0x34 KEYR5
0x38 KEYR6
0x3c KEYR7
0x40 SUSP0R
0x44 SUSP1R
0x48 SUSP2R
0x4c SUSP3R
0x50 SUSP4R
0x54 SUSP5R
0x58 SUSP6R
0x5c SUSP7R
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw
KEYSIZE
rw
CHMOD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GCMPH
rw
DMAOUTEN
rw
DMAINEN
rw
ERRIE
rw
CCFIE
rw
ERRC
rw
CCFC
rw
CHMOD
rw
MODE
rw
DATATYPE
rw
EN
rw
Toggle fields

EN

Bit 0: AES enable.

Allowed values:
0: Disabled: Disable AES
1: Enabled: Enable AES

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

Allowed values:
0: None: Word
1: HalfWord: Half-word (16-bit)
2: Byte: Byte (8-bit)
3: Bit: Bit

MODE

Bits 3-4: AES operating mode.

Allowed values:
0: Mode1: Mode 1: encryption
1: Mode2: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
2: Mode3: Mode 3: decryption
3: Mode4: Mode 4: key derivation then single decryption

CHMOD

Bits 5-6: AES chaining mode selection Bit1 Bit0.

Allowed values:
0: ECB: Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1
1: CBC: Cipher-block chaining (CBC)
2: CTR: Counter mode (CTR)
3: GCM: Galois counter mode (GCM) and Galois message authentication code (GMAC)

CCFC

Bit 7: Computation Complete Flag Clear.

Allowed values:
1: Clear: Clear computation complete flag

ERRC

Bit 8: Error clear.

Allowed values:
1: Clear: Clear RDERR and WRERR flags

CCFIE

Bit 9: CCF flag interrupt enable.

Allowed values:
0: Disabled: Disable (mask) CCF interrupt
1: Enabled: Enable CCF interrupt

ERRIE

Bit 10: Error interrupt enable.

Allowed values:
0: Disabled: Disable (mask) error interrupt
1: Enabled: Enable error interrupt

DMAINEN

Bit 11: Enable DMA management of data input phase.

Allowed values:
0: Disabled: Disable DMA Input
1: Enabled: Enable DMA Input

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

Allowed values:
0: Disabled: Disable DMA Output
1: Enabled: Enabled DMA Output

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

Allowed values:
0: Init: Init phase
1: Header: Header phase
2: Payload: Payload phase
3: Final: Final Phase

CHMOD2

Bit 16: AES chaining mode Bit2.

Allowed values:
0: CHMOD: Mode as per CHMOD (ECB, CBC, CTR, GCM)
1: CCM: Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)

KEYSIZE

Bit 18: Key size selection.

Allowed values:
0: AES128: 128
1: AES256: 256

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

Allowed values: 0x0-0xf

SR

status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
WRERR
r
RDERR
r
CCF
r
Toggle fields

CCF

Bit 0: Computation complete flag.

Allowed values:
0: Complete: Computation complete
1: NotComplete: Computation not complete

RDERR

Bit 1: Read error flag.

Allowed values:
0: NoError: Read error not detected
1: Error: Read error detected

WRERR

Bit 2: Write error flag.

Allowed values:
0: NoError: Write error not detected
1: Error: Write error detected

BUSY

Bit 3: Busy flag.

Allowed values:
0: Idle: Idle
1: Busy: Busy

DINR

data input register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
rw
Toggle fields

DIN

Bits 0-31: Data Input Register.

Allowed values: 0x0-0xffffffff

DOUTR

data output register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-31: Data output register.

Allowed values: 0x0-0xffffffff

KEYR0

key register 0

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits[31:0].

Allowed values: 0x0-0xffffffff

KEYR1

key register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [63:32]).

Allowed values: 0x0-0xffffffff

KEYR2

key register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [95:64]).

Allowed values: 0x0-0xffffffff

KEYR3

key register 3

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [127:96]).

Allowed values: 0x0-0xffffffff

IVR0

initialization vector register 0

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: initialization vector register (LSB IVR [31:0]).

Allowed values: 0x0-0xffffffff

IVR1

initialization vector register 1

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (IVR [63:32]).

Allowed values: 0x0-0xffffffff

IVR2

initialization vector register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (IVR [95:64]).

Allowed values: 0x0-0xffffffff

IVR3

initialization vector register 3

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI
rw
Toggle fields

IVI

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

Allowed values: 0x0-0xffffffff

KEYR4

key register 4

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [159:128]).

Allowed values: 0x0-0xffffffff

KEYR5

key register 5

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [191:160]).

Allowed values: 0x0-0xffffffff

KEYR6

key register 6

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [223:192]).

Allowed values: 0x0-0xffffffff

KEYR7

key register 7

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-31: Cryptographic key, bits [255:224]).

Allowed values: 0x0-0xffffffff

SUSP0R

AES suspend register 0

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 0.

Allowed values: 0x0-0xffffffff

SUSP1R

AES suspend register 1

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 1.

Allowed values: 0x0-0xffffffff

SUSP2R

AES suspend register 2

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 2.

Allowed values: 0x0-0xffffffff

SUSP3R

AES suspend register 3

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 3.

Allowed values: 0x0-0xffffffff

SUSP4R

AES suspend register 4

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 4.

Allowed values: 0x0-0xffffffff

SUSP5R

AES suspend register 5

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 5.

Allowed values: 0x0-0xffffffff

SUSP6R

AES suspend register 6

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 6.

Allowed values: 0x0-0xffffffff

SUSP7R

AES suspend register 7

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
rw
Toggle fields

SUSP

Bits 0-31: AES suspend register 7.

Allowed values: 0x0-0xffffffff

SEC_COMP

0x50010200: Comparator

2/23 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 COMP1_CSR
0x4 COMP2_CSR
Toggle registers

COMP1_CSR

Comparator 1 control and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

1/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1_LOCK
w
COMP1_VALUE
r
COMP1_SCALEN
rw
COMP1_BRGEN
rw
COMP1_BLANKING
rw
COMP1_HYST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1_POLARITY
rw
COMP1_INPSEL
rw
COMP1_INMSEL
rw
COMP1_PWRMODE
rw
COMP1_EN
rw
Toggle fields

COMP1_EN

Bit 0: Comparator 1 enable bit.

COMP1_PWRMODE

Bits 2-3: Power Mode of the comparator 1.

COMP1_INMSEL

Bits 4-6: Comparator 1 Input Minus connection configuration bit.

COMP1_INPSEL

Bit 7: Comparator1 input plus selection bit.

COMP1_POLARITY

Bit 15: Comparator 1 polarity selection bit.

COMP1_HYST

Bits 16-17: Comparator 1 hysteresis selection bits.

COMP1_BLANKING

Bits 18-20: Comparator 1 blanking source selection bits.

COMP1_BRGEN

Bit 22: Scaler bridge enable.

COMP1_SCALEN

Bit 23: Voltage scaler enable bit.

COMP1_VALUE

Bit 30: Comparator 1 output status bit.

COMP1_LOCK

Bit 31: COMP1_CSR register lock bit.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

1/12 fields covered.

Toggle fields

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-6: Comparator 2 Input Minus connection configuration bit.

COMP2_INPSEL

Bit 7: Comparator 2 Input Plus connection configuration bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: COMP2_CSR register lock bit.

SEC_CRC

0x50023000: Cyclic redundancy check calculation unit

0/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

Data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-7: General-purpose 8-bit data register bits.

CR

Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw
REV_IN
rw
POLYSIZE
rw
RESET
w
Toggle fields

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle fields

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Polynomialcoefficients
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Polynomialcoefficients
rw
Toggle fields

Polynomialcoefficients

Bits 0-31: Programmable polynomial.

SEC_CRS

0x50006000: Clock recovery system

9/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 ISR
0xc ICR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00004000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
SWSYNC
rw
AUTOTRIMEN
rw
CEN
rw
ESYNCIE
rw
ERRIE
rw
SYNCWARNIE
rw
SYNCOKIE
rw
Toggle fields

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Generate software SYNC event.

TRIM

Bits 8-14: HSI48 oscillator smooth trimming.

CFGR

configuration register

Offset: 0x4, size: 32, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL
rw
SYNCSRC
rw
SYNCDIV
rw
FELIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD
rw
Toggle fields

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNC divider.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

interrupt and status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEDIR
r
TRIMOVF
r
SYNCMISS
r
SYNCERR
r
ESYNCF
r
ERRF
r
SYNCWARNF
r
SYNCOKF
r
Toggle fields

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ESYNCC
rw
ERRC
rw
SYNCWARNC
rw
SYNCOKC
rw
Toggle fields

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: SYNC warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

SEC_DAC

0x50007400: DAC

49/49 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R[1]
0xc DHR12L[1]
0x10 DHR8R[1]
0x14 DHR12R[2]
0x18 DHR12L[2]
0x1c DHR8R[2]
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR[1]
0x30 DOR[2]
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR[1]
0x44 SHSR[2]
0x48 SHHR
0x4c SHRR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN[2]
rw
DMAUDRIE[2]
rw
DMAEN[2]
rw
MAMP[2]
rw
WAVE[2]
rw
TSEL2
rw
TEN[2]
rw
EN[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HFSEL
rw
CEN[1]
rw
DMAUDRIE[1]
rw
DMAEN[1]
rw
MAMP[1]
rw
WAVE[1]
rw
TSEL1
rw
TEN[1]
rw
EN[1]
rw
Toggle fields

EN[1]

Bit 0: DAC channel1 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[1]

Bit 1: DAC channel1 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL1

Bits 2-5: TSEL10.

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9

WAVE[1]

Bits 6-7: DAC channel1 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[1]

Bits 8-11: DAC channel1 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[1]

Bit 12: DAC channel1 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[1]

Bit 13: DAC channel1 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[1]

Bit 14: DAC channel1 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

HFSEL

Bit 15: HFSEL.

Allowed values:
0: Disabled: High frequency interface mode disabled
1: Enabled: High frequency interface mode enabled

EN[2]

Bit 16: DAC channel2 enable.

Allowed values:
0: Disabled: DAC Channel X disabled
1: Enabled: DAC Channel X enabled

TEN[2]

Bit 17: DAC channel2 trigger enable.

Allowed values:
0: Disabled: DAC Channel X trigger disabled
1: Enabled: DAC Channel X trigger enabled

TSEL2

Bits 18-21: TSEL20.

Allowed values:
0: Swtrig: Software trigger
1: Tim1Trgo: Timer 1 TRGO event
2: Tim2Trgo: Timer 2 TRGO event
3: Tim4Trgo: Timer 4 TRGO event
4: Tim5Trgo: Timer 5 TRGO event
5: Tim6Trgo: Timer 6 TRGO event
6: Tim7Trgo: Timer 7 TRGO event
7: Tim8Trgo: Timer 8 TRGO event
8: Tim15Trgo: Timer 15 TRGO event
11: Lptim1Out: LPTIM1 OUT event
12: Lptim2Out: LPTIM2 OUT event
13: Exti9: EXTI line 9

WAVE[2]

Bits 22-23: DAC channel2 noise/triangle wave generation enable.

Allowed values:
0: Disabled: Wave generation disabled
1: Noise: Noise wave generation enabled
2 (+): Triangle: Triangle wave generation enabled

MAMP[2]

Bits 24-27: DAC channel2 mask/amplitude selector.

Allowed values:
0: Amp1: Unmask bit0 of LFSR/ triangle amplitude equal to 1
1: Amp3: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
2: Amp7: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
3: Amp15: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
4: Amp31: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
5: Amp63: Unmask bits[5:0] of LFSR/ triangle amplitude equal 63
6: Amp127: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
7: Amp255: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
8: Amp511: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
9: Amp1023: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
10: Amp2047: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
11 (+): Amp4095: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

DMAEN[2]

Bit 28: DAC channel2 DMA enable.

Allowed values:
0: Disabled: DAC Channel X DMA mode disabled
1: Enabled: DAC Channel X DMA mode enabled

DMAUDRIE[2]

Bit 29: DAC channel2 DMA Underrun Interrupt enable.

Allowed values:
0: Disabled: DAC channel X DMA Underrun Interrupt disabled
1: Enabled: DAC channel X DMA Underrun Interrupt enabled

CEN[2]

Bit 30: DAC channel2 calibration enable.

Allowed values:
0: Normal: DAC Channel X Normal operating mode
1: Calibration: DAC Channel X calibration mode

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG[2]
w
SWTRIG[1]
w
Toggle fields

SWTRIG[1]

Bit 0: DAC channel1 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

SWTRIG[2]

Bit 1: DAC channel2 software trigger.

Allowed values:
0: NoTrigger: No trigger
1: Trigger: Trigger

DHR12R[1]

channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[1]

channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[1]

channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12R[2]

channel2 12-bit right-aligned data holding register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR12L[2]

channel2 12-bit left aligned data holding register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

Allowed values: 0x0-0xfff

DHR8R[2]

channel2 8-bit right aligned data holding register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDHR
rw
Toggle fields

DACCDHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

Allowed values: 0x0-0xff

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-11: DAC channel1 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 16-27: DAC channel2 12-bit right-aligned data.

Allowed values: 0x0-0xfff

DHR12LD

DUAL DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC[2]DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 4-15: DAC channel1 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DACC[2]DHR

Bits 20-31: DAC channel2 12-bit left-aligned data.

Allowed values: 0x0-0xfff

DHR8RD

DUAL DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC[2]DHR
rw
DACC[1]DHR
rw
Toggle fields

DACC[1]DHR

Bits 0-7: DAC channel1 8-bit right-aligned data.

Allowed values: 0x0-0xff

DACC[2]DHR

Bits 8-15: DAC channel2 8-bit right-aligned data.

Allowed values: 0x0-0xff

DOR[1]

channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

DOR[2]

channel2 data output register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACCDOR
r
Toggle fields

DACCDOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

Allowed values: 0x0-0xfff

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST[2]
r
CAL_FLAG[2]
r
DMAUDR[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST[1]
r
CAL_FLAG[1]
r
DMAUDR[1]
rw
Toggle fields

DMAUDR[1]

Bit 13: DAC channel1 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[1]

Bit 14: DAC channel1 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[1]

Bit 15: DAC channel1 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR[2]

Bit 29: DAC channel2 DMA underrun flag.

Allowed values:
0: NoUnderrun: No DMA underrun error condition occurred for DAC channel x
1: Underrun: DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG[2]

Bit 30: DAC channel2 calibration offset status.

Allowed values:
0: Lower: Calibration trimming value is lower than the offset correction value
1: Equal_Higher: Calibration trimming value is equal or greater than the offset correction value

BWST[2]

Bit 31: DAC channel2 busy writing sample time flag.

Allowed values:
0: Idle: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1: Busy: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM[1]
rw
Toggle fields

OTRIM[1]

Bits 0-4: DAC channel1 offset trimming value.

Allowed values: 0x0-0x1f

OTRIM[2]

Bits 16-20: DAC channel2 offset trimming value.

Allowed values: 0x0-0x1f

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE[1]
rw
Toggle fields

MODE[1]

Bits 0-2: DAC channel1 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

MODE[2]

Bits 16-18: DAC channel2 mode.

Allowed values:
0: NormalPinBuffer: Normal mode - DAC channelx is connected to external pin with Buffer enabled
1: NormalPinChipBuffer: Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
2: NormalPinNoBuffer: Normal mode - DAC channelx is connected to external pin with Buffer disabled
3: NormalChipNoBuffer: Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled
4: SHPinBuffer: S&H mode - DAC channelx is connected to external pin with Buffer enabled
5: SHPinChipBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled
6: SHPinNoBuffer: S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled
7: SHChipNoBuffer: S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled

SHSR[1]

DAC channel1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHSR[2]

DAC channel2 sample and hold sample time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE
rw
Toggle fields

TSAMPLE

Bits 0-9: DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored..

Allowed values: 0x0-0x3ff

SHHR

DAC Sample and Hold hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD[1]
rw
Toggle fields

THOLD[1]

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

THOLD[2]

Bits 16-25: DAC channel2 hold time (only valid in Sample and hold mode).

Allowed values: 0x0-0x3ff

SHRR

DAC Sample and Hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH[2]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH[1]
rw
Toggle fields

TREFRESH[1]

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

TREFRESH[2]

Bits 16-23: DAC channel2 refresh time (only valid in Sample and hold mode).

Allowed values: 0x0-0xff

SEC_DFSDM1

0x50016000: Digital filter for sigma delta modulators

84/400 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CH0CFGR1
0x4 CH0CFGR2
0x8 CH0AWSCDR
0xc CH0WDATR
0x10 CH0DATINR
0x14 CH0DLYR
0x20 CH1CFGR1
0x24 CH1CFGR2
0x28 CH1AWSCDR
0x2c CH1WDATR
0x30 CH1DATINR
0x34 CH1DLYR
0x40 CH2CFGR1
0x44 CH2CFGR2
0x48 CH2AWSCDR
0x4c CH2WDATR
0x50 CH2DATINR
0x54 CH2DLYR
0x60 CH3CFGR1
0x64 CH3CFGR2
0x68 CH3AWSCDR
0x6c CH3WDATR
0x70 CH3DATINR
0x74 CH3DLYR
0x80 CH4CFGR1
0x84 CH4CFGR2
0x88 CH4AWSCDR
0x8c CH4WDATR
0x90 CH4DATINR
0x94 CH4DLYR
0xa0 CH5CFGR1
0xa4 CH5CFGR2
0xa8 CH5AWSCDR
0xac CH5WDATR
0xb0 CH5DATINR
0xb4 CH5DLYR
0xc0 CH6CFGR1
0xc4 CH6CFGR2
0xc8 CH6AWSCDR
0xcc CH6WDATR
0xd0 CH6DATINR
0xd4 CH6DLYR
0xe0 CH7CFGR1
0xe4 CH7CFGR2
0xe8 CH7AWSCDR
0xec CH7WDATR
0xf0 CH7DATINR
0xf4 CH7DLYR
0x100 FLT0CR1
0x104 FLT0CR2
0x108 FLT0ISR
0x10c FLT0ICR
0x110 FLT0JCHGR
0x114 FLT0FCR
0x118 FLT0JDATAR
0x11c FLT0RDATAR
0x120 FLT0AWHTR
0x124 FLT0AWLTR
0x128 FLT0AWSR
0x12c FLT0AWCFR
0x130 FLT0EXMAX
0x134 FLT0EXMIN
0x138 FLT0CNVTIMR
0x180 FLT1CR1
0x184 FLT1CR2
0x188 FLT1ISR
0x18c FLT1ICR
0x190 FLT1JCHGR
0x194 FLT1FCR
0x198 FLT1JDATAR
0x19c FLT1RDATAR
0x1a4 FLT1AWLTR
0x1a8 FLT1AWSR
0x1ac FLT1AWCFR
0x1ac FLT1AWHTR
0x1b0 FLT1EXMAX
0x1b4 FLT1EXMIN
0x1b8 FLT1CNVTIMR
0x200 FLT2CR1
0x204 FLT2CR2
0x208 FLT2ISR
0x20c FLT2ICR
0x210 FLT2JCHGR
0x214 FLT2FCR
0x218 FLT2JDATAR
0x21c FLT2RDATAR
0x220 FLT2AWHTR
0x224 FLT2AWLTR
0x228 FLT2AWSR
0x22c FLT2AWCFR
0x230 FLT2EXMAX
0x234 FLT2EXMIN
0x238 FLT2CNVTIMR
0x280 FLT3CR1
0x284 FLT3CR2
0x288 FLT3ISR
0x28c FLT3ICR
0x290 FLT3JCHGR
0x294 FLT3FCR
0x298 FLT3JDATAR
0x29c FLT3RDATAR
0x2a0 FLT3AWHTR
0x2a4 FLT3AWLTR
0x2a8 FLT3AWSR
0x2ac FLT3AWCFR
0x2b0 FLT3EXMAX
0x2b4 FLT3EXMIN
0x2b8 FLT3CNVTIMR
Toggle registers

CH0CFGR1

channel configuration y register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH0CFGR2

channel configuration y register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH0AWSCDR

analog watchdog and short-circuit detector register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH0WDATR

channel watchdog filter data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH0DATINR

channel data input register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH0DLYR

DFSDM channel y delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: Pulses to skip for input data skipping function.

CH1CFGR1

CHCFG1R1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH1CFGR2

CHCFG1R2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH1AWSCDR

AWSCD1R

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH1WDATR

CHWDAT1R

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH1DATINR

CHDATIN1R

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH1DLYR

DFSDM channel y delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH2CFGR1

CHCFG2R1

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH2CFGR2

CHCFG2R2

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH2AWSCDR

AWSCD2R

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH2WDATR

CHWDAT2R

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH2DATINR

CHDATIN2R

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH2DLYR

DFSDM channel y delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH3CFGR1

CHCFG3R1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH3CFGR2

CHCFG3R2

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH3AWSCDR

AWSCD3R

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH3WDATR

CHWDAT3R

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH3DATINR

CHDATIN3R

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH3DLYR

DFSDM channel y delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH4CFGR1

CHCFG4R1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH4CFGR2

CHCFG4R2

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH4AWSCDR

AWSCD4R

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH4WDATR

CHWDAT4R

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH4DATINR

CHDATIN4R

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH4DLYR

DFSDM channel y delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH5CFGR1

CHCFG5R1

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH5CFGR2

CHCFG5R2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH5AWSCDR

AWSCD5R

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH5WDATR

CHWDAT5R

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH5DATINR

CHDATIN5R

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH5DLYR

DFSDM channel y delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: read-only.

CH6CFGR1

CHCFG6R1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH6CFGR2

CH6CFGR2

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH6AWSCDR

AWSCD6R

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH6WDATR

CHWDAT6R

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH6DATINR

CHDATIN6R

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH6DLYR

DFSDM channel y delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH7CFGR1

CHCFG7R1

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw
CKOUTSRC
rw
CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw
DATMPX
rw
CHINSEL
rw
CHEN
rw
CKABEN
rw
SCDEN
rw
SPICKSEL
rw
SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: Output serial clock divider.

CKOUTSRC

Bit 30: Output serial clock source selection.

DFSDMEN

Bit 31: Global enable for DFSDM interface.

CH7CFGR2

CHCFG7R2

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw
DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH7AWSCDR

AWSCD7R

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw
AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw
SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH7WDATR

CHWDAT7R

Offset: 0xec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
rw
Toggle fields

WDATA

Bits 0-15: WDATA.

CH7DATINR

CHDATIN7R

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH7DLYR

DFSDM channel y delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

FLT0CR1

control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT0CR2

control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT0ISR

interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT0ICR

interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT0JCHGR

injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT0FCR

filter control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT0JDATAR

data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT0RDATAR

data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT0AWHTR

analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT0AWLTR

analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT0AWSR

analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT0AWCFR

analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT0EXMAX

Extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT0EXMIN

Extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT0CNVTIMR

conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT1CR1

control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT1CR2

control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT1ISR

interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT1ICR

interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT1JCHGR

injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT1FCR

filter control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT1JDATAR

data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT1RDATAR

data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT1AWLTR

analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT1AWSR

analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT1AWCFR

analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT1AWHTR

analog watchdog high threshold register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT1EXMAX

Extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT1EXMIN

Extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT1CNVTIMR

conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT2CR1

control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT2CR2

control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT2ISR

interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT2ICR

interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT2JCHGR

injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT2FCR

filter control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT2JDATAR

data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT2RDATAR

data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT2AWHTR

analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT2AWLTR

analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT2AWSR

analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT2AWCFR

analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT2EXMAX

Extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT2EXMIN

Extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT2CNVTIMR

conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

FLT3CR1

control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw
FAST
rw
RCH
rw
RDMAEN
rw
RSYNC
rw
RCONT
rw
RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw
JEXTSEL
rw
JDMAEN
rw
JSCAN
rw
JSYNC
rw
JSWSTART
rw
DFEN
rw
Toggle fields

DFEN

Bit 0: DFSDM enable.

JSWSTART

Bit 1: Start a conversion of the injected group of channels.

JSYNC

Bit 3: Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger.

JSCAN

Bit 4: Scanning conversion mode for injected conversions.

JDMAEN

Bit 5: DMA channel enabled to read data for the injected channel group.

JEXTSEL

Bits 8-10: Trigger signal selection for launching injected conversions.

JEXTEN

Bits 13-14: Trigger enable and trigger edge selection for injected conversions.

RSWSTART

Bit 17: Software start of a conversion on the regular channel.

RCONT

Bit 18: Continuous mode selection for regular conversions.

RSYNC

Bit 19: Launch regular conversion synchronously with DFSDM0.

RDMAEN

Bit 21: DMA channel enabled to read data for the regular conversion.

RCH

Bits 24-26: Regular channel selection.

FAST

Bit 29: Fast conversion mode selection for regular conversions.

AWFSEL

Bit 30: Analog watchdog fast mode select.

FLT3CR2

control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw
CKABIE
rw
SCDIE
rw
AWDIE
rw
ROVRIE
rw
JOVRIE
rw
REOCIE
rw
JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: Injected end of conversion interrupt enable.

REOCIE

Bit 1: Regular end of conversion interrupt enable.

JOVRIE

Bit 2: Injected data overrun interrupt enable.

ROVRIE

Bit 3: Regular data overrun interrupt enable.

AWDIE

Bit 4: Analog watchdog interrupt enable.

SCDIE

Bit 5: Short-circuit detector interrupt enable.

CKABIE

Bit 6: Clock absence interrupt enable.

EXCH

Bits 8-15: Extremes detector channel selection.

AWDCH

Bits 16-23: Analog watchdog channel selection.

FLT3ISR

interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r
CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r
JCIP
r
AWDF
r
ROVRF
r
JOVRF
r
REOCF
r
JEOCF
r
Toggle fields

JEOCF

Bit 0: End of injected conversion flag.

REOCF

Bit 1: End of regular conversion flag.

JOVRF

Bit 2: Injected conversion overrun flag.

ROVRF

Bit 3: Regular conversion overrun flag.

AWDF

Bit 4: Analog watchdog.

JCIP

Bit 13: Injected conversion in progress status.

RCIP

Bit 14: Regular conversion in progress status.

CKABF

Bits 16-23: Clock absence flag.

SCDF

Bits 24-31: short-circuit detector flag.

FLT3ICR

interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw
CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw
CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: Clear the injected conversion overrun flag.

CLRROVRF

Bit 3: Clear the regular conversion overrun flag.

CLRCKABF

Bits 16-23: Clear the clock absence flag.

CLRSCDF

Bits 24-31: Clear the short-circuit detector flag.

FLT3JCHGR

injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: Injected channel group selection.

FLT3FCR

filter control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw
FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: Integrator oversampling ratio (averaging length).

FOSR

Bits 16-25: Sinc filter oversampling ratio (decimation rate).

FORD

Bits 29-31: Sinc filter order.

FLT3JDATAR

data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
JDATACH
r
Toggle fields

JDATACH

Bits 0-2: Injected channel most recently converted.

JDATA

Bits 8-31: Injected group conversion data.

FLT3RDATAR

data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
RPEND
r
RDATACH
r
Toggle fields

RDATACH

Bits 0-2: Regular channel most recently converted.

RPEND

Bit 4: Regular channel pending data.

RDATA

Bits 8-31: Regular channel conversion data.

FLT3AWHTR

analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw
BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: Break signal assignment to analog watchdog high threshold event.

AWHT

Bits 8-31: Analog watchdog high threshold.

FLT3AWLTR

analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw
BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: Break signal assignment to analog watchdog low threshold event.

AWLT

Bits 8-31: Analog watchdog low threshold.

FLT3AWSR

analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r
AWLTF
r
Toggle fields

AWLTF

Bits 0-7: Analog watchdog low threshold flag.

AWHTF

Bits 8-15: Analog watchdog high threshold flag.

FLT3AWCFR

analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw
CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: Clear the analog watchdog low threshold flag.

CLRAWHTF

Bits 8-15: Clear the analog watchdog high threshold flag.

FLT3EXMAX

Extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r
EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: Extremes detector maximum data channel.

EXMAX

Bits 8-31: Extremes detector maximum value.

FLT3EXMIN

Extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
r
EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: Extremes detector minimum data channel.

EXMIN

Bits 8-31: EXMIN.

FLT3CNVTIMR

conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN.

SEC_DMA1

0x50020000: Direct memory access controller

168/240 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

SEC_DMA2

0x50020400: Direct memory access controller

168/240 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IFCR
0x8 CR [1]
0xc NDTR [1]
0x10 PAR [1]
0x14 M0AR [1]
0x18 M1AR [1]
0x1c CR [2]
0x20 NDTR [2]
0x24 PAR [2]
0x28 M0AR [2]
0x2c M1AR [2]
0x30 CR [3]
0x34 NDTR [3]
0x38 PAR [3]
0x3c M0AR [3]
0x40 M1AR [3]
0x44 CR [4]
0x48 NDTR [4]
0x4c PAR [4]
0x50 M0AR [4]
0x54 M1AR [4]
0x58 CR [5]
0x5c NDTR [5]
0x60 PAR [5]
0x64 M0AR [5]
0x68 M1AR [5]
0x6c CR [6]
0x70 NDTR [6]
0x74 PAR [6]
0x78 M0AR [6]
0x7c M1AR [6]
0x80 CR [7]
0x84 NDTR [7]
0x88 PAR [7]
0x8c M0AR [7]
0x90 M1AR [7]
0x94 CR [8]
0x98 NDTR [8]
0x9c PAR [8]
0xa0 M0AR [8]
0xa4 M1AR [8]
Toggle registers

ISR

interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

GIF[1]

Bit 0: Channel 1 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[1]

Bit 1: Channel 1 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[1]

Bit 2: Channel 1 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[1]

Bit 3: Channel 1 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[2]

Bit 4: Channel 2 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[2]

Bit 5: Channel 2 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[2]

Bit 6: Channel 2 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[2]

Bit 7: Channel 2 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[3]

Bit 8: Channel 3 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[3]

Bit 9: Channel 3 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[3]

Bit 10: Channel 3 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[3]

Bit 11: Channel 3 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[4]

Bit 12: Channel 4 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[4]

Bit 13: Channel 4 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[4]

Bit 14: Channel 4 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[4]

Bit 15: Channel 4 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[5]

Bit 16: Channel 5 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[5]

Bit 17: Channel 5 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[5]

Bit 18: Channel 5 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[5]

Bit 19: Channel 5 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[6]

Bit 20: Channel 6 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[6]

Bit 21: Channel 6 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[6]

Bit 22: Channel 6 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[6]

Bit 23: Channel 6 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[7]

Bit 24: Channel 7 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[7]

Bit 25: Channel 7 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[7]

Bit 26: Channel 7 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[7]

Bit 27: Channel 7 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

GIF[8]

Bit 28: Channel 8 Global interrupt flag.

Allowed values:
0: NoEvent: No transfer error, half event, complete event
1: Event: A transfer error, half event or complete event has occured

TCIF[8]

Bit 29: Channel 8 Transfer Complete flag.

Allowed values:
0: NotComplete: No transfer complete event
1: Complete: A transfer complete event has occured

HTIF[8]

Bit 30: Channel 8 Half Transfer Complete flag.

Allowed values:
0: NotHalf: No half transfer event
1: Half: A half transfer event has occured

TEIF[8]

Bit 31: Channel 8 Transfer Error flag.

Allowed values:
0: NoError: No transfer error
1: Error: A transfer error has occured

IFCR

interrupt flag clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

CGIF[1]

Bit 0: Channel 1 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[1]

Bit 1: Channel 1 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[1]

Bit 2: Channel 1 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[1]

Bit 3: Channel 1 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[2]

Bit 4: Channel 2 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[2]

Bit 5: Channel 2 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[2]

Bit 6: Channel 2 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[2]

Bit 7: Channel 2 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[3]

Bit 8: Channel 3 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[3]

Bit 9: Channel 3 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[3]

Bit 10: Channel 3 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[3]

Bit 11: Channel 3 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[4]

Bit 12: Channel 4 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[4]

Bit 13: Channel 4 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[4]

Bit 14: Channel 4 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[4]

Bit 15: Channel 4 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[5]

Bit 16: Channel 5 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[5]

Bit 17: Channel 5 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[5]

Bit 18: Channel 5 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[5]

Bit 19: Channel 5 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[6]

Bit 20: Channel 6 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[6]

Bit 21: Channel 6 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[6]

Bit 22: Channel 6 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[6]

Bit 23: Channel 6 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[7]

Bit 24: Channel 7 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[7]

Bit 25: Channel 7 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[7]

Bit 26: Channel 7 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[7]

Bit 27: Channel 7 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CGIF[8]

Bit 28: Channel 8 Global interrupt clear.

Allowed values:
1: Clear: Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register

CTCIF[8]

Bit 29: Channel 8 Transfer Complete clear.

Allowed values:
1: Clear: Clears the TCIF flag in the ISR register

CHTIF[8]

Bit 30: Channel 8 Half Transfer clear.

Allowed values:
1: Clear: Clears the HTIF flag in the ISR register

CTEIF[8]

Bit 31: Channel 8 Transfer Error clear.

Allowed values:
1: Clear: Clears the TEIF flag in the ISR register

CR [1]

channel x configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [1]

channel x number of data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [1]

channel x peripheral address register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [1]

channel x memory address register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [1]

channel x memory address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [2]

channel x configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [2]

channel x number of data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [2]

channel x peripheral address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [2]

channel x memory address register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [2]

channel x memory address register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [3]

channel x configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [3]

channel x number of data register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [3]

channel x peripheral address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [3]

channel x memory address register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [3]

channel x memory address register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [4]

channel x configuration register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [4]

channel x number of data register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [4]

channel x peripheral address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [4]

channel x memory address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [4]

channel x memory address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [5]

channel x configuration register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [5]

channel x number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [5]

channel x peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [5]

channel x memory address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [5]

channel x memory address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [6]

channel x configuration register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [6]

channel x number of data register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [6]

channel x peripheral address register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [6]

channel x memory address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [6]

channel x memory address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [7]

channel x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [7]

channel x number of data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [7]

channel x peripheral address register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [7]

channel x memory address register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [7]

channel x memory address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

CR [8]

channel x configuration register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

12/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
DSEC
rw
SSEC
rw
SECM
rw
CT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBM
rw
MEM2MEM
rw
PL
rw
MSIZE
rw
PSIZE
rw
MINC
rw
PINC
rw
CIRC
rw
DIR
rw
TEIE
rw
HTIE
rw
TCIE
rw
EN
rw
Toggle fields

EN

Bit 0: Channel enable.

Allowed values:
0: Disabled: Channel disabled
1: Enabled: Channel enabled

TCIE

Bit 1: Transfer complete interrupt enable.

Allowed values:
0: Disabled: Transfer Complete interrupt disabled
1: Enabled: Transfer Complete interrupt enabled

HTIE

Bit 2: Half transfer interrupt enable.

Allowed values:
0: Disabled: Half Transfer interrupt disabled
1: Enabled: Half Transfer interrupt enabled

TEIE

Bit 3: Transfer error interrupt enable.

Allowed values:
0: Disabled: Transfer Error interrupt disabled
1: Enabled: Transfer Error interrupt enabled

DIR

Bit 4: Data transfer direction.

Allowed values:
0: FromPeripheral: Read from peripheral
1: FromMemory: Read from memory

CIRC

Bit 5: Circular mode.

Allowed values:
0: Disabled: Circular buffer disabled
1: Enabled: Circular buffer enabled

PINC

Bit 6: Peripheral increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

MINC

Bit 7: Memory increment mode.

Allowed values:
0: Disabled: Increment mode disabled
1: Enabled: Increment mode enabled

PSIZE

Bits 8-9: Peripheral size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

MSIZE

Bits 10-11: Memory size.

Allowed values:
0: Bits8: 8-bit size
1: Bits16: 16-bit size
2: Bits32: 32-bit size

PL

Bits 12-13: Channel priority level.

Allowed values:
0: Low: Low priority
1: Medium: Medium priority
2: High: High priority
3: VeryHigh: Very high priority

MEM2MEM

Bit 14: Memory to memory mode.

Allowed values:
0: Disabled: Memory to memory mode disabled
1: Enabled: Memory to memory mode enabled

DBM

Bit 15: double-buffer mode.

CT

Bit 16: current target memory of DMA transfer in double-buffer mode.

SECM

Bit 17: secure mode.

SSEC

Bit 18: security of the DMA transfer from the source.

DSEC

Bit 19: security of the DMA transfer to the destination.

PRIV

Bit 20: privileged mode.

NDTR [8]

channel x number of data register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-17: Number of data to transfer.

Allowed values: 0x0-0xffff

PAR [8]

channel x peripheral address register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA
rw
Toggle fields

PA

Bits 0-31: Peripheral address.

M0AR [8]

channel x memory address register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: Memory address.

M1AR [8]

channel x memory address register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA
rw
Toggle fields

MA

Bits 0-31: peripheral address.

SEC_DMAMUX1

0x50020800: Direct memory access Multiplexer

136/172 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CCR[0]
0x4 CCR[1]
0x8 CCR[2]
0xc CCR[3]
0x10 CCR[4]
0x14 CCR[5]
0x18 CCR[6]
0x1c CCR[7]
0x20 CCR[8]
0x24 CCR[9]
0x28 CCR[10]
0x2c CCR[11]
0x30 CCR[12]
0x34 CCR[13]
0x38 CCR[14]
0x3c CCR[15]
0x80 CSR
0x84 CCFR
0x100 RGCR[0]
0x104 RGCR[1]
0x108 RGCR[2]
0x10c RGCR[3]
0x140 RGSR
0x144 RGCFR
Toggle registers

CCR[0]

DMA Multiplexer Channel 0 Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[1]

DMA Multiplexer Channel 1 Control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[2]

DMA Multiplexer Channel 2 Control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[3]

DMA Multiplexer Channel 3 Control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[4]

DMA Multiplexer Channel 4 Control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[5]

DMA Multiplexer Channel 5 Control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[6]

DMA Multiplexer Channel 6 Control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[7]

DMA Multiplexer Channel 7 Control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[8]

DMA Multiplexer Channel 8 Control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[9]

DMA Multiplexer Channel 9 Control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[10]

DMA Multiplexer Channel 10 Control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[11]

DMA Multiplexer Channel 11 Control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[12]

DMA Multiplexer Channel 12 Control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[13]

DMA Multiplexer Channel 13 Control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[14]

DMA Multiplexer Channel 14 Control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CCR[15]

DMA Multiplexer Channel 15 Control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw
NBREQ
rw
SPOL
rw
SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw
SOIE
rw
DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

Allowed values:
0: Disabled: Synchronization overrun interrupt disabled
1: Enabled: Synchronization overrun interrupt enabled

EGE

Bit 9: Event Generation Enable.

Allowed values:
0: Disabled: Event generation disabled
1: Enabled: Event generation enabled

SE

Bit 16: Synchronization enable.

Allowed values:
0: Disabled: Synchronization disabled
1: Enabled: Synchronization enabled

SPOL

Bits 17-18: Sync polarity.

Allowed values:
0: NoEdge: No event, i.e. no synchronization nor detection
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

NBREQ

Bits 19-23: Nb request.

Allowed values: 0x0-0x1f

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

DMA Multiplexer Channel Status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

SOF[0]

Bit 0: Synchronization Overrun Flag 0.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[1]

Bit 1: Synchronization Overrun Flag 1.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[2]

Bit 2: Synchronization Overrun Flag 2.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[3]

Bit 3: Synchronization Overrun Flag 3.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[4]

Bit 4: Synchronization Overrun Flag 4.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[5]

Bit 5: Synchronization Overrun Flag 5.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[6]

Bit 6: Synchronization Overrun Flag 6.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[7]

Bit 7: Synchronization Overrun Flag 7.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[8]

Bit 8: Synchronization Overrun Flag 8.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[9]

Bit 9: Synchronization Overrun Flag 9.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[10]

Bit 10: Synchronization Overrun Flag 10.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[11]

Bit 11: Synchronization Overrun Flag 11.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[12]

Bit 12: Synchronization Overrun Flag 12.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[13]

Bit 13: Synchronization Overrun Flag 13.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[14]

Bit 14: Synchronization Overrun Flag 14.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

SOF[15]

Bit 15: Synchronization Overrun Flag 15.

Allowed values:
0: NoSyncEvent: No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ
1: SyncEvent: Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ

CCFR

DMA Channel Clear Flag Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF[15]
r/w1c
CSOF[14]
r/w1c
CSOF[13]
r/w1c
CSOF[12]
r/w1c
CSOF[11]
r/w1c
CSOF[10]
r/w1c
CSOF[9]
r/w1c
CSOF[8]
r/w1c
CSOF[7]
r/w1c
CSOF[6]
r/w1c
CSOF[5]
r/w1c
CSOF[4]
r/w1c
CSOF[3]
r/w1c
CSOF[2]
r/w1c
CSOF[1]
r/w1c
CSOF[0]
r/w1c
Toggle fields

CSOF[0]

Bit 0: Synchronization Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[1]

Bit 1: Synchronization Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[2]

Bit 2: Synchronization Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[3]

Bit 3: Synchronization Clear Overrun Flag 3.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[4]

Bit 4: Synchronization Clear Overrun Flag 4.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[5]

Bit 5: Synchronization Clear Overrun Flag 5.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[6]

Bit 6: Synchronization Clear Overrun Flag 6.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[7]

Bit 7: Synchronization Clear Overrun Flag 7.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[8]

Bit 8: Synchronization Clear Overrun Flag 8.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[9]

Bit 9: Synchronization Clear Overrun Flag 9.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[10]

Bit 10: Synchronization Clear Overrun Flag 10.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[11]

Bit 11: Synchronization Clear Overrun Flag 11.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[12]

Bit 12: Synchronization Clear Overrun Flag 12.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[13]

Bit 13: Synchronization Clear Overrun Flag 13.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[14]

Bit 14: Synchronization Clear Overrun Flag 14.

Allowed values:
1: Clear: Clear synchronization flag

CSOF[15]

Bit 15: Synchronization Clear Overrun Flag 15.

Allowed values:
1: Clear: Clear synchronization flag

RGCR[0]

DMA Request Generator 0 Control Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGCR[1]

DMA Request Generator 1 Control Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGCR[2]

DMA Request Generator 2 Control Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGCR[3]

DMA Request Generator 3 Control Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw
GPOL
rw
GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw
SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

Allowed values:
0: Disabled: Trigger overrun interrupt disabled
1: Enabled: Trigger overrun interrupt enabled

GE

Bit 16: Generation Enable.

Allowed values:
0: Disabled: DMA request generation disabled
1: Enabled: DMA request enabled

GPOL

Bits 17-18: Generation Polarity.

Allowed values:
0: NoEdge: No event, i.e. no detection nor generation
1: RisingEdge: Rising edge
2: FallingEdge: Falling edge
3: BothEdges: Rising and falling edges

GNBREQ

Bits 19-23: Number of Request.

Allowed values: 0x0-0x1f

RGSR

DMA Request Generator Status Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF[3]
r
OF[2]
r
OF[1]
r
OF[0]
r
Toggle fields

OF[0]

Bit 0: Generator Overrun Flag 0.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[1]

Bit 1: Generator Overrun Flag 1.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[2]

Bit 2: Generator Overrun Flag 2.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

OF[3]

Bit 3: Generator Overrun Flag 3.

Allowed values:
0: NoTrigger: No new trigger event occured on DMA request generator channel x, before the request counter underrun
1: Trigger: New trigger event occured on DMA request generator channel x, before the request counter underrun

RGCFR

DMA Request Generator Clear Flag Register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF[3]
r/w1c
COF[2]
r/w1c
COF[1]
r/w1c
COF[0]
r/w1c
Toggle fields

COF[0]

Bit 0: Generator Clear Overrun Flag 0.

Allowed values:
1: Clear: Clear overrun flag

COF[1]

Bit 1: Generator Clear Overrun Flag 1.

Allowed values:
1: Clear: Clear overrun flag

COF[2]

Bit 2: Generator Clear Overrun Flag 2.

Allowed values:
1: Clear: Clear overrun flag

COF[3]

Bit 3: Generator Clear Overrun Flag 3.

Allowed values:
1: Clear: Clear overrun flag

SEC_EXTI

0x5002f400: External interrupt/event controller

0/302 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc RPR1
0x10 FPR1
0x14 SECCFGR1
0x18 PRIVCFGR1
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c RPR2
0x30 FPR2
0x34 PRIVCFGR2
0x38 SECCFGR2
0x60 EXTICR1
0x64 EXTICR2
0x68 EXTICR3
0x6c EXTICR4
0x70 LOCKRG
0x80 IMR1
0x84 EMR1
0x90 IMR2
0x94 EMR2
Toggle registers

RTSR1

EXTI rising trigger selection register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT22
rw
RT21
rw
RT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15
rw
RT14
rw
RT13
rw
RT12
rw
RT11
rw
RT10
rw
RT9
rw
RT8
rw
RT7
rw
RT6
rw
RT5
rw
RT4
rw
RT3
rw
RT2
rw
RT1
rw
RT0
rw
Toggle fields

RT0

Bit 0: Rising trigger event configuration bit of configurable event input x.

RT1

Bit 1: Rising trigger event configuration bit of configurable event input x.

RT2

Bit 2: Rising trigger event configuration bit of configurable event input x.

RT3

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT4

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT5

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT6

Bit 6: Rising trigger event configuration bit of configurable event input x.

RT7

Bit 7: Rising trigger event configuration bit of configurable event input x.

RT8

Bit 8: Rising trigger event configuration bit of configurable event input x.

RT9

Bit 9: Rising trigger event configuration bit of configurable event input x.

RT10

Bit 10: Rising trigger event configuration bit of configurable event input x.

RT11

Bit 11: Rising trigger event configuration bit of configurable event input x.

RT12

Bit 12: Rising trigger event configuration bit of configurable event input x.

RT13

Bit 13: Rising trigger event configuration bit of configurable event input x.

RT14

Bit 14: Rising trigger event configuration bit of configurable event input x.

RT15

Bit 15: Rising trigger event configuration bit of configurable event input x.

RT16

Bit 16: Rising trigger event configuration bit of configurable event input x.

RT21

Bit 21: Rising trigger event configuration bit of configurable event input x.

RT22

Bit 22: Rising trigger event configuration bit of configurable event input x.

FTSR1

EXTI falling trigger selection register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT22
rw
FT21
rw
FT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15
rw
FT14
rw
FT13
rw
FT12
rw
FT11
rw
FT10
rw
FT9
rw
FT8
rw
FT7
rw
FT6
rw
FT5
rw
FT4
rw
FT3
rw
FT2
rw
FT1
rw
FT0
rw
Toggle fields

FT0

Bit 0: Falling trigger event configuration bit of configurable event input x.

FT1

Bit 1: Falling trigger event configuration bit of configurable event input x.

FT2

Bit 2: Falling trigger event configuration bit of configurable event input x.

FT3

Bit 3: Falling trigger event configuration bit of configurable event input x.

FT4

Bit 4: Falling trigger event configuration bit of configurable event input x.

FT5

Bit 5: Falling trigger event configuration bit of configurable event input x.

FT6

Bit 6: Falling trigger event configuration bit of configurable event input x.

FT7

Bit 7: Falling trigger event configuration bit of configurable event input x.

FT8

Bit 8: Falling trigger event configuration bit of configurable event input x.

FT9

Bit 9: Falling trigger event configuration bit of configurable event input x.

FT10

Bit 10: Falling trigger event configuration bit of configurable event input x.

FT11

Bit 11: Falling trigger event configuration bit of configurable event input x.

FT12

Bit 12: Falling trigger event configuration bit of configurable event input x.

FT13

Bit 13: Falling trigger event configuration bit of configurable event input x.

FT14

Bit 14: Falling trigger event configuration bit of configurable event input x.

FT15

Bit 15: Falling trigger event configuration bit of configurable event input x.

FT16

Bit 16: Falling trigger event configuration bit of configurable event input x.

FT21

Bit 21: Falling trigger event configuration bit of configurable event input x.

FT22

Bit 22: Falling trigger event configuration bit of configurable event input x.

SWIER1

EXTI software interrupt event register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI22
rw
SWI21
rw
SWI16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI15
rw
SWI14
rw
SWI13
rw
SWI12
rw
SWI11
rw
SWI10
rw
SWI9
rw
SWI8
rw
SWI7
rw
SWI6
rw
SWI5
rw
SWI4
rw
SWI3
rw
SWI2
rw
SWI1
rw
SWI0
rw
Toggle fields

SWI0

Bit 0: Software interrupt on event x.

SWI1

Bit 1: Software interrupt on event x.

SWI2

Bit 2: Software interrupt on event x.

SWI3

Bit 3: Software interrupt on event x.

SWI4

Bit 4: Software interrupt on event x.

SWI5

Bit 5: Software interrupt on event x.

SWI6

Bit 6: Software interrupt on event x.

SWI7

Bit 7: Software interrupt on event x.

SWI8

Bit 8: Software interrupt on event x.

SWI9

Bit 9: Software interrupt on event x.

SWI10

Bit 10: Software interrupt on event x.

SWI11

Bit 11: Software interrupt on event x.

SWI12

Bit 12: Software interrupt on event x.

SWI13

Bit 13: Software interrupt on event x.

SWI14

Bit 14: Software interrupt on event x.

SWI15

Bit 15: Software interrupt on event x.

SWI16

Bit 16: Software interrupt on event x.

SWI21

Bit 21: Software interrupt on event x.

SWI22

Bit 22: Software interrupt on event x.

RPR1

EXTI rising edge pending register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPIF22
rw
RPIF21
rw
RPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF15
rw
RPIF14
rw
RPIF13
rw
RPIF12
rw
RPIF11
rw
RPIF10
rw
RPIF9
rw
RPIF8
rw
RPIF7
rw
RPIF6
rw
RPIF5
rw
RPIF4
rw
RPIF3
rw
RPIF2
rw
RPIF1
rw
RPIF0
rw
Toggle fields

RPIF0

Bit 0: configurable event inputs x rising edge pending bit.

RPIF1

Bit 1: configurable event inputs x rising edge pending bit.

RPIF2

Bit 2: configurable event inputs x rising edge pending bit.

RPIF3

Bit 3: configurable event inputs x rising edge pending bit.

RPIF4

Bit 4: configurable event inputs x rising edge pending bit.

RPIF5

Bit 5: configurable event inputs x rising edge pending bit.

RPIF6

Bit 6: configurable event inputs x rising edge pending bit.

RPIF7

Bit 7: configurable event inputs x rising edge pending bit.

RPIF8

Bit 8: configurable event inputs x rising edge pending bit.

RPIF9

Bit 9: configurable event inputs x rising edge pending bit.

RPIF10

Bit 10: configurable event inputs x rising edge pending bit.

RPIF11

Bit 11: configurable event inputs x rising edge pending bit.

RPIF12

Bit 12: configurable event inputs x rising edge pending bit.

RPIF13

Bit 13: configurable event inputs x rising edge pending bit.

RPIF14

Bit 14: configurable event inputs x rising edge pending bit.

RPIF15

Bit 15: configurable event inputs x rising edge pending bit.

RPIF16

Bit 16: configurable event inputs x rising edge pending bit.

RPIF21

Bit 21: configurable event inputs x rising edge pending bit.

RPIF22

Bit 22: configurable event inputs x rising edge pending bit.

FPR1

EXTI falling edge pending register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPIF22
rw
FPIF21
rw
FPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF15
rw
FPIF14
rw
FPIF13
rw
FPIF12
rw
FPIF11
rw
FPIF10
rw
FPIF9
rw
FPIF8
rw
FPIF7
rw
FPIF6
rw
FPIF5
rw
FPIF4
rw
FPIF3
rw
FPIF2
rw
FPIF1
rw
FPIF0
rw
Toggle fields

FPIF0

Bit 0: configurable event inputs x falling edge pending bit..

FPIF1

Bit 1: configurable event inputs x falling edge pending bit..

FPIF2

Bit 2: configurable event inputs x falling edge pending bit..

FPIF3

Bit 3: configurable event inputs x falling edge pending bit..

FPIF4

Bit 4: configurable event inputs x falling edge pending bit..

FPIF5

Bit 5: configurable event inputs x falling edge pending bit..

FPIF6

Bit 6: configurable event inputs x falling edge pending bit..

FPIF7

Bit 7: configurable event inputs x falling edge pending bit..

FPIF8

Bit 8: configurable event inputs x falling edge pending bit..

FPIF9

Bit 9: configurable event inputs x falling edge pending bit..

FPIF10

Bit 10: configurable event inputs x falling edge pending bit..

FPIF11

Bit 11: configurable event inputs x falling edge pending bit..

FPIF12

Bit 12: configurable event inputs x falling edge pending bit..

FPIF13

Bit 13: configurable event inputs x falling edge pending bit..

FPIF14

Bit 14: configurable event inputs x falling edge pending bit..

FPIF15

Bit 15: configurable event inputs x falling edge pending bit..

FPIF16

Bit 16: configurable event inputs x falling edge pending bit..

FPIF21

Bit 21: configurable event inputs x falling edge pending bit..

FPIF22

Bit 22: configurable event inputs x falling edge pending bit..

SECCFGR1

EXTI security configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEC31
rw
SEC30
rw
SEC29
rw
SEC28
rw
SEC27
rw
SEC26
rw
SEC25
rw
SEC24
rw
SEC23
rw
SEC22
rw
SEC21
rw
SEC20
rw
SEC19
rw
SEC18
rw
SEC17
rw
SEC16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15
rw
SEC14
rw
SEC13
rw
SEC12
rw
SEC11
rw
SEC10
rw
SEC9
rw
SEC8
rw
SEC7
rw
SEC6
rw
SEC5
rw
SEC4
rw
SEC3
rw
SEC2
rw
SEC1
rw
SEC0
rw
Toggle fields

SEC0

Bit 0: Security enable on event input x.

SEC1

Bit 1: Security enable on event input x.

SEC2

Bit 2: Security enable on event input x.

SEC3

Bit 3: Security enable on event input x.

SEC4

Bit 4: Security enable on event input x.

SEC5

Bit 5: Security enable on event input x.

SEC6

Bit 6: Security enable on event input x.

SEC7

Bit 7: Security enable on event input x.

SEC8

Bit 8: Security enable on event input x.

SEC9

Bit 9: Security enable on event input x.

SEC10

Bit 10: Security enable on event input x.

SEC11

Bit 11: Security enable on event input x.

SEC12

Bit 12: Security enable on event input x.

SEC13

Bit 13: Security enable on event input x.

SEC14

Bit 14: Security enable on event input x.

SEC15

Bit 15: Security enable on event input x.

SEC16

Bit 16: Security enable on event input x.

SEC17

Bit 17: Security enable on event input x.

SEC18

Bit 18: Security enable on event input x.

SEC19

Bit 19: Security enable on event input x.

SEC20

Bit 20: Security enable on event input x.

SEC21

Bit 21: Security enable on event input x.

SEC22

Bit 22: Security enable on event input x.

SEC23

Bit 23: Security enable on event input x.

SEC24

Bit 24: Security enable on event input x.

SEC25

Bit 25: Security enable on event input x.

SEC26

Bit 26: Security enable on event input x.

SEC27

Bit 27: Security enable on event input x.

SEC28

Bit 28: Security enable on event input x.

SEC29

Bit 29: Security enable on event input x.

SEC30

Bit 30: Security enable on event input x.

SEC31

Bit 31: Security enable on event input x.

PRIVCFGR1

EXTI privilege configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

PRIV0

Bit 0: Security enable on event input x.

PRIV1

Bit 1: Security enable on event input x.

PRIV2

Bit 2: Security enable on event input x.

PRIV3

Bit 3: Security enable on event input x.

PRIV4

Bit 4: Security enable on event input x.

PRIV5

Bit 5: Security enable on event input x.

PRIV6

Bit 6: Security enable on event input x.

PRIV7

Bit 7: Security enable on event input x.

PRIV8

Bit 8: Security enable on event input x.

PRIV9

Bit 9: Security enable on event input x.

PRIV10

Bit 10: Security enable on event input x.

PRIV11

Bit 11: Security enable on event input x.

PRIV12

Bit 12: Security enable on event input x.

PRIV13

Bit 13: Security enable on event input x.

PRIV14

Bit 14: Security enable on event input x.

PRIV15

Bit 15: Security enable on event input x.

PRIV16

Bit 16: Security enable on event input x.

PRIV17

Bit 17: Security enable on event input x.

PRIV18

Bit 18: Security enable on event input x.

PRIV19

Bit 19: Security enable on event input x.

PRIV20

Bit 20: Security enable on event input x.

PRIV21

Bit 21: Security enable on event input x.

PRIV22

Bit 22: Security enable on event input x.

PRIV23

Bit 23: Security enable on event input x.

PRIV24

Bit 24: Security enable on event input x.

PRIV25

Bit 25: Security enable on event input x.

PRIV26

Bit 26: Security enable on event input x.

PRIV27

Bit 27: Security enable on event input x.

PRIV28

Bit 28: Security enable on event input x.

PRIV29

Bit 29: Security enable on event input x.

PRIV30

Bit 30: Security enable on event input x.

PRIV31

Bit 31: Security enable on event input x.

RTSR2

EXTI rising trigger selection register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT38
rw
RT37
rw
RT36
rw
RT35
rw
Toggle fields

RT35

Bit 3: Rising trigger event configuration bit of configurable event input x.

RT36

Bit 4: Rising trigger event configuration bit of configurable event input x.

RT37

Bit 5: Rising trigger event configuration bit of configurable event input x.

RT38

Bit 6: Rising trigger event configuration bit of configurable event input x.

FTSR2

EXTI falling trigger selection register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT38
rw
FT37
rw
FT36
rw
FT35
rw
Toggle fields

FT35

Bit 3: FT35.

FT36

Bit 4: FT36.

FT37

Bit 5: FT37.

FT38

Bit 6: FT38.

SWIER2

EXTI software interrupt event register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI38
rw
SWI37
rw
SWI36
rw
SWI35
rw
Toggle fields

SWI35

Bit 3: SWI35.

SWI36

Bit 4: SWI36.

SWI37

Bit 5: SWI37.

SWI38

Bit 6: SWI38.

RPR2

EXTI rising edge pending register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF38
rw
RPIF37
rw
RPIF36
rw
RPIF35
rw
Toggle fields

RPIF35

Bit 3: RPIF35.

RPIF36

Bit 4: RPIF36.

RPIF37

Bit 5: RPIF37.

RPIF38

Bit 6: RPIF38.

FPR2

EXTI falling edge pending register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF38
rw
FPIF37
rw
FPIF36
rw
FPIF35
rw
Toggle fields

FPIF35

Bit 3: FPIF35.

FPIF36

Bit 4: FPIF36.

FPIF37

Bit 5: FPIF37.

FPIF38

Bit 6: FPIF38.

PRIVCFGR2

EXTI security enable register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV42
rw
PRIV41
rw
PRIV40
rw
PRIV39
rw
PRIV38
rw
PRIV37
rw
PRIV36
rw
PRIV35
rw
PRIV34
rw
PRIV33
rw
PRIV32
rw
Toggle fields

PRIV32

Bit 0: PRIV32.

PRIV33

Bit 1: PRIV33.

PRIV34

Bit 2: PRIV34.

PRIV35

Bit 3: PRIV35.

PRIV36

Bit 4: PRIV36.

PRIV37

Bit 5: PRIV37.

PRIV38

Bit 6: PRIV38.

PRIV39

Bit 7: PRIV39.

PRIV40

Bit 8: PRIV40.

PRIV41

Bit 9: PRIV41.

PRIV42

Bit 10: PRIV42.

SECCFGR2

EXTI security enable register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC42
rw
SEC41
rw
SEC40
rw
SEC39
rw
SEC38
rw
SEC37
rw
SEC36
rw
SEC35
rw
SEC34
rw
SEC33
rw
SEC32
rw
Toggle fields

SEC32

Bit 0: SEC32.

SEC33

Bit 1: SEC33.

SEC34

Bit 2: SEC34.

SEC35

Bit 3: SEC35.

SEC36

Bit 4: SEC36.

SEC37

Bit 5: SEC37.

SEC38

Bit 6: SEC38.

SEC39

Bit 7: SEC39.

SEC40

Bit 8: SEC40.

SEC41

Bit 9: SEC41.

SEC42

Bit 10: SEC42.

EXTICR1

EXTI external interrupt selection register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI3
rw
EXTI2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI1
rw
EXTI0
rw
Toggle fields

EXTI0

Bits 0-7: EXTIm GPIO port selection.

EXTI1

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI2

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI3

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR2

EXTI external interrupt selection register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI7
rw
EXTI6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI5
rw
EXTI4
rw
Toggle fields

EXTI4

Bits 0-7: EXTIm GPIO port selection.

EXTI5

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI6

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI7

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR3

EXTI external interrupt selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI11
rw
EXTI10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI9
rw
EXTI8
rw
Toggle fields

EXTI8

Bits 0-7: EXTIm GPIO port selection.

EXTI9

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI10

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI11

Bits 24-31: EXTIm+3 GPIO port selection.

EXTICR4

EXTI external interrupt selection register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15
rw
EXTI14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI13
rw
EXTI12
rw
Toggle fields

EXTI12

Bits 0-7: EXTIm GPIO port selection.

EXTI13

Bits 8-15: EXTIm+1 GPIO port selection.

EXTI14

Bits 16-23: EXTIm+2 GPIO port selection.

EXTI15

Bits 24-31: EXTIm+3 GPIO port selection.

LOCKRG

EXTI lock register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
rw
Toggle fields

LOCK

Bit 0: LOCK.

IMR1

EXTI CPU wakeup with interrupt mask register

Offset: 0x80, size: 32, reset: 0xFF9E0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw
IM30
rw
IM29
rw
IM28
rw
IM27
rw
IM26
rw
IM25
rw
IM24
rw
IM23
rw
IM22
rw
IM21
rw
IM20
rw
IM19
rw
IM18
rw
IM17
rw
IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw
IM14
rw
IM13
rw
IM12
rw
IM11
rw
IM10
rw
IM9
rw
IM8
rw
IM7
rw
IM6
rw
IM5
rw
IM4
rw
IM3
rw
IM2
rw
IM1
rw
IM0
rw
Toggle fields

IM0

Bit 0: CPU wakeup with interrupt mask on event input.

IM1

Bit 1: CPU wakeup with interrupt mask on event input.

IM2

Bit 2: CPU wakeup with interrupt mask on event input.

IM3

Bit 3: CPU wakeup with interrupt mask on event input.

IM4

Bit 4: CPU wakeup with interrupt mask on event input.

IM5

Bit 5: CPU wakeup with interrupt mask on event input.

IM6

Bit 6: CPU wakeup with interrupt mask on event input.

IM7

Bit 7: CPU wakeup with interrupt mask on event input.

IM8

Bit 8: CPU wakeup with interrupt mask on event input.

IM9

Bit 9: CPU wakeup with interrupt mask on event input.

IM10

Bit 10: CPU wakeup with interrupt mask on event input.

IM11

Bit 11: CPU wakeup with interrupt mask on event input.

IM12

Bit 12: CPU wakeup with interrupt mask on event input.

IM13

Bit 13: CPU wakeup with interrupt mask on event input.

IM14

Bit 14: CPU wakeup with interrupt mask on event input.

IM15

Bit 15: CPU wakeup with interrupt mask on event input.

IM16

Bit 16: CPU wakeup with interrupt mask on event input.

IM17

Bit 17: CPU wakeup with interrupt mask on event input.

IM18

Bit 18: CPU wakeup with interrupt mask on event input.

IM19

Bit 19: CPU wakeup with interrupt mask on event input.

IM20

Bit 20: CPU wakeup with interrupt mask on event input.

IM21

Bit 21: CPU wakeup with interrupt mask on event input.

IM22

Bit 22: CPU wakeup with interrupt mask on event input.

IM23

Bit 23: CPU wakeup with interrupt mask on event input.

IM24

Bit 24: CPU wakeup with interrupt mask on event input.

IM25

Bit 25: CPU wakeup with interrupt mask on event input.

IM26

Bit 26: CPU wakeup with interrupt mask on event input.

IM27

Bit 27: CPU wakeup with interrupt mask on event input.

IM28

Bit 28: CPU wakeup with interrupt mask on event input.

IM29

Bit 29: CPU wakeup with interrupt mask on event input.

IM30

Bit 30: CPU wakeup with interrupt mask on event input.

IM31

Bit 31: CPU wakeup with interrupt mask on event input.

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM31
rw
EM30
rw
EM29
rw
EM28
rw
EM27
rw
EM26
rw
EM25
rw
EM24
rw
EM23
rw
EM22
rw
EM21
rw
EM20
rw
EM19
rw
EM18
rw
EM17
rw
EM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw
EM14
rw
EM13
rw
EM12
rw
EM11
rw
EM10
rw
EM9
rw
EM8
rw
EM7
rw
EM6
rw
EM5
rw
EM4
rw
EM3
rw
EM2
rw
EM1
rw
EM0
rw
Toggle fields

EM0

Bit 0: CPU wakeup with interrupt mask on event input.

EM1

Bit 1: CPU wakeup with interrupt mask on event input.

EM2

Bit 2: CPU wakeup with interrupt mask on event input.

EM3

Bit 3: CPU wakeup with interrupt mask on event input.

EM4

Bit 4: CPU wakeup with interrupt mask on event input.

EM5

Bit 5: CPU wakeup with interrupt mask on event input.

EM6

Bit 6: CPU wakeup with interrupt mask on event input.

EM7

Bit 7: CPU wakeup with interrupt mask on event input.

EM8

Bit 8: CPU wakeup with interrupt mask on event input.

EM9

Bit 9: CPU wakeup with interrupt mask on event input.

EM10

Bit 10: CPU wakeup with interrupt mask on event input.

EM11

Bit 11: CPU wakeup with interrupt mask on event input.

EM12

Bit 12: CPU wakeup with interrupt mask on event input.

EM13

Bit 13: CPU wakeup with interrupt mask on event input.

EM14

Bit 14: CPU wakeup with interrupt mask on event input.

EM15

Bit 15: CPU wakeup with interrupt mask on event input.

EM16

Bit 16: CPU wakeup with interrupt mask on event input.

EM17

Bit 17: CPU wakeup with interrupt mask on event input.

EM18

Bit 18: CPU wakeup with interrupt mask on event input.

EM19

Bit 19: CPU wakeup with interrupt mask on event input.

EM20

Bit 20: CPU wakeup with interrupt mask on event input.

EM21

Bit 21: CPU wakeup with interrupt mask on event input.

EM22

Bit 22: CPU wakeup with interrupt mask on event input.

EM23

Bit 23: CPU wakeup with interrupt mask on event input.

EM24

Bit 24: CPU wakeup with interrupt mask on event input.

EM25

Bit 25: CPU wakeup with interrupt mask on event input.

EM26

Bit 26: CPU wakeup with interrupt mask on event input.

EM27

Bit 27: CPU wakeup with interrupt mask on event input.

EM28

Bit 28: CPU wakeup with interrupt mask on event input.

EM29

Bit 29: CPU wakeup with interrupt mask on event input.

EM30

Bit 30: CPU wakeup with interrupt mask on event input.

EM31

Bit 31: CPU wakeup with interrupt mask on event input.

IMR2

EXTI CPUm wakeup with interrupt mask register

Offset: 0x90, size: 32, reset: 0x00000787, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM42
rw
IM41
rw
IM40
rw
IM38
rw
IM37
rw
IM36
rw
IM35
rw
IM34
rw
IM33
rw
IM32
rw
Toggle fields

IM32

Bit 0: CPU wakeup with interrupt mask on event input.

IM33

Bit 1: CPU wakeup with interrupt mask on event input.

IM34

Bit 2: CPU wakeup with interrupt mask on event input.

IM35

Bit 3: CPU wakeup with interrupt mask on event input.

IM36

Bit 4: CPU wakeup with interrupt mask on event input.

IM37

Bit 5: CPU wakeup with interrupt mask on event input.

IM38

Bit 6: CPU wakeup with interrupt mask on event input.

IM40

Bit 8: CPU wakeup with interrupt mask on event input.

IM41

Bit 9: CPU wakeup with interrupt mask on event input.

IM42

Bit 10: CPU wakeup with interrupt mask on event input.

EMR2

EXTI CPU wakeup with event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM42
rw
EM41
rw
EM40
rw
EM38
rw
EM37
rw
EM36
rw
EM35
rw
EM34
rw
EM33
rw
EM32
rw
Toggle fields

EM32

Bit 0: CPU wakeup with interrupt mask on event input.

EM33

Bit 1: CPU wakeup with interrupt mask on event input.

EM34

Bit 2: CPU wakeup with interrupt mask on event input.

EM35

Bit 3: CPU wakeup with interrupt mask on event input.

EM36

Bit 4: CPU wakeup with interrupt mask on event input.

EM37

Bit 5: CPU wakeup with interrupt mask on event input.

EM38

Bit 6: CPU wakeup with interrupt mask on event input.

EM40

Bit 8: CPU wakeup with interrupt mask on event input.

EM41

Bit 9: CPU wakeup with interrupt mask on event input.

EM42

Bit 10: CPU wakeup with interrupt mask on event input.

SEC_FDCAN1

0x5000a400: FDCAN1

36/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 ENDN
0xc DBTP
0x10 TEST
0x14 RWD
0x18 CCCR
0x1c NBTP
0x20 TSCC
0x24 TSCV
0x28 TOCC
0x2c TOCV
0x40 ECR
0x44 PSR
0x48 TDCR
0x50 IR
0x54 IE
0x58 ILS
0x5c ILE
0x80 RXGFC
0x84 XIDAM
0x88 HPMS
0x90 RXF0S
0x94 RXF0A
0x98 RXF1S
0x9c RXF1A
0xc0 TXBC
0xc4 TXFQS
0xc8 TXBRP
0xcc TXBAR
0xd0 TXBCR
0xd4 TXBTO
0xd8 TXBCF
0xdc TXBTIE
0xe0 TXBCIE
0xe4 TXEFS
0xe8 TXEFA
0x100 CKDIV
Toggle registers

CREL

FDCAN Core Release Register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r
STEP
r
SUBSTEP
r
YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r
DAY
r
Toggle fields

DAY

Bits 0-7: Timestamp Day.

MON

Bits 8-15: Timestamp Month.

YEAR

Bits 16-19: Timestamp Year.

SUBSTEP

Bits 20-23: Sub-step of Core release.

STEP

Bits 24-27: Step of Core release.

REL

Bits 28-31: Core release.

ENDN

FDCAN Core Release Register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: Endiannes Test Value.

DBTP

FDCAN Data Bit Timing and Prescaler Register

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw
DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw
DTSEG2
rw
DSJW
rw
Toggle fields

DSJW

Bits 0-3: Synchronization Jump Width.

DTSEG2

Bits 4-7: Data time segment after sample point.

DTSEG1

Bits 8-12: Data time segment after sample point.

DBRP

Bits 16-20: Data BIt Rate Prescaler.

TDC

Bit 23: Transceiver Delay Compensation.

TEST

FDCAN Test Register

Offset: 0x10, size: 32, reset: 0x00000010, access: Unspecified

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r
TX
rw
LBCK
rw
Toggle fields

LBCK

Bit 4: Loop Back mode.

TX

Bits 5-6: Loop Back mode.

RX

Bit 7: Control of Transmit Pin.

RWD

FDCAN RAM Watchdog Register

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r
WDC
rw
Toggle fields

WDC

Bits 0-7: Watchdog configuration.

WDV

Bits 8-15: Watchdog value.

CCCR

FDCAN CC Control Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw
TXP
rw
EFBI
rw
PXHD
rw
BSE
rw
FDOE
rw
TEST
rw
DAR
rw
MON
rw
CSR
rw
CSA
rw
ASM
rw
CCE
rw
INIT
rw
Toggle fields

INIT

Bit 0: Initialization.

CCE

Bit 1: Configuration Change Enable.

ASM

Bit 2: ASM Restricted Operation Mode.

CSA

Bit 3: Clock Stop Acknowledge.

CSR

Bit 4: Clock Stop Request.

MON

Bit 5: Bus Monitoring Mode.

DAR

Bit 6: Disable Automatic Retransmission.

TEST

Bit 7: Test Mode Enable.

FDOE

Bit 8: FD Operation Enable.

BSE

Bit 9: FDCAN Bit Rate Switching.

PXHD

Bit 12: Protocol Exception Handling Disable.

EFBI

Bit 13: Edge Filtering during Bus Integration.

TXP

Bit 14: TXP.

NISO

Bit 15: Non ISO Operation.

NBTP

FDCAN Nominal Bit Timing and Prescaler Register

Offset: 0x1c, size: 32, reset: 0x06000A03, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw
NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw
TSEG2
rw
Toggle fields

TSEG2

Bits 0-6: Nominal Time segment after sample point.

NTSEG1

Bits 8-15: Nominal Time segment before sample point.

NBRP

Bits 16-24: Bit Rate Prescaler.

NSJW

Bits 25-31: NSJW: Nominal (Re)Synchronization Jump Width.

TSCC

FDCAN Timestamp Counter Configuration Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: Timestamp Select.

TCP

Bits 16-19: Timestamp Counter Prescaler.

TSCV

FDCAN Timestamp Counter Value Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: Timestamp Counter.

TOCC

FDCAN Timeout Counter Configuration Register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw
ETOC
rw
Toggle fields

ETOC

Bit 0: Enable Timeout Counter.

TOS

Bits 1-2: Timeout Select.

TOP

Bits 16-31: Timeout Period.

TOCV

FDCAN Timeout Counter Value Register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: Timeout Counter.

ECR

FDCAN Error Counter Register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
rw
REC
r
TEC
r
Toggle fields

TEC

Bits 0-7: Transmit Error Counter.

REC

Bits 8-14: Receive Error Counter.

RP

Bit 15: Receive Error Passive.

CEL

Bits 16-23: AN Error Logging.

PSR

FDCAN Protocol Status Register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

5/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw
REDL
rw
RBRS
rw
RESI
rw
DLEC
rw
BO
r
EW
r
EP
r
ACT
r
LEC
rw
Toggle fields

LEC

Bits 0-2: Last Error Code.

ACT

Bits 3-4: Activity.

EP

Bit 5: Error Passive.

EW

Bit 6: Warning Status.

BO

Bit 7: Bus_Off Status.

DLEC

Bits 8-10: Data Last Error Code.

RESI

Bit 11: ESI flag of last received FDCAN Message.

RBRS

Bit 12: BRS flag of last received FDCAN Message.

REDL

Bit 13: Received FDCAN Message.

PXE

Bit 14: Protocol Exception Event.

TDCV

Bits 16-22: Transmitter Delay Compensation Value.

TDCR

FDCAN Transmitter Delay Compensation Register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw
TDCF
rw
Toggle fields

TDCF

Bits 0-6: Transmitter Delay Compensation Filter Window Length.

TDCO

Bits 8-14: Transmitter Delay Compensation Offset.

IR

FDCAN Interrupt Register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw
PED
rw
PEA
rw
WDI
rw
BO
rw
EW
rw
EP
rw
ELO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOO
rw
MRAF
rw
TSW
rw
TEFL
rw
TEFF
rw
TEFN
rw
TFE
rw
TCF
rw
TC
rw
HPM
rw
RF1L
rw
RF1F
rw
RF1N
rw
RF0L
rw
RF0F
rw
RF0N
rw
Toggle fields

RF0N

Bit 0: RF0N.

RF0F

Bit 1: RF0F.

RF0L

Bit 2: RF0L.

RF1N

Bit 3: RF1N.

RF1F

Bit 4: RF1F.

RF1L

Bit 5: RF1L.

HPM

Bit 6: HPM.

TC

Bit 7: TC.

TCF

Bit 8: TCF.

TFE

Bit 9: TFE.

TEFN

Bit 10: TEFN.

TEFF

Bit 11: TEFF.

TEFL

Bit 12: TEFL.

TSW

Bit 13: TSW.

MRAF

Bit 14: MRAF.

TOO

Bit 15: TOO.

ELO

Bit 16: ELO.

EP

Bit 17: EP.

EW

Bit 18: EW.

BO

Bit 19: BO.

WDI

Bit 20: WDI.

PEA

Bit 21: PEA.

PED

Bit 22: PED.

ARA

Bit 23: ARA.

IE

FDCAN Interrupt Enable Register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw
PEDE
rw
PEAE
rw
WDIE
rw
BOE
rw
EWE
rw
EPE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELOE
rw
TOOE
rw
MRAFE
rw
TEFLE
rw
TEFFE
rw
TEFNE
rw
TEFE
rw
TCFE
rw
TCE
rw
HPME
rw
RF1LE
rw
RF1FE
rw
RF1NE
rw
RF0LE
rw
RF0FE
rw
RF0NE
rw
Toggle fields

RF0NE

Bit 0: Rx FIFO 0 New Message Enable.

RF0FE

Bit 1: Rx FIFO 0 Full Enable.

RF0LE

Bit 2: Rx FIFO 0 Message Lost Enable.

RF1NE

Bit 3: Rx FIFO 1 New Message Enable.

RF1FE

Bit 4: Rx FIFO 1 Watermark Reached Enable.

RF1LE

Bit 5: Rx FIFO 1 Message Lost Enable.

HPME

Bit 6: High Priority Message Enable.

TCE

Bit 7: Transmission Completed Enable.

TCFE

Bit 8: Transmission Cancellation Finished Enable.

TEFE

Bit 9: Tx FIFO Empty Enable.

TEFNE

Bit 10: Tx Event FIFO New Entry Enable.

TEFFE

Bit 11: Tx Event FIFO Full Enable.

TEFLE

Bit 12: Tx Event FIFO Element Lost Enable.

MRAFE

Bit 13: Message RAM Access Failure Enable.

TOOE

Bit 14: Timeout Occurred Enable.

ELOE

Bit 15: Error Logging Overflow Enable.

EPE

Bit 16: Error Passive Enable.

EWE

Bit 17: Warning Status Enable.

BOE

Bit 18: Bus_Off Status Enable.

WDIE

Bit 19: Watchdog Interrupt Enable.

PEAE

Bit 20: Protocol Error in Arbitration Phase Enable.

PEDE

Bit 21: Protocol Error in Data Phase Enable.

ARAE

Bit 22: Access to Reserved Address Enable.

ILS

FDCAN Interrupt Line Select Register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERR
rw
BERR
rw
MISC
rw
TFERR
rw
SMSG
rw
RxFIFO1
rw
RxFIFO0
rw
Toggle fields

RxFIFO0

Bit 0: RxFIFO0.

RxFIFO1

Bit 1: RxFIFO1.

SMSG

Bit 2: SMSG.

TFERR

Bit 3: TFERR.

MISC

Bit 4: MISC.

BERR

Bit 5: BERR.

PERR

Bit 6: PERR.

ILE

FDCAN Interrupt Line Enable Register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw
EINT0
rw
Toggle fields

EINT0

Bit 0: Enable Interrupt Line 0.

EINT1

Bit 1: Enable Interrupt Line 1.

RXGFC

FDCAN Global Filter Configuration Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw
LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0OM
rw
F1OM
rw
ANFS
rw
ANFE
rw
RRFS
rw
RRFE
rw
Toggle fields

RRFE

Bit 0: Reject Remote Frames Extended.

RRFS

Bit 1: Reject Remote Frames Standard.

ANFE

Bits 2-3: Accept Non-matching Frames Extended.

ANFS

Bits 4-5: Accept Non-matching Frames Standard.

F1OM

Bit 8: F1OM.

F0OM

Bit 9: F0OM.

LSS

Bits 16-20: LSS.

LSE

Bits 24-27: LSE.

XIDAM

FDCAN Extended ID and Mask Register

Offset: 0x84, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: Extended ID Mask.

HPMS

FDCAN High Priority Message Status Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r
FIDX
r
MSI
r
BIDX
r
Toggle fields

BIDX

Bits 0-2: Buffer Index.

MSI

Bits 6-7: Message Storage Indicator.

FIDX

Bits 8-12: Filter Index.

FLST

Bit 15: Filter List.

RXF0S

FDCAN Rx FIFO 0 Status Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw
F0F
rw
F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw
F0FL
rw
Toggle fields

F0FL

Bits 0-3: Rx FIFO 0 Fill Level.

F0GI

Bits 8-9: Rx FIFO 0 Get Index.

F0PI

Bits 16-17: Rx FIFO 0 Put Index.

F0F

Bit 24: Rx FIFO 0 Full.

RF0L

Bit 25: Rx FIFO 0 Message Lost.

RXF0A

CAN Rx FIFO 0 Acknowledge Register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-2: Rx FIFO 0 Acknowledge Index.

RXF1S

FDCAN Rx FIFO 1 Status Register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF1L
r
F1F
r
F1PI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
r
F1FL
rw
Toggle fields

F1FL

Bits 0-3: Rx FIFO 1 Fill Level.

F1GI

Bits 8-9: Rx FIFO 1 Get Index.

F1PI

Bits 16-17: Rx FIFO 1 Put Index.

F1F

Bit 24: Rx FIFO 1 Full.

RF1L

Bit 25: Rx FIFO 1 Message Lost.

RXF1A

FDCAN Rx FIFO 1 Acknowledge Register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-2: Rx FIFO 1 Acknowledge Index.

TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

TFQM

Bit 24: Tx FIFO/Queue Mode.

TXFQS

FDCAN Tx FIFO/Queue Status Register

Offset: 0xc4, size: 32, reset: 0x00000003, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r
TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r
TFFL
r
Toggle fields

TFFL

Bits 0-2: Tx FIFO Free Level.

TFGI

Bits 8-9: TFGI.

TFQPI

Bits 16-17: Tx FIFO/Queue Put Index.

TFQF

Bit 21: Tx FIFO/Queue Full.

TXBRP

FDCAN Tx Buffer Request Pending Register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRP
r
Toggle fields

TRP

Bits 0-2: Transmission Request Pending.

TXBAR

FDCAN Tx Buffer Add Request Register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-2: Add Request.

TXBCR

FDCAN Tx Buffer Cancellation Request Register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-2: Cancellation Request.

TXBTO

FDCAN Tx Buffer Transmission Occurred Register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
r
Toggle fields

TO

Bits 0-2: Transmission Occurred..

TXBCF

FDCAN Tx Buffer Cancellation Finished Register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-2: Cancellation Finished.

TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-2: Transmission Interrupt Enable.

TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
rw
Toggle fields

CF

Bits 0-2: Cancellation Finished Interrupt Enable.

TXEFS

FDCAN Tx Event FIFO Status Register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
r
EFF
r
EFPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
r
EFFL
r
Toggle fields

EFFL

Bits 0-2: Event FIFO Fill Level.

EFGI

Bits 8-9: Event FIFO Get Index..

EFPI

Bits 16-17: Event FIFO Put Index.

EFF

Bit 24: Event FIFO Full..

TEFL

Bit 25: Tx Event FIFO Element Lost..

TXEFA

FDCAN Tx Event FIFO Acknowledge Register

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-1: Event FIFO Acknowledge Index.

CKDIV

FDCAN TT Trigger Memory Configuration Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDIV
rw
Toggle fields

PDIV

Bits 0-3: PDIV.

SEC_FLASH

0x50022000: Flash

5/114 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ACR
0x4 PDKEYR
0x8 NSKEYR
0xc SECKEYR
0x10 OPTKEYR
0x14 LVEKEYR
0x20 NSSR
0x24 SECSR
0x28 NSCR
0x2c SECCR
0x30 ECCR
0x40 OPTR
0x44 NSBOOTADD0R
0x48 NSBOOTADD1R
0x4c SECBOOTADD0R
0x50 SECWM1R1
0x54 SECWM1R2
0x58 WRP1AR
0x5c WRP1BR
0x60 SECWM2R1
0x64 SECWM2R2
0x68 WRP2AR
0x6c WRP2BR
0x80 SECBB1R[1]
0x84 SECBB1R[2]
0x88 SECBB1R[3]
0x8c SECBB1R[4]
0xa0 SECBB2R[1]
0xa4 SECBB2R[2]
0xa8 SECBB2R[3]
0xac SECBB2R[4]
0xc0 SECHDPCR
0xc4 PRIVCFGR
Toggle registers

ACR

Access control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEN
rw
SLEEP_PD
rw
RUN_PD
rw
LATENCY
rw
Toggle fields

LATENCY

Bits 0-3: Latency.

RUN_PD

Bit 13: Flash Power-down mode during Low-power run mode.

SLEEP_PD

Bit 14: Flash Power-down mode during Low-power sleep mode.

LVEN

Bit 15: LVEN.

PDKEYR

Power down key register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR
w
Toggle fields

PDKEYR

Bits 0-31: RUN_PD in FLASH_ACR key.

NSKEYR

Flash non-secure key register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSKEYR
w
Toggle fields

NSKEYR

Bits 0-31: NSKEYR.

SECKEYR

Flash secure key register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECKEYR
w
Toggle fields

SECKEYR

Bits 0-31: SECKEYR.

OPTKEYR

Flash option key register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR
w
Toggle fields

OPTKEYR

Bits 0-31: OPTKEYR.

LVEKEYR

Flash low voltage key register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVEKEYR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEKEYR
w
Toggle fields

LVEKEYR

Bits 0-31: LVEKEYR.

NSSR

Flash status register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR
rw
OPTWERR
rw
NSPGSERR
rw
NSSIZERR
rw
NSPGAERR
rw
NSWRPERR
rw
NSPROGERR
rw
NSOPERR
rw
NSEOP
rw
Toggle fields

NSEOP

Bit 0: NSEOP.

NSOPERR

Bit 1: NSOPERR.

NSPROGERR

Bit 3: NSPROGERR.

NSWRPERR

Bit 4: NSWRPERR.

NSPGAERR

Bit 5: NSPGAERR.

NSSIZERR

Bit 6: NSSIZERR.

NSPGSERR

Bit 7: NSPGSERR.

OPTWERR

Bit 13: OPTWERR.

OPTVERR

Bit 15: OPTVERR.

NSBSY

Bit 16: NSBusy.

SECSR

Flash status register

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECRDERR
rw
SECPGSERR
rw
SECSIZERR
rw
SECPGAERR
rw
SECWRPERR
rw
SECPROGERR
rw
SECOPERR
rw
SECEOP
rw
Toggle fields

SECEOP

Bit 0: SECEOP.

SECOPERR

Bit 1: SECOPERR.

SECPROGERR

Bit 3: SECPROGERR.

SECWRPERR

Bit 4: SECWRPERR.

SECPGAERR

Bit 5: SECPGAERR.

SECSIZERR

Bit 6: SECSIZERR.

SECPGSERR

Bit 7: SECPGSERR.

SECRDERR

Bit 14: Secure read protection error.

SECBSY

Bit 16: SECBusy.

NSCR

Flash non-secure control register

Offset: 0x28, size: 32, reset: 0xC0000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSLOCK
rw
OPTLOCK
rw
OBL_LAUNCH
rw
NSERRIE
rw
NSEOPIE
rw
OPTSTRT
rw
NSSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSMER2
rw
NSBKER
rw
NSPNB
rw
NSMER1
rw
NSPER
rw
NSPG
rw
Toggle fields

NSPG

Bit 0: NSPG.

NSPER

Bit 1: NSPER.

NSMER1

Bit 2: NSMER1.

NSPNB

Bits 3-9: NSPNB.

NSBKER

Bit 11: NSBKER.

NSMER2

Bit 15: NSMER2.

NSSTRT

Bit 16: Options modification start.

OPTSTRT

Bit 17: Options modification start.

NSEOPIE

Bit 24: NSEOPIE.

NSERRIE

Bit 25: NSERRIE.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

NSLOCK

Bit 31: NSLOCK.

SECCR

Flash secure control register

Offset: 0x2c, size: 32, reset: 0x80000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECLOCK
rw
SECINV
rw
SECRDERRIE
rw
SECERRIE
rw
SECEOPIE
rw
SECSTRT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECMER2
rw
SECBKER
rw
SECPNB
rw
SECMER1
rw
SECPER
rw
SECPG
rw
Toggle fields

SECPG

Bit 0: SECPG.

SECPER

Bit 1: SECPER.

SECMER1

Bit 2: SECMER1.

SECPNB

Bits 3-9: SECPNB.

SECBKER

Bit 11: SECBKER.

SECMER2

Bit 15: SECMER2.

SECSTRT

Bit 16: SECSTRT.

SECEOPIE

Bit 24: SECEOPIE.

SECERRIE

Bit 25: SECERRIE.

SECRDERRIE

Bit 26: SECRDERRIE.

SECINV

Bit 29: SECINV.

SECLOCK

Bit 31: SECLOCK.

ECCR

Flash ECC register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

3/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCD
rw
ECCC
rw
ECCD2
rw
ECCC2
rw
ECCIE
rw
SYSF_ECC
r
BK_ECC
r
ADDR_ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC
r
Toggle fields

ADDR_ECC

Bits 0-18: ECC fail address.

BK_ECC

Bit 21: BK_ECC.

SYSF_ECC

Bit 22: SYSF_ECC.

ECCIE

Bit 24: ECC correction interrupt enable.

ECCC2

Bit 28: ECCC2.

ECCD2

Bit 29: ECCD2.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZEN
rw
PA15_PUPEN
rw
nBOOT0
rw
nSWBOOT0
rw
SRAM2_RST
rw
SRAM2_PE
rw
DBANK
rw
DB256K
rw
SWAP_BANK
rw
WWDG_SW
rw
IWDG_STDBY
rw
IWDG_STOP
rw
IWDG_SW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_SHDW
rw
nRST_STDBY
rw
nRST_STOP
rw
BOR_LEV
rw
RDP
rw
Toggle fields

RDP

Bits 0-7: Read protection level.

BOR_LEV

Bits 8-10: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRST_SHDW.

IWDG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

SWAP_BANK

Bit 20: SWAP_BANK.

DB256K

Bit 21: DB256K.

DBANK

Bit 22: DBANK.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: nSWBOOT0.

nBOOT0

Bit 27: nBOOT0.

PA15_PUPEN

Bit 28: PA15_PUPEN.

TZEN

Bit 31: TZEN.

NSBOOTADD0R

Flash non-secure boot address 0 register

Offset: 0x44, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD0
w
Toggle fields

NSBOOTADD0

Bits 7-31: NSBOOTADD0.

NSBOOTADD1R

Flash non-secure boot address 1 register

Offset: 0x48, size: 32, reset: 0x0000000F, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD1
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD1
w
Toggle fields

NSBOOTADD1

Bits 7-31: NSBOOTADD1.

SECBOOTADD0R

FFlash secure boot address 0 register

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBOOTADD0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBOOTADD0
w
BOOT_LOCK
rw
Toggle fields

BOOT_LOCK

Bit 0: BOOT_LOCK.

SECBOOTADD0

Bits 7-31: SECBOOTADD0.

SECWM1R1

Flash bank 1 secure watermak1 register

Offset: 0x50, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM1_PSTRT
rw
Toggle fields

SECWM1_PSTRT

Bits 0-6: SECWM1_PSTRT.

SECWM1_PEND

Bits 16-22: SECWM1_PEND.

SECWM1R2

Flash secure watermak1 register 2

Offset: 0x54, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP1EN
rw
HDP1_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP1EN
rw
PCROP1_PSTRT
rw
Toggle fields

PCROP1_PSTRT

Bits 0-6: PCROP1_PSTRT.

PCROP1EN

Bit 15: PCROP1EN.

HDP1_PEND

Bits 16-22: HDP1_PEND.

HDP1EN

Bit 31: HDP1EN.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x58, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1A_PSTRT
rw
Toggle fields

WRP1A_PSTRT

Bits 0-6: WRP1A_PSTRT.

WRP1A_PEND

Bits 16-22: WRP1A_PEND.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x5c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP1B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP1B_PSTRT
rw
Toggle fields

WRP1B_PSTRT

Bits 0-6: WRP1B_PSTRT.

WRP1B_PEND

Bits 16-22: WRP1B_PEND.

SECWM2R1

Flash secure watermak2 register

Offset: 0x60, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECWM2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECWM2_PSTRT
rw
Toggle fields

SECWM2_PSTRT

Bits 0-6: SECWM2_PSTRT.

SECWM2_PEND

Bits 16-22: SECWM2_PEND.

SECWM2R2

Flash secure watermak2 register2

Offset: 0x64, size: 32, reset: 0x0F000F00, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP2EN
rw
HDP2_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCROP2EN
rw
PCROP2_PSTRT
rw
Toggle fields

PCROP2_PSTRT

Bits 0-6: PCROP2_PSTRT.

PCROP2EN

Bit 15: PCROP2EN.

HDP2_PEND

Bits 16-22: HDP2_PEND.

HDP2EN

Bit 31: HDP2EN.

WRP2AR

Flash WPR2 area A address register

Offset: 0x68, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2A_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2A_PSTRT
rw
Toggle fields

WRP2A_PSTRT

Bits 0-6: WRP2A_PSTRT.

WRP2A_PEND

Bits 16-22: WRP2A_PEND.

WRP2BR

Flash WPR2 area B address register

Offset: 0x6c, size: 32, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP2B_PEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRP2B_PSTRT
rw
Toggle fields

WRP2B_PSTRT

Bits 0-6: WRP2B_PSTRT.

WRP2B_PEND

Bits 16-22: WRP2B_PEND.

SECBB1R[1]

FLASH secure block based bank 1

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[2]

FLASH secure block based bank 1

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[3]

FLASH secure block based bank 1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB1R[4]

FLASH secure block based bank 1

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1
rw
Toggle fields

SECBB1

Bits 0-31: SECBB1.

SECBB2R[1]

FLASH secure block based bank 2

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[2]

FLASH secure block based bank 2

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[3]

FLASH secure block based bank 2

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECBB2R[4]

FLASH secure block based bank 2

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2
rw
Toggle fields

SECBB2

Bits 0-31: SECBB2.

SECHDPCR

FLASH secure HDP control register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDP2_ACCDIS
rw
HDP1_ACCDIS
rw
Toggle fields

HDP1_ACCDIS

Bit 0: HDP1_ACCDIS.

HDP2_ACCDIS

Bit 1: HDP2_ACCDIS.

PRIVCFGR

Power privilege configuration register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

SEC_FMC

0x54020000: FMC

130/143 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR[1]
0x8 BCR[2]
0xc BTR[2]
0x10 BCR[3]
0x14 BTR[3]
0x18 BCR[4]
0x1c BTR[4]
0x20 PCSCNTR
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x94 ECCR
0x104 BWTR[1]
0x10c BWTR[2]
0x114 BWTR[3]
0x11c BWTR[4]
Toggle registers

BCR1

FMC_BCR1

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

16/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
WFDIS
rw
CCLKEN
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

CCLKEN

Bit 20: Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.).

Allowed values:
0: Disabled: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set
1: Enabled: The FMC_CLK is only generated during the synchronous memory access (read/write transaction)

WFDIS

Bit 21: Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register..

Allowed values:
0: Enabled: Write FIFO enabled
1: Disabled: Write FIFO disabled

NBLSET

Bits 22-23: NBLSET.

BTR[1]

SRAM/NOR-flash chip-select timing registers for bank 1

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

BCR[2]

SRAM/NOR-Flash chip-select control register 2

Offset: 0x8, size: 32, reset: 0x000030D2, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

NBLSET

Bits 22-23: NBLSET.

BTR[2]

SRAM/NOR-flash chip-select timing registers for bank 2

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

BCR[3]

SRAM/NOR-Flash chip-select control register 3

Offset: 0x10, size: 32, reset: 0x000030D2, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

NBLSET

Bits 22-23: NBLSET.

BTR[3]

SRAM/NOR-flash chip-select timing registers for bank 3

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

BCR[4]

SRAM/NOR-Flash chip-select control register 4

Offset: 0x18, size: 32, reset: 0x000030D2, access: read-write

14/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBLSET
rw
CBURSTRW
rw
CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw
EXTMOD
rw
WAITEN
rw
WREN
rw
WAITCFG
rw
WAITPOL
rw
BURSTEN
rw
FACCEN
rw
MWID
rw
MTYP
rw
MUXEN
rw
MBKEN
rw
Toggle fields

MBKEN

Bit 0: Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus..

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

MUXEN

Bit 1: Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:.

Allowed values:
0: Disabled: Address/Data non-multiplexed
1: Enabled: Address/Data multiplexed on databus

MTYP

Bits 2-3: Memory type These bits define the type of external memory attached to the corresponding memory bank:.

Allowed values:
0: SRAM: SRAM memory type
1: PSRAM: PSRAM (CRAM) memory type
2: Flash: NOR Flash/OneNAND Flash

MWID

Bits 4-5: Memory data bus width Defines the external memory device width, valid for all type of memories..

Allowed values:
0: Bits8: Memory data bus width 8 bits
1: Bits16: Memory data bus width 16 bits
2: Bits32: Memory data bus width 32 bits

FACCEN

Bit 6: Flash access enable This bit enables NOR Flash memory access operations..

Allowed values:
0: Disabled: Corresponding NOR Flash memory access is disabled
1: Enabled: Corresponding NOR Flash memory access is enabled

BURSTEN

Bit 8: Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:.

Allowed values:
0: Disabled: Burst mode disabled
1: Enabled: Burst mode enabled

WAITPOL

Bit 9: Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:.

Allowed values:
0: ActiveLow: NWAIT active low
1: ActiveHigh: NWAIT active high

WAITCFG

Bit 11: Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:.

Allowed values:
0: BeforeWaitState: NWAIT signal is active one data cycle before wait state
1: DuringWaitState: NWAIT signal is active during wait state

WREN

Bit 12: Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:.

Allowed values:
0: Disabled: Write operations disabled for the bank by the FMC
1: Enabled: Write operations enabled for the bank by the FMC

WAITEN

Bit 13: Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are taken into account
1: Enabled: NWAIT signal enabled

EXTMOD

Bit 14: Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)..

Allowed values:
0: Disabled: Values inside the FMC_BWTR are not taken into account
1: Enabled: Values inside the FMC_BWTR are taken into account

ASYNCWAIT

Bit 15: Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol..

Allowed values:
0: Disabled: Wait signal not used in asynchronous mode
1: Enabled: Wait signal used even in asynchronous mode

CPSIZE

Bits 16-18: CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved..

Allowed values:
0: NoBurstSplit: No burst split when crossing page boundary
1: Bytes128: 128 bytes CRAM page size
2: Bytes256: 256 bytes CRAM page size
3: Bytes512: 512 bytes CRAM page size
4: Bytes1024: 1024 bytes CRAM page size

CBURSTRW

Bit 19: Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register..

Allowed values:
0: Disabled: Write operations are always performed in asynchronous mode
1: Enabled: Write operations are performed in synchronous mode

NBLSET

Bits 22-23: NBLSET.

BTR[4]

SRAM/NOR-flash chip-select timing registers for bank 4

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

7/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw
ACCMOD
rw
DATLAT
rw
CLKDIV
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care..

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ....

Allowed values: 0x0-0xf

CLKDIV

Bits 20-23: Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula).

Allowed values: 0x1-0xf

DATLAT

Bits 24-27: Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles.

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

DATAHLD

Bits 30-31: DATAHLD.

PCSCNTR

PCSCNTR

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB[4]EN
rw
CNTB[3]EN
rw
CNTB[2]EN
rw
CNTB[1]EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT
rw
Toggle fields

CSCOUNT

Bits 0-15: Chip select counter.

CNTB[1]EN

Bit 16: Counter Bank 1 enable.

CNTB[2]EN

Bit 17: Counter Bank 2 enable.

CNTB[3]EN

Bit 18: Counter Bank 3 enable.

CNTB[4]EN

Bit 19: Counter Bank 4 enable.

PCR

NAND Flash control registers

Offset: 0x80, size: 32, reset: 0x00000018, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECCPS
rw
TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw
TCLR
rw
ECCEN
rw
PWID
rw
PTYP
rw
PBKEN
rw
PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:.

Allowed values:
0: Disabled: Wait feature disabled
1: Enabled: Wait feature enabled

PBKEN

Bit 2: NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus.

Allowed values:
0: Disabled: Corresponding memory bank is disabled
1: Enabled: Corresponding memory bank is enabled

PTYP

Bit 3: Memory type.

Allowed values:
1: NANDFlash: NAND Flash

PWID

Bits 4-5: Data bus width. These bits define the external memory device width..

Allowed values:
0: Bits8: External memory device width 8 bits
1: Bits16: External memory device width 16 bits

ECCEN

Bit 6: ECC computation logic enable bit.

Allowed values:
0: Disabled: ECC logic is disabled and reset
1: Enabled: ECC logic is enabled

TCLR

Bits 9-12: CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

Allowed values: 0x0-0xf

TAR

Bits 13-16: ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space..

Allowed values: 0x0-0xf

ECCPS

Bits 17-19: ECC page size. These bits define the page size for the extended ECC:.

Allowed values:
0: Bytes256: ECC page size 256 bytes
1: Bytes512: ECC page size 512 bytes
2: Bytes1024: ECC page size 1024 bytes
3: Bytes2048: ECC page size 2048 bytes
4: Bytes4096: ECC page size 4096 bytes
5: Bytes8192: ECC page size 8192 bytes

SR

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Offset: 0x84, size: 32, reset: 0x00000040, access: Unspecified

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEMPT
r
IFEN
rw
ILEN
rw
IREN
rw
IFS
rw
ILS
rw
IRS
rw
Toggle fields

IRS

Bit 0: Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

Allowed values:
0: DidNotOccur: Interrupt rising edge did not occur
1: Occurred: Interrupt rising edge occurred

ILS

Bit 1: Interrupt high-level status The flag is set by hardware and reset by software..

Allowed values:
0: DidNotOccur: Interrupt high-level did not occur
1: Occurred: Interrupt high-level occurred

IFS

Bit 2: Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set..

Allowed values:
0: DidNotOccur: Interrupt falling edge did not occur
1: Occurred: Interrupt falling edge occurred

IREN

Bit 3: Interrupt rising edge detection enable bit.

Allowed values:
0: Disabled: Interrupt rising edge detection request disabled
1: Enabled: Interrupt rising edge detection request enabled

ILEN

Bit 4: Interrupt high-level detection enable bit.

Allowed values:
0: Disabled: Interrupt high-level detection request disabled
1: Enabled: Interrupt high-level detection request enabled

IFEN

Bit 5: Interrupt falling edge detection enable bit.

Allowed values:
0: Disabled: Interrupt falling edge detection request disabled
1: Enabled: Interrupt falling edge detection request enabled

FEMPT

Bit 6: FIFO empty. Read-only bit that provides the status of the FIFO.

Allowed values:
0: NotEmpty: FIFO not empty
1: Empty: FIFO empty

PMEM

The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access.

Offset: 0x88, size: 32, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw
MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw
MEMSET
rw
Toggle fields

MEMSET

Bits 0-7: Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:.

Allowed values: 0x0-0xfe

MEMWAIT

Bits 8-15: Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

Allowed values: 0x1-0xfe

MEMHOLD

Bits 16-23: Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:.

Allowed values: 0x1-0xfe

MEMHIZ

Bits 24-31: Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:.

Allowed values: 0x0-0xfe

PATT

The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature).

Offset: 0x8c, size: 32, reset: 0xFCFCFCFC, access: read-write

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw
ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw
ATTSET
rw
Toggle fields

ATTSET

Bits 0-7: Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

Allowed values: 0x0-0xfe

ATTWAIT

Bits 8-15: Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:.

Allowed values: 0x1-0xfe

ATTHOLD

Bits 16-23: Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:.

Allowed values: 0x1-0xfe

ATTHIZ

Bits 24-31: Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:.

Allowed values: 0x0-0xfe

ECCR

This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC
r
Toggle fields

ECC

Bits 0-31: ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields..

Allowed values: 0x0-0xffffffff

BWTR[1]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x104, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[2]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x10c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[3]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x114, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

BWTR[4]

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x11c, size: 32, reset: 0x0FFFFFFF, access: read-write

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACCMOD
rw
BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw
ADDHLD
rw
ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1..

Allowed values: 0x0-0xf

ADDHLD

Bits 4-7: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration..

Allowed values: 0x1-0xf

DATAST

Bits 8-15: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:.

Allowed values: 0x1-0xff

BUSTURN

Bits 16-19: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ....

Allowed values: 0x0-0xf

ACCMOD

Bits 28-29: Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1..

Allowed values:
0: A: Access mode A
1: B: Access mode B
2: C: Access mode C
3: D: Access mode D

SEC_GPIOA

0x52020000: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xABFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x0C000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x64000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOB

0x52020400: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFEBF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000100, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOC

0x52020800: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOD

0x52020c00: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOE

0x52021000: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOF

0x52021400: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOG

0x52021800: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GPIOH

0x52021c00: General-purpose I/Os

193/193 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0x0000000F, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER[15]
rw
MODER[14]
rw
MODER[13]
rw
MODER[12]
rw
MODER[11]
rw
MODER[10]
rw
MODER[9]
rw
MODER[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER[7]
rw
MODER[6]
rw
MODER[5]
rw
MODER[4]
rw
MODER[3]
rw
MODER[2]
rw
MODER[1]
rw
MODER[0]
rw
Toggle fields

MODER[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

MODER[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Input: Input mode
1: Output: General purpose output mode
2: Alternate: Alternate function mode
3: Analog: Analog mode

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OT[0]

Bit 0: Port x configuration pin 0.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[1]

Bit 1: Port x configuration pin 1.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[2]

Bit 2: Port x configuration pin 2.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[3]

Bit 3: Port x configuration pin 3.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[4]

Bit 4: Port x configuration pin 4.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[5]

Bit 5: Port x configuration pin 5.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[6]

Bit 6: Port x configuration pin 6.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[7]

Bit 7: Port x configuration pin 7.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[8]

Bit 8: Port x configuration pin 8.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[9]

Bit 9: Port x configuration pin 9.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[10]

Bit 10: Port x configuration pin 10.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[11]

Bit 11: Port x configuration pin 11.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[12]

Bit 12: Port x configuration pin 12.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[13]

Bit 13: Port x configuration pin 13.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[14]

Bit 14: Port x configuration pin 14.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OT[15]

Bit 15: Port x configuration pin 15.

Allowed values:
0: PushPull: Output push-pull (reset state)
1: OpenDrain: Output open-drain

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

OSPEEDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

OSPEEDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: LowSpeed: Low speed
1: MediumSpeed: Medium speed
2: HighSpeed: High speed
3: VeryHighSpeed: Very high speed

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR[15]
rw
PUPDR[14]
rw
PUPDR[13]
rw
PUPDR[12]
rw
PUPDR[11]
rw
PUPDR[10]
rw
PUPDR[9]
rw
PUPDR[8]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR[7]
rw
PUPDR[6]
rw
PUPDR[5]
rw
PUPDR[4]
rw
PUPDR[3]
rw
PUPDR[2]
rw
PUPDR[1]
rw
PUPDR[0]
rw
Toggle fields

PUPDR[0]

Bits 0-1: Port x configuration pin 0.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[1]

Bits 2-3: Port x configuration pin 1.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[2]

Bits 4-5: Port x configuration pin 2.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[3]

Bits 6-7: Port x configuration pin 3.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[4]

Bits 8-9: Port x configuration pin 4.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[5]

Bits 10-11: Port x configuration pin 5.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[6]

Bits 12-13: Port x configuration pin 6.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[7]

Bits 14-15: Port x configuration pin 7.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[8]

Bits 16-17: Port x configuration pin 8.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[9]

Bits 18-19: Port x configuration pin 9.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[10]

Bits 20-21: Port x configuration pin 10.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[11]

Bits 22-23: Port x configuration pin 11.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[12]

Bits 24-25: Port x configuration pin 12.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[13]

Bits 26-27: Port x configuration pin 13.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[14]

Bits 28-29: Port x configuration pin 14.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

PUPDR[15]

Bits 30-31: Port x configuration pin 15.

Allowed values:
0: Floating: No pull-up, pull-down
1: PullUp: Pull-up
2: PullDown: Pull-down

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

Toggle fields

IDR[0]

Bit 0: Port input data pin 0.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[1]

Bit 1: Port input data pin 1.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[2]

Bit 2: Port input data pin 2.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[3]

Bit 3: Port input data pin 3.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[4]

Bit 4: Port input data pin 4.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[5]

Bit 5: Port input data pin 5.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[6]

Bit 6: Port input data pin 6.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[7]

Bit 7: Port input data pin 7.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[8]

Bit 8: Port input data pin 8.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[9]

Bit 9: Port input data pin 9.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[10]

Bit 10: Port input data pin 10.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[11]

Bit 11: Port input data pin 11.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[12]

Bit 12: Port input data pin 12.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[13]

Bit 13: Port input data pin 13.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[14]

Bit 14: Port input data pin 14.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

IDR[15]

Bit 15: Port input data pin 15.

Allowed values:
0: Low: Input is logic low
1: High: Input is logic high

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

ODR[0]

Bit 0: Port output data pin 0.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[1]

Bit 1: Port output data pin 1.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[2]

Bit 2: Port output data pin 2.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[3]

Bit 3: Port output data pin 3.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[4]

Bit 4: Port output data pin 4.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[5]

Bit 5: Port output data pin 5.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[6]

Bit 6: Port output data pin 6.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[7]

Bit 7: Port output data pin 7.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[8]

Bit 8: Port output data pin 8.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[9]

Bit 9: Port output data pin 9.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[10]

Bit 10: Port output data pin 10.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[11]

Bit 11: Port output data pin 11.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[12]

Bit 12: Port output data pin 12.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[13]

Bit 13: Port output data pin 13.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[14]

Bit 14: Port output data pin 14.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

ODR[15]

Bit 15: Port output data pin 15.

Allowed values:
0: Low: Set output to logic low
1: High: Set output to logic high

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

32/32 fields covered.

Toggle fields

BS[0]

Bit 0: Port x set pin 0.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[1]

Bit 1: Port x set pin 1.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[2]

Bit 2: Port x set pin 2.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[3]

Bit 3: Port x set pin 3.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[4]

Bit 4: Port x set pin 4.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[5]

Bit 5: Port x set pin 5.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[6]

Bit 6: Port x set pin 6.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[7]

Bit 7: Port x set pin 7.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[8]

Bit 8: Port x set pin 8.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[9]

Bit 9: Port x set pin 9.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[10]

Bit 10: Port x set pin 10.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[11]

Bit 11: Port x set pin 11.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[12]

Bit 12: Port x set pin 12.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[13]

Bit 13: Port x set pin 13.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[14]

Bit 14: Port x set pin 14.

Allowed values:
1: Set: Sets the corresponding ODx bit

BS[15]

Bit 15: Port x set pin 15.

Allowed values:
1: Set: Sets the corresponding ODx bit

BR[0]

Bit 16: Port x reset pin 0.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[1]

Bit 17: Port x reset pin 1.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[2]

Bit 18: Port x reset pin 2.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[3]

Bit 19: Port x reset pin 3.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[4]

Bit 20: Port x reset pin 4.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[5]

Bit 21: Port x reset pin 5.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[6]

Bit 22: Port x reset pin 6.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[7]

Bit 23: Port x reset pin 7.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[8]

Bit 24: Port x reset pin 8.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[9]

Bit 25: Port x reset pin 9.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[10]

Bit 26: Port x reset pin 10.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[11]

Bit 27: Port x reset pin 11.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[12]

Bit 28: Port x reset pin 12.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[13]

Bit 29: Port x reset pin 13.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[14]

Bit 30: Port x reset pin 14.

Allowed values:
1: Reset: Resets the corresponding ODx bit

BR[15]

Bit 31: Port x reset pin 15.

Allowed values:
1: Reset: Resets the corresponding ODx bit

LCKR

GPIO port configuration lock register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK[15]
rw
LCK[14]
rw
LCK[13]
rw
LCK[12]
rw
LCK[11]
rw
LCK[10]
rw
LCK[9]
rw
LCK[8]
rw
LCK[7]
rw
LCK[6]
rw
LCK[5]
rw
LCK[4]
rw
LCK[3]
rw
LCK[2]
rw
LCK[1]
rw
LCK[0]
rw
Toggle fields

LCK[0]

Bit 0: Port x lock pin 0.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[1]

Bit 1: Port x lock pin 1.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[2]

Bit 2: Port x lock pin 2.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[3]

Bit 3: Port x lock pin 3.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[4]

Bit 4: Port x lock pin 4.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[5]

Bit 5: Port x lock pin 5.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[6]

Bit 6: Port x lock pin 6.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[7]

Bit 7: Port x lock pin 7.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[8]

Bit 8: Port x lock pin 8.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[9]

Bit 9: Port x lock pin 9.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[10]

Bit 10: Port x lock pin 10.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[11]

Bit 11: Port x lock pin 11.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[12]

Bit 12: Port x lock pin 12.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[13]

Bit 13: Port x lock pin 13.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[14]

Bit 14: Port x lock pin 14.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCK[15]

Bit 15: Port x lock pin 15.

Allowed values:
0: Unlocked: Port configuration not locked
1: Locked: Port configuration locked

LCKK

Bit 16: Port x lock bit y (y= 0..15).

Allowed values:
0: NotActive: Port configuration lock key not active
1: Active: Port configuration lock key active

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL7]
rw
AFR[EL6]
rw
AFR[EL5]
rw
AFR[EL4]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL3]
rw
AFR[EL2]
rw
AFR[EL1]
rw
AFR[EL0]
rw
Toggle fields

AFR[EL0]

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL1]

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL2]

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL3]

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL4]

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL5]

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL6]

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL7]

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR[EL15]
rw
AFR[EL14]
rw
AFR[EL13]
rw
AFR[EL12]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR[EL11]
rw
AFR[EL10]
rw
AFR[EL9]
rw
AFR[EL8]
rw
Toggle fields

AFR[EL8]

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL9]

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL10]

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL11]

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL12]

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL13]

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL14]

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

AFR[EL15]

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

Allowed values:
0: AF0: AF0
1: AF1: AF1
2: AF2: AF2
3: AF3: AF3
4: AF4: AF4
5: AF5: AF5
6: AF6: AF6
7: AF7: AF7
8: AF8: AF8
9: AF9: AF9
10: AF10: AF10
11: AF11: AF11
12: AF12: AF12
13: AF13: AF13
14: AF14: AF14
15: AF15: AF15

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

BR[0]

Bit 0: Port x reset pin 0.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[1]

Bit 1: Port x reset pin 1.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[2]

Bit 2: Port x reset pin 2.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[3]

Bit 3: Port x reset pin 3.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[4]

Bit 4: Port x reset pin 4.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[5]

Bit 5: Port x reset pin 5.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[6]

Bit 6: Port x reset pin 6.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[7]

Bit 7: Port x reset pin 7.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[8]

Bit 8: Port x reset pin 8.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[9]

Bit 9: Port x reset pin 9.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[10]

Bit 10: Port x reset pin 10.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[11]

Bit 11: Port x reset pin 11.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[12]

Bit 12: Port x reset pin 12.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[13]

Bit 13: Port x reset pin 13.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[14]

Bit 14: Port x reset pin 14.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

BR[15]

Bit 15: Port x reset pin 15.

Allowed values:
0: NoAction: No action on the corresponding ODx bit
1: Reset: Reset the ODx bit

SECCFGR

GPIO secure configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

16/16 fields covered.

Toggle fields

SEC0

Bit 0: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC1

Bit 1: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC2

Bit 2: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC3

Bit 3: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC4

Bit 4: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC5

Bit 5: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC6

Bit 6: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC7

Bit 7: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC8

Bit 8: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC9

Bit 9: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC10

Bit 10: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC11

Bit 11: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC12

Bit 12: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC13

Bit 13: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC14

Bit 14: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC15

Bit 15: I/O pin of Port x secure bit enable.

Allowed values:
0: NonSecure: The I/O pin is non-secure
1: Secure: The I/O pin is secure

SEC_GTZC_MPCBB1

0x50032c00: SEC_GTZC_MPCBB1

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 LCKVTR1
0x14 LCKVTR2
0x100 VCTR[0]
0x104 VCTR[1]
0x108 VCTR[2]
0x10c VCTR[3]
0x110 VCTR[4]
0x114 VCTR[5]
0x118 VCTR[6]
0x11c VCTR[7]
0x120 VCTR[8]
0x124 VCTR[9]
0x128 VCTR[10]
0x12c VCTR[11]
0x130 VCTR[12]
0x134 VCTR[13]
0x138 VCTR[14]
0x13c VCTR[15]
0x140 VCTR[16]
0x144 VCTR[17]
0x148 VCTR[18]
0x14c VCTR[19]
0x150 VCTR[20]
0x154 VCTR[21]
0x158 VCTR[22]
0x15c VCTR[23]
0x160 VCTR[24]
0x164 VCTR[25]
0x168 VCTR[26]
0x16c VCTR[27]
0x170 VCTR[28]
0x174 VCTR[29]
0x178 VCTR[30]
0x17c VCTR[31]
0x180 VCTR[32]
0x184 VCTR[33]
0x188 VCTR[34]
0x18c VCTR[35]
0x190 VCTR[36]
0x194 VCTR[37]
0x198 VCTR[38]
0x19c VCTR[39]
0x1a0 VCTR[40]
0x1a4 VCTR[41]
0x1a8 VCTR[42]
0x1ac VCTR[43]
0x1b0 VCTR[44]
0x1b4 VCTR[45]
0x1b8 VCTR[46]
0x1bc VCTR[47]
0x1c0 VCTR[48]
0x1c4 VCTR[49]
0x1c8 VCTR[50]
0x1cc VCTR[51]
0x1d0 VCTR[52]
0x1d4 VCTR[53]
0x1d8 VCTR[54]
0x1dc VCTR[55]
0x1e0 VCTR[56]
0x1e4 VCTR[57]
0x1e8 VCTR[58]
0x1ec VCTR[59]
0x1f0 VCTR[60]
0x1f4 VCTR[61]
0x1f8 VCTR[62]
0x1fc VCTR[63]
Toggle registers

CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw
INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

VCTR[0]

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[1]

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[2]

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[3]

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[4]

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[5]

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[6]

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[7]

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[8]

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[9]

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[10]

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[11]

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[12]

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[13]

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[14]

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[15]

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[16]

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[17]

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[18]

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[19]

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[20]

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[21]

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[22]

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[23]

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[24]

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[25]

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[26]

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[27]

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[28]

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[29]

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[30]

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[31]

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[32]

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[33]

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[34]

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[35]

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[36]

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[37]

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[38]

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[39]

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[40]

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[41]

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[42]

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[43]

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[44]

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[45]

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[46]

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[47]

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[48]

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[49]

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[50]

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[51]

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[52]

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[53]

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[54]

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[55]

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[56]

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[57]

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[58]

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[59]

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[60]

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[61]

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[62]

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[63]

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

SEC_GTZC_MPCBB2

0x50033000: SEC_GTZC_MPCBB2

0/2115 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 LCKVTR1
0x14 LCKVTR2
0x100 VCTR[0]
0x104 VCTR[1]
0x108 VCTR[2]
0x10c VCTR[3]
0x110 VCTR[4]
0x114 VCTR[5]
0x118 VCTR[6]
0x11c VCTR[7]
0x120 VCTR[8]
0x124 VCTR[9]
0x128 VCTR[10]
0x12c VCTR[11]
0x130 VCTR[12]
0x134 VCTR[13]
0x138 VCTR[14]
0x13c VCTR[15]
0x140 VCTR[16]
0x144 VCTR[17]
0x148 VCTR[18]
0x14c VCTR[19]
0x150 VCTR[20]
0x154 VCTR[21]
0x158 VCTR[22]
0x15c VCTR[23]
0x160 VCTR[24]
0x164 VCTR[25]
0x168 VCTR[26]
0x16c VCTR[27]
0x170 VCTR[28]
0x174 VCTR[29]
0x178 VCTR[30]
0x17c VCTR[31]
0x180 VCTR[32]
0x184 VCTR[33]
0x188 VCTR[34]
0x18c VCTR[35]
0x190 VCTR[36]
0x194 VCTR[37]
0x198 VCTR[38]
0x19c VCTR[39]
0x1a0 VCTR[40]
0x1a4 VCTR[41]
0x1a8 VCTR[42]
0x1ac VCTR[43]
0x1b0 VCTR[44]
0x1b4 VCTR[45]
0x1b8 VCTR[46]
0x1bc VCTR[47]
0x1c0 VCTR[48]
0x1c4 VCTR[49]
0x1c8 VCTR[50]
0x1cc VCTR[51]
0x1d0 VCTR[52]
0x1d4 VCTR[53]
0x1d8 VCTR[54]
0x1dc VCTR[55]
0x1e0 VCTR[56]
0x1e4 VCTR[57]
0x1e8 VCTR[58]
0x1ec VCTR[59]
0x1f0 VCTR[60]
0x1f4 VCTR[61]
0x1f8 VCTR[62]
0x1fc VCTR[63]
Toggle registers

CR

MPCBB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRWILADIS
rw
INVSECSTATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

INVSECSTATE

Bit 30: INVSECSTATE.

SRWILADIS

Bit 31: SRWILADIS.

LCKVTR1

MPCBB control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB0

Bit 0: LCKSB0.

LCKSB1

Bit 1: LCKSB1.

LCKSB2

Bit 2: LCKSB2.

LCKSB3

Bit 3: LCKSB3.

LCKSB4

Bit 4: LCKSB4.

LCKSB5

Bit 5: LCKSB5.

LCKSB6

Bit 6: LCKSB6.

LCKSB7

Bit 7: LCKSB7.

LCKSB8

Bit 8: LCKSB8.

LCKSB9

Bit 9: LCKSB9.

LCKSB10

Bit 10: LCKSB10.

LCKSB11

Bit 11: LCKSB11.

LCKSB12

Bit 12: LCKSB12.

LCKSB13

Bit 13: LCKSB13.

LCKSB14

Bit 14: LCKSB14.

LCKSB15

Bit 15: LCKSB15.

LCKSB16

Bit 16: LCKSB16.

LCKSB17

Bit 17: LCKSB17.

LCKSB18

Bit 18: LCKSB18.

LCKSB19

Bit 19: LCKSB19.

LCKSB20

Bit 20: LCKSB20.

LCKSB21

Bit 21: LCKSB21.

LCKSB22

Bit 22: LCKSB22.

LCKSB23

Bit 23: LCKSB23.

LCKSB24

Bit 24: LCKSB24.

LCKSB25

Bit 25: LCKSB25.

LCKSB26

Bit 26: LCKSB26.

LCKSB27

Bit 27: LCKSB27.

LCKSB28

Bit 28: LCKSB28.

LCKSB29

Bit 29: LCKSB29.

LCKSB30

Bit 30: LCKSB30.

LCKSB31

Bit 31: LCKSB31.

LCKVTR2

MPCBB control register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

LCKSB32

Bit 0: LCKSB32.

LCKSB33

Bit 1: LCKSB33.

LCKSB34

Bit 2: LCKSB34.

LCKSB35

Bit 3: LCKSB35.

LCKSB36

Bit 4: LCKSB36.

LCKSB37

Bit 5: LCKSB37.

LCKSB38

Bit 6: LCKSB38.

LCKSB39

Bit 7: LCKSB39.

LCKSB40

Bit 8: LCKSB40.

LCKSB41

Bit 9: LCKSB41.

LCKSB42

Bit 10: LCKSB42.

LCKSB43

Bit 11: LCKSB43.

LCKSB44

Bit 12: LCKSB44.

LCKSB45

Bit 13: LCKSB45.

LCKSB46

Bit 14: LCKSB46.

LCKSB47

Bit 15: LCKSB47.

LCKSB48

Bit 16: LCKSB48.

LCKSB49

Bit 17: LCKSB49.

LCKSB50

Bit 18: LCKSB50.

LCKSB51

Bit 19: LCKSB51.

LCKSB52

Bit 20: LCKSB52.

LCKSB53

Bit 21: LCKSB53.

LCKSB54

Bit 22: LCKSB54.

LCKSB55

Bit 23: LCKSB55.

LCKSB56

Bit 24: LCKSB56.

LCKSB57

Bit 25: LCKSB57.

LCKSB58

Bit 26: LCKSB58.

LCKSB59

Bit 27: LCKSB59.

LCKSB60

Bit 28: LCKSB60.

LCKSB61

Bit 29: LCKSB61.

LCKSB62

Bit 30: LCKSB62.

LCKSB63

Bit 31: LCKSB63.

VCTR[0]

MPCBBx vector register

Offset: 0x100, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[1]

MPCBBx vector register

Offset: 0x104, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[2]

MPCBBx vector register

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[3]

MPCBBx vector register

Offset: 0x10c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[4]

MPCBBx vector register

Offset: 0x110, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[5]

MPCBBx vector register

Offset: 0x114, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[6]

MPCBBx vector register

Offset: 0x118, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[7]

MPCBBx vector register

Offset: 0x11c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[8]

MPCBBx vector register

Offset: 0x120, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[9]

MPCBBx vector register

Offset: 0x124, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[10]

MPCBBx vector register

Offset: 0x128, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[11]

MPCBBx vector register

Offset: 0x12c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[12]

MPCBBx vector register

Offset: 0x130, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[13]

MPCBBx vector register

Offset: 0x134, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[14]

MPCBBx vector register

Offset: 0x138, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[15]

MPCBBx vector register

Offset: 0x13c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[16]

MPCBBx vector register

Offset: 0x140, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[17]

MPCBBx vector register

Offset: 0x144, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[18]

MPCBBx vector register

Offset: 0x148, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[19]

MPCBBx vector register

Offset: 0x14c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[20]

MPCBBx vector register

Offset: 0x150, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[21]

MPCBBx vector register

Offset: 0x154, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[22]

MPCBBx vector register

Offset: 0x158, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[23]

MPCBBx vector register

Offset: 0x15c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[24]

MPCBBx vector register

Offset: 0x160, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[25]

MPCBBx vector register

Offset: 0x164, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[26]

MPCBBx vector register

Offset: 0x168, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[27]

MPCBBx vector register

Offset: 0x16c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[28]

MPCBBx vector register

Offset: 0x170, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[29]

MPCBBx vector register

Offset: 0x174, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[30]

MPCBBx vector register

Offset: 0x178, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[31]

MPCBBx vector register

Offset: 0x17c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[32]

MPCBBx vector register

Offset: 0x180, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[33]

MPCBBx vector register

Offset: 0x184, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[34]

MPCBBx vector register

Offset: 0x188, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[35]

MPCBBx vector register

Offset: 0x18c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[36]

MPCBBx vector register

Offset: 0x190, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[37]

MPCBBx vector register

Offset: 0x194, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[38]

MPCBBx vector register

Offset: 0x198, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[39]

MPCBBx vector register

Offset: 0x19c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[40]

MPCBBx vector register

Offset: 0x1a0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[41]

MPCBBx vector register

Offset: 0x1a4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[42]

MPCBBx vector register

Offset: 0x1a8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[43]

MPCBBx vector register

Offset: 0x1ac, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[44]

MPCBBx vector register

Offset: 0x1b0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[45]

MPCBBx vector register

Offset: 0x1b4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[46]

MPCBBx vector register

Offset: 0x1b8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[47]

MPCBBx vector register

Offset: 0x1bc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[48]

MPCBBx vector register

Offset: 0x1c0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[49]

MPCBBx vector register

Offset: 0x1c4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[50]

MPCBBx vector register

Offset: 0x1c8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[51]

MPCBBx vector register

Offset: 0x1cc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[52]

MPCBBx vector register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[53]

MPCBBx vector register

Offset: 0x1d4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[54]

MPCBBx vector register

Offset: 0x1d8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[55]

MPCBBx vector register

Offset: 0x1dc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[56]

MPCBBx vector register

Offset: 0x1e0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[57]

MPCBBx vector register

Offset: 0x1e4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[58]

MPCBBx vector register

Offset: 0x1e8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[59]

MPCBBx vector register

Offset: 0x1ec, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[60]

MPCBBx vector register

Offset: 0x1f0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[61]

MPCBBx vector register

Offset: 0x1f4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[62]

MPCBBx vector register

Offset: 0x1f8, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

VCTR[63]

MPCBBx vector register

Offset: 0x1fc, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B31
rw
B30
rw
B29
rw
B28
rw
B27
rw
B26
rw
B25
rw
B24
rw
B23
rw
B22
rw
B21
rw
B20
rw
B19
rw
B18
rw
B17
rw
B16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B15
rw
B14
rw
B13
rw
B12
rw
B11
rw
B10
rw
B9
rw
B8
rw
B7
rw
B6
rw
B5
rw
B4
rw
B3
rw
B2
rw
B1
rw
B0
rw
Toggle fields

B0

Bit 0: B0.

B1

Bit 1: B1.

B2

Bit 2: B2.

B3

Bit 3: B3.

B4

Bit 4: B4.

B5

Bit 5: B5.

B6

Bit 6: B6.

B7

Bit 7: B7.

B8

Bit 8: B8.

B9

Bit 9: B9.

B10

Bit 10: B10.

B11

Bit 11: B11.

B12

Bit 12: B12.

B13

Bit 13: B13.

B14

Bit 14: B14.

B15

Bit 15: B15.

B16

Bit 16: B16.

B17

Bit 17: B17.

B18

Bit 18: B18.

B19

Bit 19: B19.

B20

Bit 20: B20.

B21

Bit 21: B21.

B22

Bit 22: B22.

B23

Bit 23: B23.

B24

Bit 24: B24.

B25

Bit 25: B25.

B26

Bit 26: B26.

B27

Bit 27: B27.

B28

Bit 28: B28.

B29

Bit 29: B29.

B30

Bit 30: B30.

B31

Bit 31: B31.

SEC_GTZC_TZIC

0x50032800: GTZC_TZIC

32/210 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IER1
0x4 IER2
0x8 IER3
0x10 SR1
0x14 SR2
0x18 SR3
0x20 FCR1
0x24 FCR2
0x28 FCR3
Toggle registers

IER1

TZIC interrupt enable register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

TIM2IE

Bit 0: TIM2IE.

TIM3IE

Bit 1: TIM3IE.

TIM4IE

Bit 2: TIM4IE.

TIM5IE

Bit 3: TIM5IE.

TIM6IE

Bit 4: TIM6IE.

TIM7IE

Bit 5: TIM7IE.

WWDGIE

Bit 6: WWDGIE.

IWDGIE

Bit 7: IWDGIE.

SPI2IE

Bit 8: SPI2IE.

SPI3IE

Bit 9: SPI3IE.

USART2IE

Bit 10: USART2IE.

USART3IE

Bit 11: USART3IE.

UART4IE

Bit 12: UART4IE.

UART5IE

Bit 13: UART5IE.

I2C1IE

Bit 14: I2C1IE.

I2C2IE

Bit 15: I2C2IE.

I2C3IE

Bit 16: I2C3IE.

CRSIE

Bit 17: CRSIE.

DACIE

Bit 18: DACIE.

OPAMPIE

Bit 19: OPAMPIE.

LPTIM1IE

Bit 20: LPTIM1IE.

LPUART1IE

Bit 21: LPUART1IE.

I2C4IE

Bit 22: I2C4IE.

LPTIM2IE

Bit 23: LPTIM2IE.

LPTIM3IE

Bit 24: LPTIM3IE.

FDCAN1IE

Bit 25: FDCAN1IE.

USBFSIE

Bit 26: USBFSIE.

UCPD1IE

Bit 27: UCPD1IE.

VREFBUFIE

Bit 28: VREFBUFIE.

COMPIE

Bit 29: COMPIE.

TIM1IE

Bit 30: TIM1IE.

SPI1IE

Bit 31: SPI1IE.

IER2

TZIC interrupt enable register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

Toggle fields

TIM8IE

Bit 0: TIM8IE.

USART1IE

Bit 1: USART1IE.

TIM15IE

Bit 2: TIM15IE.

TIM16IE

Bit 3: TIM16IE.

TIM17IE

Bit 4: TIM17IE.

SAI1IE

Bit 5: SAI1IE.

SAI2IE

Bit 6: SAI2IE.

DFSDM1IE

Bit 7: DFSDM1IE.

CRCIE

Bit 8: CRCIE.

TSCIE

Bit 9: TSCIE.

ICACHEIE

Bit 10: ICACHEIE.

ADCIE

Bit 11: ADCIE.

AESIE

Bit 12: AESIE.

HASHIE

Bit 13: HASHIE.

RNGIE

Bit 14: RNGIE.

PKAIE

Bit 15: PKAIE.

SDMMC1IE

Bit 16: SDMMC1IE.

FMC_REGIE

Bit 17: FMC_REGIE.

OCTOSPI1_REGIE

Bit 18: OCTOSPI1_REGIE.

RTCIE

Bit 19: RTCIE.

PWRIE

Bit 20: PWRIE.

SYSCFGIE

Bit 21: SYSCFGIE.

DMA1IE

Bit 22: DMA1IE.

DMA2IE

Bit 23: DMA2IE.

DMAMUX1IE

Bit 24: DMAMUX1IE.

RCCIE

Bit 25: RCCIE.

FLASHIE

Bit 26: FLASHIE.

FLASH_REGIE

Bit 27: FLASH_REGIE.

EXTIIE

Bit 28: EXTIIE.

OTFDEC1IE

Bit 29: OTFDEC1IE.

IER3

TZIC interrupt enable register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

Toggle fields

TZSCIE

Bit 0: TZSCIE.

TZICIE

Bit 1: TZICIE.

MPCWM1IE

Bit 2: MPCWM1IE.

MPCWM2IE

Bit 3: MPCWM2IE.

MPCBB1IE

Bit 4: MPCBB1IE.

MPCBB1_REGIE

Bit 5: MPCBB1_REGIE.

MPCBB2IE

Bit 6: MPCBB2IE.

MPCBB2_REGIE

Bit 7: MPCBB2_REGIE.

SR1

TZIC interrupt status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

Toggle fields

TIM2F

Bit 0: TIM2F.

TIM3F

Bit 1: TIM3F.

TIM4F

Bit 2: TIM4F.

TIM5F

Bit 3: TIM5F.

TIM6F

Bit 4: TIM6F.

TIM7F

Bit 5: TIM7F.

WWDGF

Bit 6: WWDGF.

IWDGF

Bit 7: IWDGF.

SPI2F

Bit 8: SPI2F.

SPI3F

Bit 9: SPI3F.

USART2F

Bit 10: USART2F.

USART3F

Bit 11: USART3F.

UART4F

Bit 12: UART4F.

UART5F

Bit 13: UART5F.

I2C1F

Bit 14: I2C1F.

I2C2F

Bit 15: I2C2F.

I2C3F

Bit 16: I2C3F.

CRSF

Bit 17: CRSF.

DACF

Bit 18: DACF.

OPAMPF

Bit 19: OPAMPF.

LPTIM1F

Bit 20: LPTIM1F.

LPUART1F

Bit 21: LPUART1F.

I2C4F

Bit 22: I2C4F.

LPTIM2F

Bit 23: LPTIM2F.

LPTIM3F

Bit 24: LPTIM3F.

FDCAN1F

Bit 25: FDCAN1F.

USBFSF

Bit 26: USBFSF.

UCPD1F

Bit 27: UCPD1F.

VREFBUFF

Bit 28: VREFBUFF.

COMPF

Bit 29: COMPF.

TIM1F

Bit 30: TIM1F.

SPI1F

Bit 31: SPI1F.

SR2

TZIC interrupt status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

Toggle fields

TIM8F

Bit 0: TIM8F.

USART1F

Bit 1: USART1F.

TIM15F

Bit 2: TIM15F.

TIM16F

Bit 3: TIM16F.

TIM17F

Bit 4: TIM17F.

SAI1F

Bit 5: SAI1F.

SAI2F

Bit 6: SAI2F.

DFSDM1F

Bit 7: DFSDM1F.

CRCF

Bit 8: CRCF.

TSCF

Bit 9: TSCF.

ICACHEF

Bit 10: ICACHEF.

ADCF

Bit 11: ADCF.

AESF

Bit 12: AESF.

HASHF

Bit 13: HASHF.

RNGF

Bit 14: RNGF.

PKAF

Bit 15: PKAF.

SDMMC1F

Bit 16: SDMMC1F.

FMC_REGF

Bit 17: FMC_REGF.

OCTOSPI1_REGF

Bit 18: OCTOSPI1_REGF.

RTCF

Bit 19: RTCF.

PWRF

Bit 20: PWRF.

SYSCFGF

Bit 21: SYSCFGF.

DMA1F

Bit 22: DMA1F.

DMA2F

Bit 23: DMA2F.

DMAMUX1F

Bit 24: DMAMUX1F.

RCCF

Bit 25: RCCF.

FLASHF

Bit 26: FLASHF.

FLASH_REGF

Bit 27: FLASH_REGF.

EXTIF

Bit 28: EXTIF.

OTFDEC1F

Bit 29: OTFDEC1F.

SR3

TZIC interrupt status register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPCBB2_REGF
rw
MPCBB2F
rw
MPCBB1_REGF
rw
MPCBB1F
rw
MPCWM2F
rw
MPCWM1F
rw
TZICF
rw
TZSCF
rw
Toggle fields

TZSCF

Bit 0: TZSCF.

TZICF

Bit 1: TZICF.

MPCWM1F

Bit 2: MPCWM1F.

MPCWM2F

Bit 3: MPCWM2F.

MPCBB1F

Bit 4: MPCBB1F.

MPCBB1_REGF

Bit 5: MPCBB1_REGF.

MPCBB2F

Bit 6: MPCBB2F.

MPCBB2_REGF

Bit 7: MPCBB2_REGF.

FCR1

TZIC interrupt clear register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

Toggle fields

TIM2FC

Bit 0: TIM2FC.

TIM3FC

Bit 1: TIM3FC.

TIM4FC

Bit 2: TIM4FC.

TIM5FC

Bit 3: TIM5FC.

TIM6FC

Bit 4: TIM6FC.

TIM7FC

Bit 5: TIM7FC.

WWDGFC

Bit 6: WWDGFC.

IWDGFC

Bit 7: IWDGFC.

SPI2FC

Bit 8: SPI2FC.

SPI3FC

Bit 9: SPI3FC.

USART2FC

Bit 10: USART2FC.

USART3FC

Bit 11: USART3FC.

UART4FC

Bit 12: UART4FC.

UART5FC

Bit 13: UART5FC.

I2C1FC

Bit 14: I2C1FC.

I2C2FC

Bit 15: I2C2FC.

I2C3FC

Bit 16: I2C3FC.

CRSFC

Bit 17: CRSFC.

DACFC

Bit 18: DACFC.

OPAMPFC

Bit 19: OPAMPFC.

LPTIM1FC

Bit 20: LPTIM1FC.

LPUART1FC

Bit 21: LPUART1FC.

I2C4FC

Bit 22: I2C4FC.

LPTIM2FC

Bit 23: LPTIM2FC.

LPTIM3FC

Bit 24: LPTIM3FC.

FDCAN1FC

Bit 25: FDCAN1FC.

USBFSFC

Bit 26: USBFSFC.

UCPD1FC

Bit 27: UCPD1FC.

VREFBUFFC

Bit 28: VREFBUFFC.

COMPFC

Bit 29: COMPFC.

TIM1FC

Bit 30: TIM1FC.

SPI1FC

Bit 31: SPI1FC.

FCR2

TZIC interrupt clear register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

Toggle fields

TIM8FC

Bit 0: TIM8FC.

USART1FC

Bit 1: USART1FC.

TIM15FC

Bit 2: TIM15FC.

TIM16FC

Bit 3: TIM16FC.

TIM17FC

Bit 4: TIM17FC.

SAI1FC

Bit 5: SAI1FC.

SAI2FC

Bit 6: SAI2FC.

DFSDM1FC

Bit 7: DFSDM1FC.

CRCFC

Bit 8: CRCFC.

TSCFC

Bit 9: TSCFC.

ICACHEFC

Bit 10: ICACHEFC.

ADCFC

Bit 11: ADCFC.

AESFC

Bit 12: AESFC.

HASHFC

Bit 13: HASHFC.

RNGFC

Bit 14: RNGFC.

PKAFC

Bit 15: PKAFC.

SDMMC1FC

Bit 16: SDMMC1FC.

FMC_REGFC

Bit 17: FMC_REGFC.

OCTOSPI1_REGFC

Bit 18: OCTOSPI1_REGFC.

RTCFC

Bit 19: RTCFC.

PWRFC

Bit 20: PWRFC.

SYSCFGFC

Bit 21: SYSCFGFC.

DMA1FC

Bit 22: DMA1FC.

DMA2FC

Bit 23: DMA2FC.

DMAMUX1FC

Bit 24: DMAMUX1FC.

RCCFC

Bit 25: RCCFC.

FLASHFC

Bit 26: FLASHFC.

FLASH_REGFC

Bit 27: FLASH_REGFC.

EXTIFC

Bit 28: EXTIFC.

OTFDEC1FC

Bit 29: OTFDEC1FC.

FCR3

TZIC interrupt clear register 3

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

Toggle fields

TZSCFC

Bit 0: TZSCFC.

TZICFC

Bit 1: TZICFC.

MPCWM1FC

Bit 2: MPCWM1FC.

MPCWM2FC

Bit 3: MPCWM2FC.

MPCBB1FC

Bit 4: MPCBB1FC.

MPCBB1_REGFC

Bit 5: MPCBB1_REGFC.

MPCBB2FC

Bit 6: MPCBB2FC.

MPCBB2_REGFC

Bit 7: MPCBB2_REGFC.

SEC_GTZC_TZSC

0x50032400: GTZC_TZSC

0/113 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x10 SECCFGR1
0x14 SECCFGR2
0x20 PRIVCFGR1
0x24 PRIVCFGR2
0x30 MPCWM1_NSWMR1
0x34 MPCWM1_NSWMR2
0x38 MPCWM2_NSWMR1
0x3c MPCWM2_NSWMR2
0x40 MPCWM3_NSWMR1
Toggle registers

CR

TZSC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK
rw
Toggle fields

LCK

Bit 0: LCK.

SECCFGR1

TZSC secure configuration register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

TIM2SEC

Bit 0: TIM2SEC.

TIM3SEC

Bit 1: TIM3SEC.

TIM4SEC

Bit 2: TIM4SEC.

TIM5SEC

Bit 3: TIM5SEC.

TIM6SEC

Bit 4: TIM6SEC.

TIM7SEC

Bit 5: TIM7SEC.

WWDGSEC

Bit 6: WWDGSEC.

IWDGSEC

Bit 7: IWDGSEC.

SPI2SEC

Bit 8: SPI2SEC.

SPI3SEC

Bit 9: SPI3SEC.

USART2SEC

Bit 10: USART2SEC.

USART3SEC

Bit 11: USART3SEC.

UART4SEC

Bit 12: UART4SEC.

UART5SEC

Bit 13: UART5SEC.

I2C1SEC

Bit 14: I2C1SEC.

I2C2SEC

Bit 15: I2C2SEC.

I2C3SEC

Bit 16: I2C3SEC.

CRSSEC

Bit 17: CRSSEC.

DACSEC

Bit 18: DACSEC.

OPAMPSEC

Bit 19: OPAMPSEC.

LPTIM1SEC

Bit 20: LPTIM1SEC.

LPUART1SEC

Bit 21: LPUART1SEC.

I2C4SEC

Bit 22: I2C4SEC.

LPTIM2SEC

Bit 23: LPTIM2SEC.

LPTIM3SEC

Bit 24: LPTIM3SEC.

FDCAN1SEC

Bit 25: FDCAN1SEC.

USBFSSEC

Bit 26: USBFSSEC.

UCPD1SEC

Bit 27: UCPD1SEC.

VREFBUFSEC

Bit 28: VREFBUFSEC.

COMPSEC

Bit 29: COMPSEC.

TIM1SEC

Bit 30: TIM1SEC.

SPI1SEC

Bit 31: SPI1SEC.

SECCFGR2

TZSC secure configuration register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

Toggle fields

TIM8SEC

Bit 0: TIM8SEC.

USART1SEC

Bit 1: USART1SEC.

TIM15SEC

Bit 2: TIM15SEC.

TIM16SEC

Bit 3: TIM16SEC.

TIM17SEC

Bit 4: TIM17SEC.

SAI1SEC

Bit 5: SAI1SEC.

SAI2SEC

Bit 6: SAI2SEC.

DFSDM1SEC

Bit 7: DFSDM1SEC.

CRCSEC

Bit 8: CRCSEC.

TSCSEC

Bit 9: TSCSEC.

ICACHESEC

Bit 10: ICACHESEC.

ADCSEC

Bit 11: ADCSEC.

AESSEC

Bit 12: AESSEC.

HASHSEC

Bit 13: HASHSEC.

RNGSEC

Bit 14: RNGSEC.

PKASEC

Bit 15: PKASEC.

SDMMC1SEC

Bit 16: SDMMC1SEC.

FSMC_REGSEC

Bit 17: FSMC_REGSEC.

OCTOSPI1_REGSEC

Bit 18: OCTOSPI1_REGSEC.

PRIVCFGR1

TZSC privilege configuration register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

TIM2PRIV

Bit 0: TIM2PRIV.

TIM3PRIV

Bit 1: TIM3PRIV.

TIM4PRIV

Bit 2: TIM4PRIV.

TIM5PRIV

Bit 3: TIM5PRIV.

TIM6PRIV

Bit 4: TIM6PRIV.

TIM7PRIV

Bit 5: TIM7PRIV.

WWDGPRIV

Bit 6: WWDGPRIV.

IWDGPRIV

Bit 7: IWDGPRIV.

SPI2PRIV

Bit 8: SPI2PRIV.

SPI3PRIV

Bit 9: SPI3PRIV.

USART2PRIV

Bit 10: USART2PRIV.

USART3PRIV

Bit 11: USART3PRIV.

UART4PRIV

Bit 12: UART4PRIV.

UART5PRIV

Bit 13: UART5PRIV.

I2C1PRIV

Bit 14: I2C1PRIV.

I2C2PRIV

Bit 15: I2C2PRIV.

I2C3PRIV

Bit 16: I2C3PRIV.

CRSPRIV

Bit 17: CRSPRIV.

DACPRIV

Bit 18: DACPRIV.

OPAMPPRIV

Bit 19: OPAMPPRIV.

LPTIM1PRIV

Bit 20: LPTIM1PRIV.

LPUART1PRIV

Bit 21: LPUART1PRIV.

I2C4PRIV

Bit 22: I2C4PRIV.

LPTIM2PRIV

Bit 23: LPTIM2PRIV.

LPTIM3PRIV

Bit 24: LPTIM3PRIV.

FDCAN1PRIV

Bit 25: FDCAN1PRIV.

USBFSPRIV

Bit 26: USBFSPRIV.

UCPD1PRIV

Bit 27: UCPD1PRIV.

VREFBUFPRIV

Bit 28: VREFBUFPRIV.

COMPPRIV

Bit 29: COMPPRIV.

TIM1PRIV

Bit 30: TIM1PRIV.

SPI1PRIV

Bit 31: SPI1PRIV.

PRIVCFGR2

TZSC privilege configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

Toggle fields

TIM8PRIV

Bit 0: TIM8PRIV.

USART1PRIV

Bit 1: USART1PRIV.

TIM15PRIV

Bit 2: TIM15PRIV.

TIM16PRIV

Bit 3: TIM16PRIV.

TIM17PRIV

Bit 4: TIM17PRIV.

SAI1PRIV

Bit 5: SAI1PRIV.

SAI2PRIV

Bit 6: SAI2PRIV.

DFSDM1PRIV

Bit 7: DFSDM1PRIV.

CRCPRIV

Bit 8: CRCPRIV.

TSCPRIV

Bit 9: TSCPRIV.

ICACHEPRIV

Bit 10: ICACHEPRIV.

ADCPRIV

Bit 11: ADCPRIV.

AESPRIV

Bit 12: AESPRIV.

HASHPRIV

Bit 13: HASHPRIV.

RNGPRIV

Bit 14: RNGPRIV.

PKAPRIV

Bit 15: PKAPRIV.

SDMMC1PRIV

Bit 16: SDMMC1PRIV.

FSMC_REGPRIV

Bit 17: FSMC_REGPRIV.

OCTOSPI1_REGPRIV

Bit 18: OCTOSPI1_REGRIV.

MPCWM1_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM1_NSWMR2

TZSC external memory non-secure watermark register 1

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM2_NSWMR1

TZSC external memory non-secure watermark register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM1LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM1STRT
rw
Toggle fields

NSWM1STRT

Bits 0-10: NSWM1STRT.

NSWM1LGTH

Bits 16-27: NSWM1LGTH.

MPCWM2_NSWMR2

TZSC external memory non-secure watermark register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

MPCWM3_NSWMR1

TZSC external memory non-secure watermark register 2

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSWM2LGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSWM2STRT
rw
Toggle fields

NSWM2STRT

Bits 0-10: NSWM2STRT.

NSWM2LGTH

Bits 16-27: NSWM2LGTH.

SEC_HASH

0x520c0400: Hash processor

17/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HRA0
0x10 HRA1
0x14 HRA2
0x18 HRA3
0x1c HRA4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x310 HR0
0x314 HR1
0x318 HR2
0x31c HR3
0x320 HR4
0x324 HR5
0x328 HR6
0x32c HR7
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw
LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAT
rw
DINNE
r
NBW
r
ALGO0
rw
MODE
rw
DATATYPE
rw
DMAE
rw
INIT
w
Toggle fields

INIT

Bit 2: Initialize message digest calculation.

DMAE

Bit 3: DMA enable.

DATATYPE

Bits 4-5: Data type selection.

MODE

Bit 6: Mode selection.

ALGO0

Bit 7: Algorithm selection.

NBW

Bits 8-11: Number of words already pushed.

DINNE

Bit 12: DIN not empty.

MDMAT

Bit 13: Multiple DMA Transfers.

LKEY

Bit 16: Long key selection.

ALGO1

Bit 18: Algorithm selection.

DIN

data input register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: Data input.

STR

start register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
rw
NBLW
rw
Toggle fields

NBLW

Bits 0-4: Number of valid bits in the last word of the message.

DCAL

Bit 8: Digest calculation.

HRA0

HASH aliased digest register 0

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HRA1

HASH aliased digest register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HRA2

HASH aliased digest register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HRA3

HASH aliased digest register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HRA4

HASH aliased digest register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw
DINIE
rw
Toggle fields

DINIE

Bit 0: Data input interrupt enable.

DCIE

Bit 1: Digest calculation completion interrupt enable.

SR

status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
DMAS
r
DCIS
rw
DINIS
rw
Toggle fields

DINIS

Bit 0: Data input interrupt status.

DCIS

Bit 1: Digest calculation completion interrupt status.

DMAS

Bit 2: DMA Status.

BUSY

Bit 3: Busy bit.

CSR0

context swap registers

Offset: 0xf8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR0
rw
Toggle fields

CSR0

Bits 0-31: CSR0.

CSR1

context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR1
rw
Toggle fields

CSR1

Bits 0-31: CSR1.

CSR2

context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR2
rw
Toggle fields

CSR2

Bits 0-31: CSR2.

CSR3

context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR3
rw
Toggle fields

CSR3

Bits 0-31: CSR3.

CSR4

context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR4
rw
Toggle fields

CSR4

Bits 0-31: CSR4.

CSR5

context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR5
rw
Toggle fields

CSR5

Bits 0-31: CSR5.

CSR6

context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR6
rw
Toggle fields

CSR6

Bits 0-31: CSR6.

CSR7

context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR7
rw
Toggle fields

CSR7

Bits 0-31: CSR7.

CSR8

context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR8
rw
Toggle fields

CSR8

Bits 0-31: CSR8.

CSR9

context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR9
rw
Toggle fields

CSR9

Bits 0-31: CSR9.

CSR10

context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR10
rw
Toggle fields

CSR10

Bits 0-31: CSR10.

CSR11

context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR11
rw
Toggle fields

CSR11

Bits 0-31: CSR11.

CSR12

context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR12
rw
Toggle fields

CSR12

Bits 0-31: CSR12.

CSR13

context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR13
rw
Toggle fields

CSR13

Bits 0-31: CSR13.

CSR14

context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR14
rw
Toggle fields

CSR14

Bits 0-31: CSR14.

CSR15

context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR15
rw
Toggle fields

CSR15

Bits 0-31: CSR15.

CSR16

context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR16
rw
Toggle fields

CSR16

Bits 0-31: CSR16.

CSR17

context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR17
rw
Toggle fields

CSR17

Bits 0-31: CSR17.

CSR18

context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR18
rw
Toggle fields

CSR18

Bits 0-31: CSR18.

CSR19

context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR19
rw
Toggle fields

CSR19

Bits 0-31: CSR19.

CSR20

context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR20
rw
Toggle fields

CSR20

Bits 0-31: CSR20.

CSR21

context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR21
rw
Toggle fields

CSR21

Bits 0-31: CSR21.

CSR22

context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR22
rw
Toggle fields

CSR22

Bits 0-31: CSR22.

CSR23

context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR23
rw
Toggle fields

CSR23

Bits 0-31: CSR23.

CSR24

context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR24
rw
Toggle fields

CSR24

Bits 0-31: CSR24.

CSR25

context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR25
rw
Toggle fields

CSR25

Bits 0-31: CSR25.

CSR26

context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR26
rw
Toggle fields

CSR26

Bits 0-31: CSR26.

CSR27

context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR27
rw
Toggle fields

CSR27

Bits 0-31: CSR27.

CSR28

context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR28
rw
Toggle fields

CSR28

Bits 0-31: CSR28.

CSR29

context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR29
rw
Toggle fields

CSR29

Bits 0-31: CSR29.

CSR30

context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR30
rw
Toggle fields

CSR30

Bits 0-31: CSR30.

CSR31

context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR31
rw
Toggle fields

CSR31

Bits 0-31: CSR31.

CSR32

context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR32
rw
Toggle fields

CSR32

Bits 0-31: CSR32.

CSR33

context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR33
rw
Toggle fields

CSR33

Bits 0-31: CSR33.

CSR34

context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR34
rw
Toggle fields

CSR34

Bits 0-31: CSR34.

CSR35

context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR35
rw
Toggle fields

CSR35

Bits 0-31: CSR35.

CSR36

context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR36
rw
Toggle fields

CSR36

Bits 0-31: CSR36.

CSR37

context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR37
rw
Toggle fields

CSR37

Bits 0-31: CSR37.

CSR38

context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR38
rw
Toggle fields

CSR38

Bits 0-31: CSR38.

CSR39

context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR39
rw
Toggle fields

CSR39

Bits 0-31: CSR39.

CSR40

context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR40
rw
Toggle fields

CSR40

Bits 0-31: CSR40.

CSR41

context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR41
rw
Toggle fields

CSR41

Bits 0-31: CSR41.

CSR42

context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR42
rw
Toggle fields

CSR42

Bits 0-31: CSR42.

CSR43

context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR43
rw
Toggle fields

CSR43

Bits 0-31: CSR43.

CSR44

context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR44
rw
Toggle fields

CSR44

Bits 0-31: CSR44.

CSR45

context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR45
rw
Toggle fields

CSR45

Bits 0-31: CSR45.

CSR46

context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR46
rw
Toggle fields

CSR46

Bits 0-31: CSR46.

CSR47

context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR47
rw
Toggle fields

CSR47

Bits 0-31: CSR47.

CSR48

context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR48
rw
Toggle fields

CSR48

Bits 0-31: CSR48.

CSR49

context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR49
rw
Toggle fields

CSR49

Bits 0-31: CSR49.

CSR50

context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR50
rw
Toggle fields

CSR50

Bits 0-31: CSR50.

CSR51

context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR51
rw
Toggle fields

CSR51

Bits 0-31: CSR51.

CSR52

context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR52
rw
Toggle fields

CSR52

Bits 0-31: CSR52.

CSR53

context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSR53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSR53
rw
Toggle fields

CSR53

Bits 0-31: CSR53.

HR0

digest register 0

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

digest register 1

Offset: 0x314, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

digest register 4

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

digest register 3

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

digest register 4

Offset: 0x320, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

HR5

supplementary digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HR6

supplementary digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HR7

supplementary digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

SEC_I2C1

0x50005400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_I2C2

0x50005800: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_I2C3

0x50005c00: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_I2C4

0x50008400: Inter-integrated circuit

17/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw
ALERTEN
rw
SMBDEN
rw
SMBHEN
rw
GCEN
rw
WUPEN
rw
NOSTRETCH
rw
SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw
TXDMAEN
rw
ANFOFF
rw
DNF
rw
ERRIE
rw
TCIE
rw
STOPIE
rw
NACKIE
rw
ADDRIE
rw
RXIE
rw
TXIE
rw
PE
rw
Toggle fields

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw
AUTOEND
rw
RELOAD
rw
NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw
STOP
rw
START
rw
HEAD10R
rw
ADD10
rw
RD_WRN
rw
SADD
rw
Toggle fields

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw
OA1MODE
rw
OA1
rw
Toggle fields

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw
OA2MSK
rw
OA2
rw
Toggle fields

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw
SCLDEL
rw
SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw
SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw
TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw
TIDLE
rw
TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r
DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r
ALERT
r
TIMEOUT
r
PECERR
r
OVR
r
ARLO
r
BERR
r
TCR
r
TC
r
STOPF
r
NACKF
r
ADDR
r
RXNE
r
TXIS
rw
TXE
rw
Toggle fields

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: 8-bit transmit data.

SEC_ICache

0x50030400: ICache

5/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 IER
0xc FCR
0x10 HMONR
0x14 MMONR
0x20 CRR[0]
0x24 CRR[1]
0x28 CRR[2]
0x2c CRR[3]
Toggle registers

CR

ICACHE control register

Offset: 0x0, size: 32, reset: 0x00000004, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISSMRST
rw
HITMRST
rw
MISSMEN
rw
HITMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WAYSEL
rw
CACHEINV
rw
EN
rw
Toggle fields

EN

Bit 0: EN.

CACHEINV

Bit 1: CACHEINV.

WAYSEL

Bit 2: WAYSEL.

HITMEN

Bit 16: HITMEN.

MISSMEN

Bit 17: MISSMEN.

HITMRST

Bit 18: HITMRST.

MISSMRST

Bit 19: MISSMRST.

SR

ICACHE status register

Offset: 0x4, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRF
r
BSYENDF
r
BUSYF
r
Toggle fields

BUSYF

Bit 0: BUSYF.

BSYENDF

Bit 1: BSYENDF.

ERRF

Bit 2: ERRF.

IER

ICACHE interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE
rw
BSYENDIE
rw
Toggle fields

BSYENDIE

Bit 1: BSYENDIE.

ERRIE

Bit 2: ERRIE.

FCR

ICACHE flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CERRF
w
CBSYENDF
w
Toggle fields

CBSYENDF

Bit 1: CBSYENDF.

CERRF

Bit 2: CERRF.

HMONR

ICACHE hit monitor register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HITMON
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HITMON
r
Toggle fields

HITMON

Bits 0-31: HITMON.

MMONR

ICACHE miss monitor register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISSMON
r
Toggle fields

MISSMON

Bits 0-15: MISSMON.

CRR[0]

ICACHE region configuration register

Offset: 0x20, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[1]

ICACHE region configuration register

Offset: 0x24, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[2]

ICACHE region configuration register

Offset: 0x28, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

CRR[3]

ICACHE region configuration register

Offset: 0x2c, size: 32, reset: 0x00000200, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST
rw
MSTSEL
rw
REMAPADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN
rw
RSIZE
rw
BASEADDR
rw
Toggle fields

BASEADDR

Bits 0-7: BASEADDR.

RSIZE

Bits 9-11: RSIZE.

REN

Bit 15: REN.

REMAPADDR

Bits 16-26: REMAPADDR.

MSTSEL

Bit 28: MSTSEL.

HBURST

Bit 31: HBURST.

SEC_IWDG

0x50003000: Independent watchdog

3/7 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) KR
0x4 (16-bit) PR
0x8 (16-bit) RLR
0xc (16-bit) SR
0x10 (16-bit) WINR
Toggle registers

KR

Key register

Offset: 0x0, size: 16, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r
RVU
r
PVU
r
Toggle fields

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: Watchdog counter window value.

SEC_LPTIM1

0x50007c00: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r
UE
r
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw
UEIE
rw
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw
RSTARE
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw
OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

SEC_LPTIM2

0x50009400: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r
UE
r
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw
UEIE
rw
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw
RSTARE
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw
OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

SEC_LPTIM3

0x50009800: Low power timer

10/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x20 OR
0x28 RCR
Toggle registers

ISR

Interrupt and Status Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOK
r
UE
r
DOWN
r
UP
r
ARROK
r
CMPOK
r
EXTTRIG
r
ARRM
r
CMPM
r
Toggle fields

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

UE

Bit 7: LPTIM update event occurred.

REPOK

Bit 8: Repetition register update Ok.

ICR

Interrupt Clear Register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

Toggle fields

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

UECF

Bit 7: Update event clear flag.

REPOKCF

Bit 8: Repetition register update OK clear flag.

IER

Interrupt Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REPOKIE
rw
UEIE
rw
DOWNIE
rw
UPIE
rw
ARROKIE
rw
CMPOKIE
rw
EXTTRIGIE
rw
ARRMIE
rw
CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

UEIE

Bit 7: Update event interrupt enable.

REPOKIE

Bit 8: REPOKIE.

CFGR

Configuration Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw
COUNTMODE
rw
PRELOAD
rw
WAVPOL
rw
WAVE
rw
TIMOUT
rw
TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw
PRESC
rw
TRGFLT
rw
CKFLT
rw
CKPOL
rw
CKSEL
rw
Toggle fields

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNTRST
rw
RSTARE
rw
CNTSTRT
rw
SNGSTRT
rw
ENABLE
rw
Toggle fields

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

RSTARE

Bit 3: Reset after read enable.

COUNTRST

Bit 4: Counter reset.

CMP

Compare Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: Counter value.

OR

LPTIM option register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_1
rw
OR_0
rw
Toggle fields

OR_0

Bit 0: Option register bit 0.

OR_1

Bit 1: Option register bit 1.

RCR

LPTIM repetition register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition register value.

SEC_LPUART1

0x50008000: Universal synchronous asynchronous receiver transmitter

84/84 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

DEDT

Bits 16-20: DEDT.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: DEAT.

Allowed values: 0x0-0x1f

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
STOP
rw
ADDM7
rw
Toggle fields

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
2: Stop2: 2 stop bit

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

17/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
HDSEL
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-19: BRR.

Allowed values: 0x0-0xfffff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
Toggle fields

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: TXFRQ.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

21/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTS
r
CTSIF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTSCF
w1c
TCCF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: /1
1: Div2: /2
2: Div4: /4
3: Div6: /6
4: Div8: /8
5: Div10: /10
6: Div12: /12
7: Div16: /16
8: Div32: /32
9: Div64: /64
10: Div128: /128
11: Div256: /256

SEC_OCTOSPI1

0x54021000: OctoSPI

0/97 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x8 DCR1
0xc DCR2
0x10 DCR3
0x14 DCR4
0x20 SR
0x24 FCR
0x40 DLR
0x48 AR
0x50 DR
0x80 PSMKR
0x88 PSMAR
0x90 PIR
0x100 CCR
0x108 TCR
0x110 IR
0x120 ABR
0x130 LPTR
0x140 WPCCR
0x148 WPTCR
0x150 WPIR
0x160 WPABR
0x180 WCCR
0x188 WTCR
0x190 WIR
0x1a0 WABR
0x200 HLCR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMODE
rw
PMM
rw
APMS
rw
TOIE
rw
SMIE
rw
FTIE
rw
TCIE
rw
TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw
FSEL
rw
DQM
rw
TCEN
rw
DMAEN
rw
ABORT
rw
EN
rw
Toggle fields

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

DQM

Bit 6: Dual-quad mode.

FSEL

Bit 7: FLASH memory selection.

FTHRES

Bits 8-12: IFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

FMODE

Bits 28-29: Functional mode.

DCR1

device configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MTYP
rw
DEVSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw
DLYBYP
rw
FRCK
rw
CKMODE
rw
Toggle fields

CKMODE

Bit 0: Mode 0 / mode 3.

FRCK

Bit 1: Free running clock.

DLYBYP

Bit 3: Delay block bypass.

CSHT

Bits 8-10: Chip-select high time.

DEVSIZE

Bits 16-20: Device size.

MTYP

Bits 24-25: Memory type.

DCR2

device configuration register 2

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRAPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-7: Clock prescaler.

WRAPSIZE

Bits 16-18: Wrap size.

DCR3

device configuration register 3

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSBOUND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

CSBOUND

Bits 16-20: CS boundary.

DCR4

device configuration register 4

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFRESH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH
rw
Toggle fields

REFRESH

Bits 0-31: REFRESH.

SR

status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
rw
BUSY
rw
TOF
rw
SMF
rw
FTF
rw
TCF
rw
TEF
rw
Toggle fields

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-13: FIFO level.

FCR

flag clear register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w
CSMF
w
CTCF
w
CTEF
w
Toggle fields

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: Data length.

AR

address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

DR

data register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: Polling interval.

CCR

communication configuration

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIOO
rw
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: Alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

SIOO

Bit 31: Send instruction only once mode.

TCR

timing configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

IR

instruction register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

ABR

alternate bytes register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

LPTR

low-power timeout register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: Timeout period.

WPCCR

wrap communication configuration register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: Instruction mode.

IDTR

Bit 3: Instruction double transfer rate.

ISIZE

Bits 4-5: Instruction size.

ADMODE

Bits 8-10: Address mode.

ADDTR

Bit 11: Address double transfer rate.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 16-18: Alternate byte mode.

ABDTR

Bit 19: Alternate bytes double transfer rate.

ABSIZE

Bits 20-21: Alternate bytes size.

DMODE

Bits 24-26: Data mode.

DDTR

Bit 27: alternate bytes double transfer rate.

DQSE

Bit 29: DQS enable.

WPTCR

wrap timing configuration register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSHIFT
rw
DHQC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: Number of dummy cycles.

DHQC

Bit 28: Delay hold quarter cycle.

SSHIFT

Bit 30: Sample shift.

WPIR

wrap instruction register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WPABR

wrap alternate bytes register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

WCCR

WCCR

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQSE
rw
DDTR
rw
DMODE
rw
ABSIZE
rw
ABDTR
rw
ABMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSIZE
rw
ADDTR
rw
ADMODE
rw
ISIZE
rw
IDTR
rw
IMODE
rw
Toggle fields

IMODE

Bits 0-2: IMODE.

IDTR

Bit 3: IDTR.

ISIZE

Bits 4-5: ISIZE.

ADMODE

Bits 8-10: ADMODE.

ADDTR

Bit 11: ADDTR.

ADSIZE

Bits 12-13: ADSIZE.

ABMODE

Bits 16-18: ABMODE.

ABDTR

Bit 19: ABDTR.

ABSIZE

Bits 20-21: ABSIZE.

DMODE

Bits 24-26: DMODE.

DDTR

Bit 27: DDTR.

DQSE

Bit 29: DQSE.

WTCR

WTCR

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCYC
rw
Toggle fields

DCYC

Bits 0-4: DCYC.

WIR

WIR

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INSTRUCTION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-31: INSTRUCTION.

WABR

write alternate bytes register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: Alternate bytes.

HLCR

HyperBus latency configuration register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TACC
rw
WZL
rw
LM
rw
Toggle fields

LM

Bit 0: Latency mode.

WZL

Bit 1: Write zero latency.

TACC

Bits 8-15: Access time.

TRWR

Bits 16-23: Read write recovery time.

SEC_OPAMP

0x50007800: Operational amplifiers

0/29 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OPAMP1_CSR
0x4 OPAMP1_OTR
0x8 OPAMP1_LPOTR
0x10 OPAMP2_CRS
0x14 OPAMP2_OTR
0x18 OPAMP2_LPOTR
Toggle registers

OPAMP1_CSR

OPAMP1 control/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw
USERTRIM
rw
CALSEL
rw
CALON
rw
VP_SEL
rw
VM_SEL
rw
PGA_GAIN
rw
OPAMODE
rw
OPALPM
rw
OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPA_RANGE

Bit 31: Operational amplifier power supply range for stability.

OPAMP1_OTR

OPAMP1 offset trimming register in normal mode

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP1_LPOTR

OPAMP1 offset trimming register in low-powe mode

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_CRS

OPAMP2 control/status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOUT
rw
USERTRIM
rw
CALSEL
rw
CALON
rw
VP_SEL
rw
VM_SEL
rw
PGA_GAIN
rw
OPAMODE
rw
OPALPM
rw
OPAEN
rw
Toggle fields

OPAEN

Bit 0: Operational amplifier Enable.

OPALPM

Bit 1: Operational amplifier Low Power Mode.

OPAMODE

Bits 2-3: Operational amplifier PGA mode.

PGA_GAIN

Bits 4-5: Operational amplifier Programmable amplifier gain value.

VM_SEL

Bits 8-9: inverting input selection.

VP_SEL

Bit 10: non inverted input selection.

CALON

Bit 12: calibration mode enable.

CALSEL

Bit 13: calibration selection.

USERTRIM

Bit 14: User trimming enable.

CALOUT

Bit 15: Operational amplifier calibration output.

OPAMP2_OTR

OPAMP2 offset trimming register in normal mode

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMOFFSETP
rw
TRIMOFFSETN
rw
Toggle fields

TRIMOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

OPAMP2_LPOTR

OPAMP2 offset trimming register in low-power mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIMLPOFFSETP
rw
TRIMLPOFFSETN
rw
Toggle fields

TRIMLPOFFSETN

Bits 0-4: Trim for NMOS differential pairs.

TRIMLPOFFSETP

Bits 8-12: Trim for PMOS differential pairs.

SEC_OTFDEC1

0x520c5000: On-The-Fly Decryption engine

7/66 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x20 R1CFGR
0x24 R1STARTADDR
0x28 R1ENDADDR
0x2c R1NONCER0
0x30 R1NONCER1
0x34 R1KEYR0
0x38 R1KEYR1
0x3c R1KEYR2
0x40 R1KEYR3
0x50 R2CFGR
0x54 R2STARTADDR
0x58 R2ENDADDR
0x5c R2NONCER0
0x60 R2NONCER1
0x64 R2KEYR0
0x68 R2KEYR1
0x6c R2KEYR2
0x70 R2KEYR3
0x80 R3CFGR
0x84 R3STARTADDR
0x88 R3ENDADDR
0x8c R3NONCER0
0x90 R3NONCER1
0x94 R3KEYR0
0x98 R3KEYR1
0x9c R3KEYR2
0xa0 R3KEYR3
0xb0 R4CFGR
0xb4 R4STARTADDR
0xb8 R4ENDADDR
0xbc R4NONCER0
0xc0 R4NONCER1
0xc4 R4KEYR0
0xc8 R4KEYR1
0xcc R4KEYR2
0xd0 R4KEYR3
0x300 ISR
0x304 ICR
0x308 IER
Toggle registers

CR

OTFDEC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENC
rw
Toggle fields

ENC

Bit 0: Encryption mode bit.

R1CFGR

OTFDEC region x configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R1STARTADDR

OTFDEC region x start address register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R1ENDADDR

OTFDEC region x end address register

Offset: 0x28, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R1NONCER0

OTFDEC region x nonce register 0

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R1NONCER1

OTFDEC region x nonce register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce.

R1KEYR0

OTFDEC region x key register 0

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR1

OTFDEC region x key register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR2

OTFDEC region x key register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R1KEYR3

OTFDEC region x key register 3

Offset: 0x40, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2CFGR

OTFDEC region x configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R2STARTADDR

OTFDEC region x start address register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R2ENDADDR

OTFDEC region x end address register

Offset: 0x58, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R2NONCER0

OTFDEC region x nonce register 0

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R2NONCER1

OTFDEC region x nonce register 1

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: Region nonce, bits [63:32]REGx_NONCE[63:32].

R2KEYR0

OTFDEC region x key register 0

Offset: 0x64, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR1

OTFDEC region x key register 1

Offset: 0x68, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R2KEYR2

OTFDEC region x key register 2

Offset: 0x6c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY_
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY_
w
Toggle fields

REGx_KEY_

Bits 0-31: REGx_KEY.

R2KEYR3

OTFDEC region x key register 3

Offset: 0x70, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3CFGR

OTFDEC region x configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R3STARTADDR

OTFDEC region x start address register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R3ENDADDR

OTFDEC region x end address register

Offset: 0x88, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R3NONCER0

OTFDEC region x nonce register 0

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R3NONCER1

OTFDEC region x nonce register 1

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R3KEYR0

OTFDEC region x key register 0

Offset: 0x94, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR1

OTFDEC region x key register 1

Offset: 0x98, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR2

OTFDEC region x key register 2

Offset: 0x9c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R3KEYR3

OTFDEC region x key register 3

Offset: 0xa0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4CFGR

OTFDEC region x configuration register

Offset: 0xb0, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEYCRC
r
MODE
rw
KEYLOCK
rw
CONFIGLOCK
rw
REG_EN
rw
Toggle fields

REG_EN

Bit 0: region on-the-fly decryption enable.

CONFIGLOCK

Bit 1: region config lock.

KEYLOCK

Bit 2: region key lock.

MODE

Bits 4-5: operating mode.

KEYCRC

Bits 8-15: region key 8-bit CRC.

REGx_VERSION

Bits 16-31: region firmware version.

R4STARTADDR

OTFDEC region x start address register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_START_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_START_ADDR
rw
Toggle fields

REGx_START_ADDR

Bits 0-31: Region AXI start address.

R4ENDADDR

OTFDEC region x end address register

Offset: 0xb8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_END_ADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_END_ADDR
rw
Toggle fields

REGx_END_ADDR

Bits 0-31: Region AXI end address.

R4NONCER0

OTFDEC region x nonce register 0

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4NONCER1

OTFDEC region x nonce register 1

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_NONCE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_NONCE
rw
Toggle fields

REGx_NONCE

Bits 0-31: REGx_NONCE.

R4KEYR0

OTFDEC region x key register 0

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR1

OTFDEC region x key register 1

Offset: 0xc8, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR2

OTFDEC region x key register 2

Offset: 0xcc, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

R4KEYR3

OTFDEC region x key register 3

Offset: 0xd0, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGx_KEY
w
Toggle fields

REGx_KEY

Bits 0-31: REGx_KEY.

ISR

OTFDEC interrupt status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
r
XONEIF
r
SEIF
r
Toggle fields

SEIF

Bit 0: Security Error Interrupt Flag status.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag status.

KEIF

Bit 2: Key Error Interrupt Flag status.

ICR

OTFDEC interrupt clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIF
w
XONEIF
w
SEIF
w
Toggle fields

SEIF

Bit 0: SEIF.

XONEIF

Bit 1: Execute-only execute-Never Error Interrupt Flag clear.

KEIF

Bit 2: KEIF.

IER

OTFDEC interrupt enable register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEIE
rw
XONEIE
rw
SEIE
rw
Toggle fields

SEIE

Bit 0: Security Error Interrupt Enable.

XONEIE

Bit 1: XONEIE.

KEIE

Bit 2: KEIE.

SEC_PKA

0x520c2000: PKA

4/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 CLRFR
Toggle registers

CR

PKA control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRIE
rw
RAMERRIE
rw
PROCENDIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE
rw
START
rw
EN
rw
Toggle fields

EN

Bit 0: PKA Enable.

START

Bit 1: Start the operation.

MODE

Bits 8-13: PKA operation code.

PROCENDIE

Bit 17: End of operation interrupt enable.

RAMERRIE

Bit 19: RAM error interrupt enable.

ADDRERRIE

Bit 20: Address error interrupt enable.

SR

PKA status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRF
r
RAMERRF
r
PROCENDF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BUSY

Bit 16: PKA operation in progress.

PROCENDF

Bit 17: PKA end of operation flag.

RAMERRF

Bit 19: PKA ram error flag.

ADDRERRF

Bit 20: address er flag.

CLRFR

PKA clear flag register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRERRFC
w
RAMERRFC
w
PROCENDFC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PROCENDFC

Bit 17: clear PKA end of operation flag.

RAMERRFC

Bit 19: CLEAR PKA RAM ERROR FLAG.

ADDRERRFC

Bit 20: clear address error flag.

SEC_PWR

0x50007000: Power control

17/322 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc CR4
0x10 SR1
0x14 SR2
0x18 SCR
0x20 PUCRA
0x24 PDCRA
0x28 PUCRB
0x2c PDCRB
0x30 PUCRC
0x34 PDCRC
0x38 PUCRD
0x3c PDCRD
0x40 PUCRE
0x44 PDCRE
0x48 PUCRF
0x4c PDCRF
0x50 PUCRG
0x54 PDCRG
0x58 PUCRH
0x5c PDCRH
0x78 SECCFGR
0x80 PRIVCFGR
Toggle registers

CR1

Power control register 1

Offset: 0x0, size: 32, reset: 0x00000400, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR
rw
VOS
rw
DBP
rw
LPMS
rw
Toggle fields

LPMS

Bits 0-2: Low-power mode selection.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USV
rw
IOSV
rw
PVME4
rw
PVME3
rw
PVME2
rw
PVME1
rw
PLS
rw
PVDE
rw
Toggle fields

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME2

Bit 5: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

PVME4

Bit 7: Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V.

IOSV

Bit 9: VDDIO2 Independent I/Os supply valid.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCPD_DBDIS
rw
UCPD_STDBY
rw
ULPMEN
rw
APC
rw
RRS
rw
EWUP5
rw
EWUP4
rw
EWUP3
rw
EWUP2
rw
EWUP1
rw
Toggle fields

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

RRS

Bits 8-9: SRAM2 retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

ULPMEN

Bit 11: ULPMEN.

UCPD_STDBY

Bit 13: UCPD_STDBY.

UCPD_DBDIS

Bit 14: UCPD_DBDIS.

CR4

Power control register 4

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSLPEN
rw
SMPSFSTEN
rw
EXTSMPSEN
rw
SMPSBYP
rw
VBRS
rw
VBE
rw
WUPP5
rw
WUPP4
rw
WUPP3
rw
WUPP2
rw
WUPP1
rw
Toggle fields

WUPP1

Bit 0: Wakeup pin WKUP1 polarity.

WUPP2

Bit 1: Wakeup pin WKUP2 polarity.

WUPP3

Bit 2: Wakeup pin WKUP3 polarity.

WUPP4

Bit 3: Wakeup pin WKUP4 polarity.

WUPP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

SMPSBYP

Bit 12: SMPSBYP.

EXTSMPSEN

Bit 13: EXTSMPSEN.

SMPSFSTEN

Bit 14: SMPSFSTEN.

SMPSLPEN

Bit 15: SMPSLPEN.

SR1

Power status register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPSHPRDY
r
EXTSMPSRDY
r
SMPSBYPRDY
r
SBF
r
WUF5
r
WUF4
r
WUF3
r
WUF2
r
WUF1
r
Toggle fields

WUF1

Bit 0: Wakeup flag 1.

WUF2

Bit 1: Wakeup flag 2.

WUF3

Bit 2: Wakeup flag 3.

WUF4

Bit 3: Wakeup flag 4.

WUF5

Bit 4: Wakeup flag 5.

SBF

Bit 8: Standby flag.

SMPSBYPRDY

Bit 12: SMPSBYPRDY.

EXTSMPSRDY

Bit 13: EXTSMPSRDY.

SMPSHPRDY

Bit 15: SMPSHPRDY.

SR2

Power status register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO4
r
PVMO3
r
PVMO2
r
PVMO1
r
PVDO
r
VOSF
r
REGLPF
r
REGLPS
r
Toggle fields

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO2

Bit 13: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

PVMO4

Bit 15: Peripheral voltage monitoring output: VDDA vs. 2.2 V.

SCR

Power status clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSBF
w
CWUF5
w
CWUF4
w
CWUF3
w
CWUF2
w
CWUF1
w
Toggle fields

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CSBF

Bit 8: Clear standby flag.

PUCRA

Power Port A pull-up control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU14

Bit 14: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD13

Bit 13: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PD15

Bit 15: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD4

Bit 4: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PU5

Bit 5: Port E pull-up bit y (y=0..15).

PU6

Bit 6: Port E pull-up bit y (y=0..15).

PU7

Bit 7: Port E pull-up bit y (y=0..15).

PU8

Bit 8: Port E pull-up bit y (y=0..15).

PU9

Bit 9: Port E pull-up bit y (y=0..15).

PU10

Bit 10: Port E pull-up bit y (y=0..15).

PU11

Bit 11: Port E pull-up bit y (y=0..15).

PU12

Bit 12: Port E pull-up bit y (y=0..15).

PU13

Bit 13: Port E pull-up bit y (y=0..15).

PU14

Bit 14: Port E pull-up bit y (y=0..15).

PU15

Bit 15: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PD5

Bit 5: Port E pull-down bit y (y=0..15).

PD6

Bit 6: Port E pull-down bit y (y=0..15).

PD7

Bit 7: Port E pull-down bit y (y=0..15).

PD8

Bit 8: Port E pull-down bit y (y=0..15).

PD9

Bit 9: Port E pull-down bit y (y=0..15).

PD10

Bit 10: Port E pull-down bit y (y=0..15).

PD11

Bit 11: Port E pull-down bit y (y=0..15).

PD12

Bit 12: Port E pull-down bit y (y=0..15).

PD13

Bit 13: Port E pull-down bit y (y=0..15).

PD14

Bit 14: Port E pull-down bit y (y=0..15).

PD15

Bit 15: Port E pull-down bit y (y=0..15).

PUCRF

Power Port F pull-up control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port F pull-up bit y (y=0..15).

PU1

Bit 1: Port F pull-up bit y (y=0..15).

PU2

Bit 2: Port F pull-up bit y (y=0..15).

PU3

Bit 3: Port F pull-up bit y (y=0..15).

PU4

Bit 4: Port F pull-up bit y (y=0..15).

PU5

Bit 5: Port F pull-up bit y (y=0..15).

PU6

Bit 6: Port F pull-up bit y (y=0..15).

PU7

Bit 7: Port F pull-up bit y (y=0..15).

PU8

Bit 8: Port F pull-up bit y (y=0..15).

PU9

Bit 9: Port F pull-up bit y (y=0..15).

PU10

Bit 10: Port F pull-up bit y (y=0..15).

PU11

Bit 11: Port F pull-up bit y (y=0..15).

PU12

Bit 12: Port F pull-up bit y (y=0..15).

PU13

Bit 13: Port F pull-up bit y (y=0..15).

PU14

Bit 14: Port F pull-up bit y (y=0..15).

PU15

Bit 15: Port F pull-up bit y (y=0..15).

PDCRF

Power Port F pull-down control register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port F pull-down bit y (y=0..15).

PD1

Bit 1: Port F pull-down bit y (y=0..15).

PD2

Bit 2: Port F pull-down bit y (y=0..15).

PD3

Bit 3: Port F pull-down bit y (y=0..15).

PD4

Bit 4: Port F pull-down bit y (y=0..15).

PD5

Bit 5: Port F pull-down bit y (y=0..15).

PD6

Bit 6: Port F pull-down bit y (y=0..15).

PD7

Bit 7: Port F pull-down bit y (y=0..15).

PD8

Bit 8: Port F pull-down bit y (y=0..15).

PD9

Bit 9: Port F pull-down bit y (y=0..15).

PD10

Bit 10: Port F pull-down bit y (y=0..15).

PD11

Bit 11: Port F pull-down bit y (y=0..15).

PD12

Bit 12: Port F pull-down bit y (y=0..15).

PD13

Bit 13: Port F pull-down bit y (y=0..15).

PD14

Bit 14: Port F pull-down bit y (y=0..15).

PD15

Bit 15: Port F pull-down bit y (y=0..15).

PUCRG

Power Port G pull-up control register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRG

Power Port G pull-down control register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15
rw
PU14
rw
PU13
rw
PU12
rw
PU11
rw
PU10
rw
PU9
rw
PU8
rw
PU7
rw
PU6
rw
PU5
rw
PU4
rw
PU3
rw
PU2
rw
PU1
rw
PU0
rw
Toggle fields

PU0

Bit 0: Port G pull-up bit y (y=0..15).

PU1

Bit 1: Port G pull-up bit y (y=0..15).

PU2

Bit 2: Port G pull-up bit y (y=0..15).

PU3

Bit 3: Port G pull-up bit y (y=0..15).

PU4

Bit 4: Port G pull-up bit y (y=0..15).

PU5

Bit 5: Port G pull-up bit y (y=0..15).

PU6

Bit 6: Port G pull-up bit y (y=0..15).

PU7

Bit 7: Port G pull-up bit y (y=0..15).

PU8

Bit 8: Port G pull-up bit y (y=0..15).

PU9

Bit 9: Port G pull-up bit y (y=0..15).

PU10

Bit 10: Port G pull-up bit y (y=0..15).

PU11

Bit 11: Port G pull-up bit y (y=0..15).

PU12

Bit 12: Port G pull-up bit y (y=0..15).

PU13

Bit 13: Port G pull-up bit y (y=0..15).

PU14

Bit 14: Port G pull-up bit y (y=0..15).

PU15

Bit 15: Port G pull-up bit y (y=0..15).

PDCRH

Power Port H pull-down control register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15
rw
PD14
rw
PD13
rw
PD12
rw
PD11
rw
PD10
rw
PD9
rw
PD8
rw
PD7
rw
PD6
rw
PD5
rw
PD4
rw
PD3
rw
PD2
rw
PD1
rw
PD0
rw
Toggle fields

PD0

Bit 0: Port G pull-down bit y (y=0..15).

PD1

Bit 1: Port G pull-down bit y (y=0..15).

PD2

Bit 2: Port G pull-down bit y (y=0..15).

PD3

Bit 3: Port G pull-down bit y (y=0..15).

PD4

Bit 4: Port G pull-down bit y (y=0..15).

PD5

Bit 5: Port G pull-down bit y (y=0..15).

PD6

Bit 6: Port G pull-down bit y (y=0..15).

PD7

Bit 7: Port G pull-down bit y (y=0..15).

PD8

Bit 8: Port G pull-down bit y (y=0..15).

PD9

Bit 9: Port G pull-down bit y (y=0..15).

PD10

Bit 10: Port G pull-down bit y (y=0..15).

PD11

Bit 11: Port G pull-down bit y (y=0..15).

PD12

Bit 12: Port G pull-down bit y (y=0..15).

PD13

Bit 13: Port G pull-down bit y (y=0..15).

PD14

Bit 14: Port G pull-down bit y (y=0..15).

PD15

Bit 15: Port G pull-down bit y (y=0..15).

SECCFGR

Power secure configuration register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APCSEC
rw
VBSEC
rw
VDMSEC
rw
LPMSEC
rw
WUP5SEC
rw
WUP4SEC
rw
WUP3SEC
rw
WUP2SEC
rw
WUP1SEC
rw
Toggle fields

WUP1SEC

Bit 0: WKUP1 pin security.

WUP2SEC

Bit 1: WKUP2 pin security.

WUP3SEC

Bit 2: WKUP3 pin security.

WUP4SEC

Bit 3: WKUP4 pin security.

WUP5SEC

Bit 4: WKUP5 pin security.

LPMSEC

Bit 8: LPMSEC.

VDMSEC

Bit 9: VDMSEC.

VBSEC

Bit 10: VBSEC.

APCSEC

Bit 11: APCSEC.

PRIVCFGR

Power privilege configuration register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
Toggle fields

PRIV

Bit 0: PRIV.

SEC_RCC

0x50021000: Reset and clock control

245/421 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 ICSCR
0x8 CFGR
0xc PLLCFGR
0x10 PLLSAI1CFGR
0x14 PLLSAI2CFGR
0x18 CIER
0x1c CIFR
0x20 CICR
0x28 AHB1RSTR
0x2c AHB2RSTR
0x30 AHB3RSTR
0x38 APB1RSTR1
0x3c APB1RSTR2
0x40 APB2RSTR
0x48 AHB1ENR
0x4c AHB2ENR
0x50 AHB3ENR
0x58 APB1ENR1
0x5c APB1ENR2
0x60 APB2ENR
0x68 AHB1SMENR
0x6c AHB2SMENR
0x70 AHB3SMENR
0x78 APB1SMENR1
0x7c APB1SMENR2
0x80 APB2SMENR
0x88 CCIPR1
0x90 BDCR
0x94 CSR
0x98 CRRCR
0x9c CCIPR2
0xb8 SECCFGR
0xbc SECSR
0xe8 AHB1SECSR
0xec AHB2SECSR
0xf0 AHB3SECSR
0xf8 APB1SECSR1
0xfc APB1SECSR2
0x100 APB2SECSR
Toggle registers

CR

Clock control register

Offset: 0x0, size: 32, reset: 0x00000063, access: Unspecified

11/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV
rw
PLLSAI2RDY
r
PLLSAI2ON
rw
PLLSAI1RDY
r
PLLSAI1ON
rw
PLLRDY
r
PLLON
rw
CSSON
w
HSEBYP
rw
HSERDY
r
HSEON
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIASFS
rw
HSIRDY
r
HSIKERON
rw
HSION
rw
MSIRANGE
rw
MSIRGSEL
w
MSIPLLEN
rw
MSIRDY
r
MSION
rw
Toggle fields

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRGSEL

Bit 3: MSI clock range selection.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSIASFS

Bit 11: HSI automatic start from Stop.

HSEON

Bit 16: HSE clock enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

HSERDY

Bit 17: HSE clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

HSEBYP

Bit 18: HSE crystal oscillator bypass.

Allowed values:
0: NotBypassed: HSE crystal oscillator not bypassed
1: Bypassed: HSE crystal oscillator bypassed with external clock

CSSON

Bit 19: Clock security system enable.

Allowed values:
0: Off: Clock security system disabled (clock detector OFF)
1: On: Clock security system enable (clock detector ON if the HSE is ready, OFF if not)

PLLON

Bit 24: Main PLL enable.

Allowed values:
0: Off: Clock Off
1: On: Clock On

PLLRDY

Bit 25: Main PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PLLSAI2ON

Bit 28: SAI2 PLL enable.

PLLSAI2RDY

Bit 29: SAI2 PLL clock ready flag.

Allowed values:
0: NotReady: Clock not ready
1: Ready: Clock ready

PRIV

Bit 31: PRIV.

ICSCR

Internal clock sources calibration register

Offset: 0x4, size: 32, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSITRIM
rw
HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM
rw
MSICAL
r
Toggle fields

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCOPRE
r
MCOSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK
rw
PPRE2
rw
PPRE1
rw
HPRE
rw
SWS
r
SW
rw
Toggle fields

SW

Bits 0-1: System clock switch.

Allowed values:
0: MSI: MSI selected as system clock
1: HSI: HSI selected as system clock
2: HSE: HSE selected as system clock
3: PLL: PLL selected as system clock

SWS

Bits 2-3: System clock switch status.

Allowed values:
0: MSI: MSI oscillator used as system clock
1: HSI: HSI oscillator used as system clock
2: HSE: HSE used as system clock
3: PLL: PLL used as system clock

HPRE

Bits 4-7: AHB prescaler.

Allowed values:
8: Div2: SYSCLK divided by 2
9: Div4: SYSCLK divided by 4
10: Div8: SYSCLK divided by 8
11: Div16: SYSCLK divided by 16
12: Div64: SYSCLK divided by 64
13: Div128: SYSCLK divided by 128
14: Div256: SYSCLK divided by 256
15: Div512: SYSCLK divided by 512
0 (+): Div1: SYSCLK not divided

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

Allowed values:
4: Div2: HCLK divided by 2
5: Div4: HCLK divided by 4
6: Div8: HCLK divided by 8
7: Div16: HCLK divided by 16
0 (+): Div1: HCLK not divided

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

Allowed values:
0: MSI: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI: HSI oscillator selected as wakeup from stop clock and CSS backup clock

MCOSEL

Bits 24-27: Microcontroller clock output.

Allowed values:
0: None: MCO output disabled, no clock on MCO
1: SYSCLK: SYSCLK system clock selected
2: MSI: MSI clock selected
3: HSI: HSI clock selected
4: HSE: HSE clock selected
5: PLL: Main PLL clock selected
6: LSI: LSI clock selected
7: LSE: LSE clock selected
8: HSI48: Internal HSI48 clock selected

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

Allowed values:
0: Div1: MCO divided by 1
1: Div2: MCO divided by 2
2: Div4: MCO divided by 4
3: Div8: MCO divided by 8
4: Div16: MCO divided by 16

PLLCFGR

PLL configuration register

Offset: 0xc, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLPDIV
rw
PLLR
rw
PLLREN
rw
PLLQ
rw
PLLQEN
rw
PLLP
rw
PLLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLN
rw
PLLM
rw
PLLSRC
rw
Toggle fields

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-7: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLL multiplication factor for VCO.

PLLPEN

Bit 16: Main PLL PLLSAI3CLK output enable.

PLLP

Bit 17: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock).

PLLQEN

Bit 20: Main PLL PLLUSB1CLK output enable.

PLLQ

Bits 21-22: Main PLL division factor for PLLUSB1CLK(48 MHz clock).

PLLREN

Bit 24: Main PLL PLLCLK output enable.

PLLR

Bits 25-26: Main PLL division factor for PLLCLK (system clock).

PLLPDIV

Bits 27-31: Main PLL division factor for PLLSAI2CLK.

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, size: 32, reset: 0x00001000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI1PDIV
rw
PLLSAI1R
rw
PLLSAI1REN
rw
PLLSAI1Q
rw
PLLSAI1QEN
rw
PLLSAI1P
rw
PLLSAI1PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI1N
rw
PLLSAI1M
rw
PLLSAI1SRC
rw
Toggle fields

PLLSAI1SRC

Bits 0-1: PLLSAI1SRC.

PLLSAI1M

Bits 4-7: Division factor for PLLSAI1 input clock.

PLLSAI1N

Bits 8-14: SAI1PLL multiplication factor for VCO.

PLLSAI1PEN

Bit 16: SAI1PLL PLLSAI1CLK output enable.

PLLSAI1P

Bit 17: SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock).

PLLSAI1QEN

Bit 20: SAI1PLL PLLUSB2CLK output enable.

PLLSAI1Q

Bits 21-22: SAI1PLL division factor for PLLUSB2CLK (48 MHz clock).

PLLSAI1REN

Bit 24: PLLSAI1 PLLADC1CLK output enable.

PLLSAI1R

Bits 25-26: PLLSAI1 division factor for PLLADC1CLK (ADC clock).

PLLSAI1PDIV

Bits 27-31: PLLSAI1 division factor for PLLSAI1CLK.

PLLSAI2CFGR

PLLSAI2 configuration register

Offset: 0x14, size: 32, reset: 0x00001000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2PDIV
rw
PLLSAI2P
rw
PLLSAI2PEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2N
rw
PLLSAI2M
rw
PLLSAI2SRC
rw
Toggle fields

PLLSAI2SRC

Bits 0-1: PLLSAI2SRC.

PLLSAI2M

Bits 4-7: Division factor for PLLSAI2 input clock.

PLLSAI2N

Bits 8-14: SAI2PLL multiplication factor for VCO.

PLLSAI2PEN

Bit 16: SAI2PLL PLLSAI2CLK output enable.

PLLSAI2P

Bit 17: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).

PLLSAI2PDIV

Bits 27-31: PLLSAI2 division factor for PLLSAI2CLK.

CIER

Clock interrupt enable register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

Toggle fields

LSIRDYIE

Bit 0: LSI ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLL ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

PLLSAI2RDYIE

Bit 7: PLLSAI2 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

Toggle fields

LSIRDYF

Bit 0: LSI ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

PLLSAI2RDYF

Bit 7: PLLSAI2 ready interrupt flag.

CSSF

Bit 8: Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/11 fields covered.

Toggle fields

LSIRDYC

Bit 0: LSI ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

PLLSAI2RDYC

Bit 7: PLLSAI2 ready interrupt clear.

CSSC

Bit 8: Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 oscillator ready interrupt clear.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCRST
rw
TSCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCRST
rw
FLASHRST
rw
DMAMUX1RST
rw
DMA2RST
rw
DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1 reset.

Allowed values:
1: Reset: Reset the selected module

DMA2RST

Bit 1: DMA2 reset.

Allowed values:
1: Reset: Reset the selected module

DMAMUX1RST

Bit 2: DMAMUXRST.

Allowed values:
1: Reset: Reset the selected module

FLASHRST

Bit 8: Flash memory interface reset.

Allowed values:
1: Reset: Reset the selected module

CRCRST

Bit 12: CRC reset.

Allowed values:
1: Reset: Reset the selected module

TSCRST

Bit 16: Touch Sensing Controller reset.

Allowed values:
1: Reset: Reset the selected module

GTZCRST

Bit 22: GTZC reset.

Allowed values:
1: Reset: Reset the selected module

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1RST
rw
OTFDEC1RST
rw
PKARST
rw
RNGRST
rw
HASHRST
rw
AESRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCRST
rw
GPIOHRST
rw
GPIOGRST
rw
GPIOFRST
rw
GPIOERST
rw
GPIODRST
rw
GPIOCRST
rw
GPIOBRST
rw
GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: IO port A reset.

Allowed values:
1: Reset: Reset the selected module

GPIOBRST

Bit 1: IO port B reset.

Allowed values:
1: Reset: Reset the selected module

GPIOCRST

Bit 2: IO port C reset.

Allowed values:
1: Reset: Reset the selected module

GPIODRST

Bit 3: IO port D reset.

Allowed values:
1: Reset: Reset the selected module

GPIOERST

Bit 4: IO port E reset.

Allowed values:
1: Reset: Reset the selected module

GPIOFRST

Bit 5: IO port F reset.

Allowed values:
1: Reset: Reset the selected module

GPIOGRST

Bit 6: IO port G reset.

Allowed values:
1: Reset: Reset the selected module

GPIOHRST

Bit 7: IO port H reset.

Allowed values:
1: Reset: Reset the selected module

ADCRST

Bit 13: ADC reset.

Allowed values:
1: Reset: Reset the selected module

AESRST

Bit 16: AES hardware accelerator reset.

Allowed values:
1: Reset: Reset the selected module

HASHRST

Bit 17: Hash reset.

Allowed values:
1: Reset: Reset the selected module

RNGRST

Bit 18: Random number generator reset.

Allowed values:
1: Reset: Reset the selected module

PKARST

Bit 19: PKARST.

Allowed values:
1: Reset: Reset the selected module

OTFDEC1RST

Bit 21: OTFDEC1RST.

Allowed values:
1: Reset: Reset the selected module

SDMMC1RST

Bit 22: SDMMC1 reset.

Allowed values:
1: Reset: Reset the selected module

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1RST
rw
FMCRST
rw
Toggle fields

FMCRST

Bit 0: Flexible memory controller reset.

Allowed values:
1: Reset: Reset the selected module

OSPI1RST

Bit 8: OSPI1RST.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1RST
rw
OPAMPRST
rw
DAC1RST
rw
PWRRST
rw
CRSRST
rw
I2C3RST
rw
I2C2RST
rw
I2C1RST
rw
UART5RST
rw
UART4RST
rw
USART3RST
rw
USART2RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3RST
rw
SPI2RST
rw
TIM7RST
rw
TIM6RST
rw
TIM5RST
rw
TIM4RST
rw
TIM3RST
rw
TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM3RST

Bit 1: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM4RST

Bit 2: TIM3 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM5RST

Bit 3: TIM5 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM6RST

Bit 4: TIM6 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM7RST

Bit 5: TIM7 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI2RST

Bit 14: SPI2 reset.

Allowed values:
1: Reset: Reset the selected module

SPI3RST

Bit 15: SPI3 reset.

Allowed values:
1: Reset: Reset the selected module

USART2RST

Bit 17: USART2 reset.

Allowed values:
1: Reset: Reset the selected module

USART3RST

Bit 18: USART3 reset.

Allowed values:
1: Reset: Reset the selected module

UART4RST

Bit 19: UART4 reset.

Allowed values:
1: Reset: Reset the selected module

UART5RST

Bit 20: UART5 reset.

Allowed values:
1: Reset: Reset the selected module

I2C1RST

Bit 21: I2C1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C2RST

Bit 22: I2C2 reset.

Allowed values:
1: Reset: Reset the selected module

I2C3RST

Bit 23: I2C3 reset.

Allowed values:
1: Reset: Reset the selected module

CRSRST

Bit 24: CRS reset.

Allowed values:
1: Reset: Reset the selected module

PWRRST

Bit 28: Power interface reset.

Allowed values:
1: Reset: Reset the selected module

DAC1RST

Bit 29: DAC1 interface reset.

Allowed values:
1: Reset: Reset the selected module

OPAMPRST

Bit 30: OPAMP interface reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

Allowed values:
1: Reset: Reset the selected module

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1RST
rw
USBFSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1RST
rw
LPTIM3RST
rw
LPTIM2RST
rw
I2C4RST
rw
LPUART1RST
rw
Toggle fields

LPUART1RST

Bit 0: Low-power UART 1 reset.

Allowed values:
1: Reset: Reset the selected module

I2C4RST

Bit 1: I2C4 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM2RST

Bit 5: Low-power timer 2 reset.

Allowed values:
1: Reset: Reset the selected module

LPTIM3RST

Bit 6: LPTIM3RST.

Allowed values:
1: Reset: Reset the selected module

FDCAN1RST

Bit 9: FDCAN1RST.

Allowed values:
1: Reset: Reset the selected module

USBFSRST

Bit 21: USBFSRST.

Allowed values:
1: Reset: Reset the selected module

UCPD1RST

Bit 23: UCPD1RST.

Allowed values:
1: Reset: Reset the selected module

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST
rw
SAI2RST
rw
SAI1RST
rw
TIM17RST
rw
TIM16RST
rw
TIM15RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw
TIM8RST
rw
SPI1RST
rw
TIM1RST
rw
SYSCFGRST
rw
Toggle fields

SYSCFGRST

Bit 0: System configuration (SYSCFG) reset.

Allowed values:
1: Reset: Reset the selected module

TIM1RST

Bit 11: TIM1 timer reset.

Allowed values:
1: Reset: Reset the selected module

SPI1RST

Bit 12: SPI1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM8RST

Bit 13: TIM8 timer reset.

Allowed values:
1: Reset: Reset the selected module

USART1RST

Bit 14: USART1 reset.

Allowed values:
1: Reset: Reset the selected module

TIM15RST

Bit 16: TIM15 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM16RST

Bit 17: TIM16 timer reset.

Allowed values:
1: Reset: Reset the selected module

TIM17RST

Bit 18: TIM17 timer reset.

Allowed values:
1: Reset: Reset the selected module

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

Allowed values:
1: Reset: Reset the selected module

SAI2RST

Bit 22: Serial audio interface 2 (SAI2) reset.

Allowed values:
1: Reset: Reset the selected module

DFSDM1RST

Bit 24: Digital filters for sigma-delata modulators (DFSDM) reset.

Allowed values:
1: Reset: Reset the selected module

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, size: 32, reset: 0x00000100, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GTZCEN
rw
TSCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCEN
rw
FLASHEN
rw
DMAMUX1EN
rw
DMA2EN
rw
DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMA2EN

Bit 1: DMA2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DMAMUX1EN

Bit 2: DMAMUX clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FLASHEN

Bit 8: Flash memory interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRCEN

Bit 12: CRC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TSCEN

Bit 16: Touch Sensing Controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GTZCEN

Bit 22: GTZCEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1EN
rw
OTFDEC1EN
rw
PKAEN
rw
RNGEN
rw
HASHEN
rw
AESEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCEN
rw
GPIOHEN
rw
GPIOGEN
rw
GPIOFEN
rw
GPIOEEN
rw
GPIODEN
rw
GPIOCEN
rw
GPIOBEN
rw
GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: IO port A clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOBEN

Bit 1: IO port B clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOCEN

Bit 2: IO port C clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIODEN

Bit 3: IO port D clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOEEN

Bit 4: IO port E clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOFEN

Bit 5: IO port F clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOGEN

Bit 6: IO port G clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

GPIOHEN

Bit 7: IO port H clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

ADCEN

Bit 13: ADC clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AESEN

Bit 16: AES accelerator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

HASHEN

Bit 17: HASH clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RNGEN

Bit 18: Random Number Generator clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PKAEN

Bit 19: PKAEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OTFDEC1EN

Bit 21: OTFDEC1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SDMMC1EN

Bit 22: SDMMC1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1EN
rw
FMCEN
rw
Toggle fields

FMCEN

Bit 0: Flexible memory controller clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OSPI1EN

Bit 8: OSPI1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR1

APB1ENR1

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1EN
rw
OPAMPEN
rw
DAC1EN
rw
PWREN
rw
CRSEN
rw
I2C3EN
rw
I2C2EN
rw
I2C1EN
rw
UART5EN
rw
UART4EN
rw
USART3EN
rw
USART2EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SP3EN
rw
SPI2EN
rw
WWDGEN
rw
RTCAPBEN
rw
TIM7EN
rw
TIM6EN
rw
TIM5EN
rw
TIM4EN
rw
TIM3EN
rw
TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM3EN

Bit 1: TIM3 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM4EN

Bit 2: TIM4 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM5EN

Bit 3: TIM5 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM6EN

Bit 4: TIM6 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM7EN

Bit 5: TIM7 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

RTCAPBEN

Bit 10: RTC APB clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

WWDGEN

Bit 11: Window watchdog clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI2EN

Bit 14: SPI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SP3EN

Bit 15: SPI3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART2EN

Bit 17: USART2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART3EN

Bit 18: USART3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART4EN

Bit 19: UART4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UART5EN

Bit 20: UART5 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C1EN

Bit 21: I2C1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C2EN

Bit 22: I2C2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C3EN

Bit 23: I2C3 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

CRSEN

Bit 24: Clock Recovery System clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

PWREN

Bit 28: Power interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DAC1EN

Bit 29: DAC1 interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

OPAMPEN

Bit 30: OPAMP interface clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM1EN

Bit 31: Low power timer 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1EN
rw
USBFSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1EN
rw
LPTIM3EN
rw
LPTIM2EN
rw
I2C4EN
rw
LPUART1EN
rw
Toggle fields

LPUART1EN

Bit 0: Low power UART 1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

I2C4EN

Bit 1: I2C4 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM2EN

Bit 5: LPTIM2EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

LPTIM3EN

Bit 6: LPTIM3EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

FDCAN1EN

Bit 9: FDCAN1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USBFSEN

Bit 21: USBFSEN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

UCPD1EN

Bit 23: UCPD1EN.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

APB2ENR

APB2ENR

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1EN
rw
SAI2EN
rw
SAI1EN
rw
TIM17EN
rw
TIM16EN
rw
TIM15EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1EN
rw
TIM8EN
rw
SPI1EN
rw
TIM1EN
rw
SYSCFGEN
rw
Toggle fields

SYSCFGEN

Bit 0: SYSCFG clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM1EN

Bit 11: TIM1 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SPI1EN

Bit 12: SPI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM8EN

Bit 13: TIM8 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

USART1EN

Bit 14: USART1clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM15EN

Bit 16: TIM15 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM16EN

Bit 17: TIM16 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

TIM17EN

Bit 18: TIM17 timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI1EN

Bit 21: SAI1 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

SAI2EN

Bit 22: SAI2 clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

DFSDM1EN

Bit 24: DFSDM timer clock enable.

Allowed values:
0: Disabled: The selected clock is disabled
1: Enabled: The selected clock is enabled

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, size: 32, reset: 0x00C11307, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESMEN
rw
GTZCSMEN
rw
TSCSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSMEN
rw
SRAM1SMEN
rw
FLASHSMEN
rw
DMAMUX1SMEN
rw
DMA2SMEN
rw
DMA1SMEN
rw
Toggle fields

DMA1SMEN

Bit 0: DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: DMA2 clocks enable during Sleep and Stop modes.

DMAMUX1SMEN

Bit 2: DMAMUX clock enable during Sleep and Stop modes.

FLASHSMEN

Bit 8: Flash memory interface clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CRCSMEN.

TSCSMEN

Bit 16: Touch Sensing Controller clocks enable during Sleep and Stop modes.

GTZCSMEN

Bit 22: GTZCSMEN.

ICACHESMEN

Bit 23: ICACHESMEN.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6c, size: 32, reset: 0x006F22FF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SMEN
rw
OTFDEC1SMEN
rw
PKASMEN
rw
RNGSMEN
rw
HASHSMEN
rw
AESSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCFSSMEN
rw
SRAM2SMEN
rw
GPIOHSMEN
rw
GPIOGSMEN
rw
GPIOFSMEN
rw
GPIOESMEN
rw
GPIODSMEN
rw
GPIOCSMEN
rw
GPIOBSMEN
rw
GPIOASMEN
rw
Toggle fields

GPIOASMEN

Bit 0: IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: IO port E clocks enable during Sleep and Stop modes.

GPIOFSMEN

Bit 5: IO port F clocks enable during Sleep and Stop modes.

GPIOGSMEN

Bit 6: IO port G clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: IO port H clocks enable during Sleep and Stop modes.

SRAM2SMEN

Bit 9: SRAM2 interface clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: ADC clocks enable during Sleep and Stop modes.

AESSMEN

Bit 16: AES accelerator clocks enable during Sleep and Stop modes.

HASHSMEN

Bit 17: HASH clock enable during Sleep and Stop modes.

RNGSMEN

Bit 18: Random Number Generator clocks enable during Sleep and Stop modes.

PKASMEN

Bit 19: PKASMEN.

OTFDEC1SMEN

Bit 21: OTFDEC1SMEN.

SDMMC1SMEN

Bit 22: SDMMC1 clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, size: 32, reset: 0x00000101, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SMEN
rw
FMCSMEN
rw
Toggle fields

FMCSMEN

Bit 0: Flexible memory controller clocks enable during Sleep and Stop modes.

OSPI1SMEN

Bit 8: OSPI1SMEN.

APB1SMENR1

APB1SMENR1

Offset: 0x78, size: 32, reset: 0xF1FECC3F, access: read-write

0/22 fields covered.

Toggle fields

TIM2SMEN

Bit 0: TIM2 timer clocks enable during Sleep and Stop modes.

TIM3SMEN

Bit 1: TIM3 timer clocks enable during Sleep and Stop modes.

TIM4SMEN

Bit 2: TIM4 timer clocks enable during Sleep and Stop modes.

TIM5SMEN

Bit 3: TIM5 timer clocks enable during Sleep and Stop modes.

TIM6SMEN

Bit 4: TIM6 timer clocks enable during Sleep and Stop modes.

TIM7SMEN

Bit 5: TIM7 timer clocks enable during Sleep and Stop modes.

RTCAPBSMEN

Bit 10: RTC APB clock enable during Sleep and Stop modes.

WWDGSMEN

Bit 11: Window watchdog clocks enable during Sleep and Stop modes.

SPI2SMEN

Bit 14: SPI2 clocks enable during Sleep and Stop modes.

SP3SMEN

Bit 15: SPI3 clocks enable during Sleep and Stop modes.

USART2SMEN

Bit 17: USART2 clocks enable during Sleep and Stop modes.

USART3SMEN

Bit 18: USART3 clocks enable during Sleep and Stop modes.

UART4SMEN

Bit 19: UART4 clocks enable during Sleep and Stop modes.

UART5SMEN

Bit 20: UART5 clocks enable during Sleep and Stop modes.

I2C1SMEN

Bit 21: I2C1 clocks enable during Sleep and Stop modes.

I2C2SMEN

Bit 22: I2C2 clocks enable during Sleep and Stop modes.

I2C3SMEN

Bit 23: I2C3 clocks enable during Sleep and Stop modes.

CRSSMEN

Bit 24: CRS clock enable during Sleep and Stop modes.

PWRSMEN

Bit 28: Power interface clocks enable during Sleep and Stop modes.

DAC1SMEN

Bit 29: DAC1 interface clocks enable during Sleep and Stop modes.

OPAMPSMEN

Bit 30: OPAMP interface clocks enable during Sleep and Stop modes.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during Sleep and Stop modes.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7c, size: 32, reset: 0x00A00223, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SMEN
rw
USBFSSMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SMEN
rw
LPTIM3SMEN
rw
LPTIM2SMEN
rw
I2C4SMEN
rw
LPUART1SMEN
rw
Toggle fields

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during Sleep and Stop modes.

I2C4SMEN

Bit 1: I2C4 clocks enable during Sleep and Stop modes.

LPTIM2SMEN

Bit 5: LPTIM2SMEN.

LPTIM3SMEN

Bit 6: LPTIM3SMEN.

FDCAN1SMEN

Bit 9: FDCAN1SMEN.

USBFSSMEN

Bit 21: USBFSSMEN.

UCPD1SMEN

Bit 23: UCPD1SMEN.

APB2SMENR

APB2SMENR

Offset: 0x80, size: 32, reset: 0x01677801, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SMEN
rw
SAI2SMEN
rw
SAI1SMEN
rw
TIM17SMEN
rw
TIM16SMEN
rw
TIM15SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SMEN
rw
TIM8SMEN
rw
SPI1SMEN
rw
TIM1SMEN
rw
SYSCFGSMEN
rw
Toggle fields

SYSCFGSMEN

Bit 0: SYSCFG clocks enable during Sleep and Stop modes.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during Sleep and Stop modes.

SPI1SMEN

Bit 12: SPI1 clocks enable during Sleep and Stop modes.

TIM8SMEN

Bit 13: TIM8 timer clocks enable during Sleep and Stop modes.

USART1SMEN

Bit 14: USART1clocks enable during Sleep and Stop modes.

TIM15SMEN

Bit 16: TIM15 timer clocks enable during Sleep and Stop modes.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during Sleep and Stop modes.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during Sleep and Stop modes.

SAI1SMEN

Bit 21: SAI1 clocks enable during Sleep and Stop modes.

SAI2SMEN

Bit 22: SAI2 clocks enable during Sleep and Stop modes.

DFSDM1SMEN

Bit 24: DFSDM timer clocks enable during Sleep and Stop modes.

CCIPR1

CCIPR1

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCSEL
rw
CLK48MSEL
rw
FDCANSEL
rw
LPTIM3SEL
rw
LPTIM2SEL
rw
LPTIM1SEL
rw
I2C3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C2SEL
rw
I2C1SEL
rw
LPUART1SEL
rw
UART5SEL
rw
UART4SEL
rw
USART3SEL
rw
USART2SEL
rw
USART1SEL
rw
Toggle fields

USART1SEL

Bits 0-1: USART1 clock source selection.

USART2SEL

Bits 2-3: USART2 clock source selection.

USART3SEL

Bits 4-5: USART3 clock source selection.

UART4SEL

Bits 6-7: UART4 clock source selection.

UART5SEL

Bits 8-9: UART5 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C2SEL

Bits 14-15: I2C2 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

LPTIM3SEL

Bits 22-23: Low-power timer 3 clock source selection.

FDCANSEL

Bits 24-25: FDCAN clock source selection.

CLK48MSEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

BDCR

BDCR

Offset: 0x90, size: 32, reset: 0x00000000, access: Unspecified

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSCOSEL
rw
LSCOEN
rw
BDRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCEN
rw
LSESYSRDY
rw
RTCSEL
rw
LSESYSEN
rw
LSECSSD
r
LSECSSON
rw
LSEDRV
rw
LSEBYP
rw
LSERDY
r
LSEON
rw
Toggle fields

LSEON

Bit 0: LSE oscillator enable.

Allowed values:
0: Off: LSE oscillator Off
1: On: LSE oscillator On

LSERDY

Bit 1: LSE oscillator ready.

Allowed values:
0: NotReady: LSE oscillator not ready
1: Ready: LSE oscillator ready

LSEBYP

Bit 2: LSE oscillator bypass.

Allowed values:
0: NotBypassed: LSE crystal oscillator not bypassed
1: Bypassed: LSE crystal oscillator bypassed with external clock

LSEDRV

Bits 3-4: SE oscillator drive capability.

Allowed values:
0: Lower: 'Xtal mode' lower driving capability
1: MediumLow: 'Xtal mode' medium low driving capability
2: MediumHigh: 'Xtal mode' medium high driving capability
3: Higher: 'Xtal mode' higher driving capability

LSECSSON

Bit 5: LSECSSON.

Allowed values:
0: Off: CSS on LSE (32 kHz external oscillator) OFF
1: On: CSS on LSE (32 kHz external oscillator) ON

LSECSSD

Bit 6: LSECSSD.

Allowed values:
0: NoFailure: No failure detected on LSE (32 kHz oscillator)
1: Failure: Failure detected on LSE (32 kHz oscillator)

LSESYSEN

Bit 7: LSESYSEN.

Allowed values:
0: Disabled: LSESYS only enabled when requested by a peripheral or system function
1: Enabled: LSESYS enabled always generated by RCC

RTCSEL

Bits 8-9: RTC clock source selection.

Allowed values:
0: NoClock: No clock
1: LSE: LSE oscillator clock used as RTC clock
2: LSI: LSI oscillator clock used as RTC clock
3: HSE: HSE oscillator clock divided by a prescaler used as RTC clock

LSESYSRDY

Bit 11: LSESYSRDY.

Allowed values:
0: NotReady: LSESYS clock not ready
1: Ready: LSESYS clock ready

RTCEN

Bit 15: RTC clock enable.

Allowed values:
0: Disabled: RTC clock disabled
1: Enabled: RTC clock enabled

BDRST

Bit 16: Backup domain software reset.

Allowed values:
0: Disabled: Reset not activated
1: Enabled: Reset the entire RTC domain

LSCOEN

Bit 24: Low speed clock output enable.

Allowed values:
0: Disabled: LSCO disabled
1: Enabled: LSCO enabled

LSCOSEL

Bit 25: Low speed clock output selection.

Allowed values:
0: LSI: LSI clock selected"
1: LSE: LSE clock selected

CSR

CSR

Offset: 0x94, size: 32, reset: 0x0C000600, access: Unspecified

10/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWRSTF
r
WWDGRSTF
r
IWWDGRSTF
r
SFTRSTF
r
BORRSTF
r
PINRSTF
r
OBLRSTF
r
RMVF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSISRANGE
rw
LSIPREDIV
rw
LSIRDY
r
LSION
rw
Toggle fields

LSION

Bit 0: LSI oscillator enable.

Allowed values:
0: Off: LSI oscillator Off
1: On: LSI oscillator On

LSIRDY

Bit 1: LSI oscillator ready.

Allowed values:
0: NotReady: LSI oscillator not ready
1: Ready: LSI oscillator ready

LSIPREDIV

Bit 4: LSIPREDIV.

MSISRANGE

Bits 8-11: SI range after Standby mode.

RMVF

Bit 23: Remove reset flag.

Allowed values:
1: Clear: Clears the reset flag

OBLRSTF

Bit 25: Option byte loader reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

PINRSTF

Bit 26: Pin reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

BORRSTF

Bit 27: BOR flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

SFTRSTF

Bit 28: Software reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

IWWDGRSTF

Bit 29: Independent window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

WWDGRSTF

Bit 30: Window watchdog reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

LPWRSTF

Bit 31: Low-power reset flag.

Allowed values:
0: NoReset: No reset has occured
1: Reset: A reset has occured

CRRCR

Clock recovery RC register

Offset: 0x98, size: 32, reset: 0x00000000, access: Unspecified

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48CAL
r
HSI48RDY
r
HSI48ON
rw
Toggle fields

HSI48ON

Bit 0: HSI48 clock enable.

HSI48RDY

Bit 1: HSI48 clock ready flag.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

CCIPR2

Peripherals independent clock configuration register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPISEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMCSEL
rw
SAI2SEL
rw
SAI1SEL
rw
ADFSDMSEL
rw
DFSDMSEL
rw
I2C4SEL
rw
Toggle fields

I2C4SEL

Bits 0-1: I2C4 clock source selection.

DFSDMSEL

Bit 2: Digital filter for sigma delta modulator kernel clock source selection.

ADFSDMSEL

Bits 3-4: Digital filter for sigma delta modulator audio clock source selection.

SAI1SEL

Bits 5-7: SAI1 clock source selection.

SAI2SEL

Bits 8-10: SAI2 clock source selection.

SDMMCSEL

Bit 14: SDMMC clock selection.

OSPISEL

Bits 20-21: Octospi clock source selection.

SECCFGR

RCC secure configuration register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

Toggle fields

HSISEC

Bit 0: HSISEC.

HSESEC

Bit 1: HSESEC.

MSISEC

Bit 2: MSISEC.

LSISEC

Bit 3: LSISEC.

LSESEC

Bit 4: LSESEC.

SYSCLKSEC

Bit 5: SYSCLKSEC.

PRESCSEC

Bit 6: PRESCSEC.

PLLSEC

Bit 7: PLLSEC.

PLLSAI1SEC

Bit 8: PLLSAI1SEC.

PLLSAI2SEC

Bit 9: PLLSAI2SEC.

CLK48MSEC

Bit 10: CLK48MSEC.

HSI48SEC

Bit 11: HSI48SEC.

RMVFSEC

Bit 12: RMVFSEC.

SECSR

RCC secure status register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

Toggle fields

HSISECF

Bit 0: HSISECF.

HSESECF

Bit 1: HSESECF.

MSISECF

Bit 2: MSISECF.

LSISECF

Bit 3: LSISECF.

LSESECF

Bit 4: LSESECF.

SYSCLKSECF

Bit 5: SYSCLKSECF.

PRESCSECF

Bit 6: PRESCSECF.

PLLSECF

Bit 7: PLLSECF.

PLLSAI1SECF

Bit 8: PLLSAI1SECF.

PLLSAI2SECF

Bit 9: PLLSAI2SECF.

CLK48MSECF

Bit 10: CLK48MSECF.

HSI48SECF

Bit 11: HSI48SECF.

RMVFSECF

Bit 12: RMVFSECF.

AHB1SECSR

RCC AHB1 security status register

Offset: 0xe8, size: 32, reset: 0x00400300, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESECF
r
GTZCSECF
r
TSCSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCSECF
r
SRAM1SECF
r
FLASHSECF
r
DMAMUX1SECF
r
DMA2SECF
r
DMA1SECF
r
Toggle fields

DMA1SECF

Bit 0: DMA1SECF.

DMA2SECF

Bit 1: DMA2SECF.

DMAMUX1SECF

Bit 2: DMAMUX1SECF.

FLASHSECF

Bit 8: FLASHSECF.

SRAM1SECF

Bit 9: SRAM1SECF.

CRCSECF

Bit 12: CRCSECF.

TSCSECF

Bit 16: TSCSECF.

GTZCSECF

Bit 22: GTZCSECF.

ICACHESECF

Bit 23: ICACHESECF.

AHB2SECSR

RCC AHB2 security status register

Offset: 0xec, size: 32, reset: 0x002002FF, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC1SECF
r
OTFDEC1SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2SECF
r
GPIOHSECF
r
GPIOGSECF
r
GPIOFSECF
r
GPIOESECF
r
GPIODSECF
r
GPIOCSECF
r
GPIOBSECF
r
GPIOASECF
r
Toggle fields

GPIOASECF

Bit 0: GPIOASECF.

GPIOBSECF

Bit 1: GPIOBSECF.

GPIOCSECF

Bit 2: GPIOCSECF.

GPIODSECF

Bit 3: GPIODSECF.

GPIOESECF

Bit 4: GPIOESECF.

GPIOFSECF

Bit 5: GPIOFSECF.

GPIOGSECF

Bit 6: GPIOGSECF.

GPIOHSECF

Bit 7: GPIOHSECF.

SRAM2SECF

Bit 9: SRAM2SECF.

OTFDEC1SECF

Bit 21: OTFDEC1SECF.

SDMMC1SECF

Bit 22: SDMMC1SECF.

AHB3SECSR

RCC AHB3 security status register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SECF
r
FSMCSECF
r
Toggle fields

FSMCSECF

Bit 0: FSMCSECF.

OSPI1SECF

Bit 8: OSPI1SECF.

APB1SECSR1

RCC APB1 security status register 1

Offset: 0xf8, size: 32, reset: 0x00000400, access: read-only

22/22 fields covered.

Toggle fields

TIM2SECF

Bit 0: TIM2SECF.

TIM3SECF

Bit 1: TIM3SECF.

TIM4SECF

Bit 2: TIM4SECF.

TIM5SECF

Bit 3: TIM5SECF.

TIM6SECF

Bit 4: TIM6SECF.

TIM7SECF

Bit 5: TIM7SECF.

RTCAPBSECF

Bit 10: RTCAPBSECF.

WWDGSECF

Bit 11: WWDGSECF.

SPI2SECF

Bit 14: SPI2SECF.

SPI3SECF

Bit 15: SPI3SECF.

UART2SECF

Bit 17: UART2SECF.

UART3SECF

Bit 18: UART3SECF.

UART4SECF

Bit 19: UART4SECF.

UART5SECF

Bit 20: UART5SECF.

I2C1SECF

Bit 21: I2C1SECF.

I2C2SECF

Bit 22: I2C2SECF.

I2C3SECF

Bit 23: I2C3SECF.

CRSSECF

Bit 24: CRSSECF.

PWRSECF

Bit 28: PWRSECF.

DACSECF

Bit 29: DACSECF.

OPAMPSECF

Bit 30: OPAMPSECF.

LPTIM1SECF

Bit 31: LPTIM1SECF.

APB1SECSR2

RCC APB1 security status register 2

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1SECF
r
USBFSSECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCAN1SECF
r
LPTIM3SECF
r
LPTIM2SECF
r
I2C4SECF
r
LPUART1SECF
r
Toggle fields

LPUART1SECF

Bit 0: LPUART1SECF.

I2C4SECF

Bit 1: I2C4SECF.

LPTIM2SECF

Bit 5: LPTIM2SECF.

LPTIM3SECF

Bit 6: LPTIM3SECF.

FDCAN1SECF

Bit 9: FDCAN1SECF.

USBFSSECF

Bit 21: USBFSSECF.

UCPD1SECF

Bit 23: UCPD1SECF.

APB2SECSR

RCC APB2 security status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SECF
r
SAI2SECF
r
SAI1SECF
r
TIM17SECF
r
TIM16SECF
r
TIM15SECF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1SECF
r
TIM8SECF
r
SPI1SECF
r
TIM1SECF
r
SYSCFGSECF
r
Toggle fields

SYSCFGSECF

Bit 0: SYSCFGSECF.

TIM1SECF

Bit 11: TIM1SECF.

SPI1SECF

Bit 12: SPI1SECF.

TIM8SECF

Bit 13: TIM8SECF.

USART1SECF

Bit 14: USART1SECF.

TIM15SECF

Bit 16: TIM15SECF.

TIM16SECF

Bit 17: TIM16SECF.

TIM17SECF

Bit 18: TIM17SECF.

SAI1SECF

Bit 21: SAI1SECF.

SAI2SECF

Bit 22: SAI2SECF.

DFSDM1SECF

Bit 24: DFSDM1SECF.

SEC_RNG

0x520c0800: RNG

4/17 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x10 HTCR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFIGLOCK
rw
CONDRST
rw
RNG_CONFIG1
rw
CLKDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2
rw
NISTC
rw
RNG_CONFIG3
rw
CED
rw
IE
rw
RNGEN
rw
Toggle fields

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

CED

Bit 5: Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled..

RNG_CONFIG3

Bits 8-11: RNG configuration 3.

NISTC

Bit 12: Non NIST compliant.

RNG_CONFIG2

Bits 13-15: RNG configuration 2.

CLKDIV

Bits 16-19: Clock divider factor.

RNG_CONFIG1

Bits 20-25: RNG configuration 1.

CONDRST

Bit 30: Conditioning soft reset.

CONFIGLOCK

Bit 31: RNG Config Lock.

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw
CEIS
rw
SECS
r
CECS
r
DRDY
r
Toggle fields

DRDY

Bit 0: Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated..

CECS

Bit 1: Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SECS

Bit 2: Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01).

CEIS

Bit 5: Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1..

SEIS

Bit 6: Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register..

DR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: Random data 32-bit random data which are valid when DRDY=1..

HTCR

The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0.

Offset: 0x10, size: 32, reset: 0x000CAA74, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG
rw
Toggle fields

HTCFG

Bits 0-31: health test configuration.

SEC_RTC

0x50002800: Real-time clock

129/147 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x1c PRIVCR
0x20 SMCR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x58 SMISR
0x5c SCR
Toggle registers

TR

time register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

date register

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

Allowed values: 0x0-0xffff

ICSR

RTC initialization control and status register

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw
INITF
r
RSF
r/w0c
INITS
r
SHPF
rw
WUTWF
r
ALR[B]WF
r
ALR[A]WF
r
Toggle fields

ALR[A]WF

Bit 0: Alarm A write flag.

ALR[B]WF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: Shift operation pending.

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: Initialization status flag.

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: Registers synchronization flag.

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: Initialization flag.

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: Initialization mode.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

RECALPF

Bit 16: Recalibration pending Flag.

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

prescaler register

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

Allowed values: 0x0-0x7f

WUTR

wakeup timer register

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUTOCLR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: Wakeup auto-reload value bits.

Allowed values: 0x0-0xffff

WUTOCLR

Bits 16-31: WUTOCLR.

CR

RTC control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw
TAMPALRM_TYPE
rw
TAMPALRM_PU
rw
TAMPOE
rw
TAMPTS
rw
ITSE
rw
COE
rw
OSEL
rw
POL
rw
COSEL
rw
BKP
rw
SUB1H
rw
ADD1H
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw
WUTIE
rw
ALR[B]IE
rw
ALR[A]IE
rw
TSE
rw
WUTE
rw
ALR[B]E
rw
ALR[A]E
rw
FMT
rw
BYPSHAD
rw
REFCKON
rw
TSEDGE
rw
WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: TSEDGE.

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: REFCKON.

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: BYPSHAD.

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: FMT.

Allowed values:
0: TwentyFourHour: 24 hour/day format
1: AmPm: AM/PM hour format

ALR[A]E

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

ALR[B]E

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

WUTE

Bit 10: WUTE.

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: TSE.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALR[A]IE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

ALR[B]IE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

WUTIE

Bit 14: WUTIE.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: TSIE.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: ADD1H.

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: SUB1H.

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: BKP.

Allowed values:
0: DSTNotChanged: Daylight Saving Time change has not been performed
1: DSTChanged: Daylight Saving Time change has been performed

COSEL

Bit 19: COSEL.

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: POL.

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: OSEL.

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: COE.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ITSE

Bit 24: ITSE.

Allowed values:
0: Disabled: Internal event timestamp disabled
1: Enabled: Internal event timestamp enabled

TAMPTS

Bit 25: TAMPTS.

Allowed values:
0: Disabled: Tamper detection event does not cause a RTC timestamp to be saved
1: Enabled: Save RTC timestamp on tamper detection event

TAMPOE

Bit 26: TAMPOE.

Allowed values:
0: Disabled: The tamper flag is not routed on TAMPALRM
1: Enabled: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

Allowed values:
0: NoPullUp: No pull-up is applied on TAMPALRM output
1: PullUp: A pull-up is applied on TAMPALRM output

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

Allowed values:
0: PushPull: TAMPALRM is push-pull output
1: OpenDrain: TAMPALRM is open-drain output

OUT2EN

Bit 31: OUT2EN.

Allowed values:
0: Disabled: RTC output 2 disable
1: Enabled: RTC output 2 enable

PRIVCR

RTC privilege mode control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIV
rw
INITPRIV
rw
CALPRIV
rw
TSPRIV
rw
WUTPRIV
rw
ALRBPRIV
rw
ALRAPRIV
rw
Toggle fields

ALRAPRIV

Bit 0: ALRAPRIV.

ALRBPRIV

Bit 1: ALRBPRIV.

WUTPRIV

Bit 2: WUTPRIV.

TSPRIV

Bit 3: TSPRIV.

CALPRIV

Bit 13: CALPRIV.

INITPRIV

Bit 14: INITPRIV.

PRIV

Bit 15: PRIV.

SMCR

RTC secure mode control register

Offset: 0x20, size: 32, reset: 0x0000E00F, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT
rw
INITDPROT
rw
CALDPROT
rw
TSDPROT
rw
WUTDPROT
rw
ALRBDPROT
rw
ALRADPROT
rw
Toggle fields

ALRADPROT

Bit 0: ALRADPROT.

ALRBDPROT

Bit 1: ALRBDPROT.

WUTDPROT

Bit 2: WUTDPROT.

TSDPROT

Bit 3: TSDPROT.

CALDPROT

Bit 13: CALDPROT.

INITDPROT

Bit 14: INITDPROT.

DECPROT

Bit 15: DECPROT.

WPR

write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: Write protection key.

Allowed values:
0: Activate: Activate write protection (any value that is not the keys)
83: Deactivate2: Key 2
202: Deactivate1: Key 1

CALR

calibration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw
CALW8
rw
CALW16
rw
LPCAL
rw
CALM
rw
Toggle fields

CALM

Bits 0-8: Calibration minus.

Allowed values: 0x0-0x1ff

LPCAL

Bit 12: LPCAL.

CALW16

Bit 13: Use a 16-second calibration cycle period.

Allowed values:
1: SixteenSeconds: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: Use an 8-second calibration cycle period.

Allowed values:
1: EightSeconds: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

SHIFTR

shift control register

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: Subtract a fraction of a second.

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: Add one second.

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

time stamp time register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw
MNU
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

time stamp date register

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw
YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw
MT
rw
MU
rw
DT
rw
DU
rw
Toggle fields

DU

Bits 0-3: Date units in BCD format.

Allowed values: 0x0-0xf

DT

Bits 4-5: Date tens in BCD format.

Allowed values: 0x0-0x3

MU

Bits 8-11: Month units in BCD format.

Allowed values: 0x0-0xf

MT

Bit 12: Month tens in BCD format.

Allowed values: 0x0-0x1

WDU

Bits 13-15: Week day units.

Allowed values: 0x1-0x7

YU

Bits 16-19: Year units in BCD format.

Allowed values: 0x0-0xf

YT

Bits 20-23: Year tens in BCD format.

Allowed values: 0x0-0xf

TSSSR

timestamp sub second register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

Allowed values: 0x0-0xffff

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw
WDSEL
rw
DT
rw
DU
rw
MSK3
rw
PM
rw
HT
rw
HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw
MNT
rw
MNU
rw
MSK1
rw
ST
rw
SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: AM/PM notation.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: Week day selection.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: Sub seconds value.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

SR

RTC status register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSF
r
TSOVF
r
TSF
r
WUTF
r
ALR[B]F
r
ALR[A]F
r
Toggle fields

ALR[A]F

Bit 0: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

ALR[B]F

Bit 1: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

WUTF

Bit 2: WUTF.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 3: TSF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 4: TSOVF.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSF

Bit 5: ITSF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r
TSOVMF
r
TSMF
r
WUTMF
r
ALR[B]MF
r
ALR[A]MF
r
Toggle fields

ALR[A]MF

Bit 0: Alarm A masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

ALR[B]MF

Bit 1: Alarm B masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

WUTMF

Bit 2: WUTMF.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSMF

Bit 3: TSMF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVMF

Bit 4: TSOVMF.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSMF

Bit 5: ITSMF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

SMISR

RTC secure masked interrupt status register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r
TSOVMF
r
TSMF
r
WUTMF
r
ALRBMF
r
ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SCR

RTC status clear register

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITSF
w
CTSOVF
w
CTSF
w
CWUTF
w
CALRBF
w
CALRAF
w
Toggle fields

CALRAF

Bit 0: CALRAF.

Allowed values:
1: Clear: Clear interrupt flag

CALRBF

Bit 1: CALRBF.

Allowed values:
1: Clear: Clear interrupt flag

CWUTF

Bit 2: CWUTF.

Allowed values:
1: Clear: Clear interrupt flag

CTSF

Bit 3: CTSF.

Allowed values:
1: Clear: Clear interrupt flag

CTSOVF

Bit 4: CTSOVF.

Allowed values:
1: Clear: Clear interrupt flag

CITSF

Bit 5: CITSF.

Allowed values:
1: Clear: Clear interrupt flag

SEC_SAI1

0x50015400: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw
SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw
CKEN1
rw
MICNBR
rw
PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw
DLYM[4]L
rw
DLYM[3]R
rw
DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw
DLYM[2]L
rw
DLYM[1]R
rw
DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SEC_SAI2

0x50015800: Serial audio interface

84/118 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 CR1 [A]
0x8 CR2 [A]
0xc FRCR [A]
0x10 SLOTR [A]
0x14 IM [A]
0x18 SR [A]
0x1c CLRFR [A]
0x20 DR [A]
0x24 CR1 [B]
0x28 CR2 [B]
0x2c FRCR [B]
0x30 SLOTR [B]
0x34 IM [B]
0x38 SR [B]
0x3c CLRFR [B]
0x40 DR [B]
0x44 PDMCR
0x48 PDMDLY
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw
SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

CR1 [A]

AConfiguration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [A]

AConfiguration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [A]

AFRCR

Offset: 0xc, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [A]

ASlot register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [A]

AInterrupt mask register2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [A]

AStatus register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [A]

AClear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [A]

AData register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

CR1 [B]

AConfiguration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

11/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSR
rw
MCKDIV
rw
NODIV
rw
DMAEN
rw
SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw
MONO
rw
SYNCEN
rw
CKSTR
rw
LSBFIRST
rw
DS
rw
PRTCFG
rw
MODE
rw
Toggle fields

MODE

Bits 0-1: Audio block mode.

Allowed values:
0: MasterTx: Master transmitter
1: MasterRx: Master receiver
2: SlaveTx: Slave transmitter
3: SlaveRx: Slave receiver

PRTCFG

Bits 2-3: Protocol configuration.

Allowed values:
0: Free: Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol
1: Spdif: SPDIF protocol
2: Ac97: AC’97 protocol

DS

Bits 5-7: Data size.

Allowed values:
2: Bit8: 8 bits
3: Bit10: 10 bits
4: Bit16: 16 bits
5: Bit20: 20 bits
6: Bit24: 24 bits
7: Bit32: 32 bits

LSBFIRST

Bit 8: Least significant bit first.

Allowed values:
0: MsbFirst: Data are transferred with MSB first
1: LsbFirst: Data are transferred with LSB first

CKSTR

Bit 9: Clock strobing edge.

Allowed values:
0: FallingEdge: Data strobing edge is falling edge of SCK
1: RisingEdge: Data strobing edge is rising edge of SCK

SYNCEN

Bits 10-11: Synchronization enable.

Allowed values:
0: Asynchronous: audio sub-block in asynchronous mode
1: Internal: audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode
2: External: audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode

MONO

Bit 12: Mono mode.

Allowed values:
0: Stereo: Stereo mode
1: Mono: Mono mode

OUTDRIV

Bit 13: Output drive.

Allowed values:
0: OnStart: Audio block output driven when SAIEN is set
1: Immediately: Audio block output driven immediately after the setting of this bit

SAIEN

Bit 16: Audio block A enable.

Allowed values:
0: Disabled: SAI audio block disabled
1: Enabled: SAI audio block enabled

DMAEN

Bit 17: DMA enable.

Allowed values:
0: Disabled: DMA disabled
1: Enabled: DMA enabled

NODIV

Bit 19: No divider.

Allowed values:
0: MasterClock: MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value
1: NoDiv: MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.

MCKDIV

Bits 20-23: Master clock divider.

OSR

Bit 26: OSR.

CR2 [B]

AConfiguration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw
CPL
rw
MUTECNT
rw
MUTEVAL
rw
MUTE
rw
TRIS
rw
FFLUSH
w
FTH
rw
Toggle fields

FTH

Bits 0-2: FIFO threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: 1⁄4 FIFO
2: Quarter2: 1⁄2 FIFO
3: Quarter3: 3⁄4 FIFO
4: Full: FIFO full

FFLUSH

Bit 3: FIFO flush.

Allowed values:
0: NoFlush: No FIFO flush
1: Flush: FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

Allowed values:
0: Disabled: No mute mode
1: Enabled: Mute mode enabled

MUTEVAL

Bit 6: Mute value.

Allowed values:
0: SendZero: Bit value 0 is sent during the mute mode
1: SendLast: Last values are sent during the mute mode

MUTECNT

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

Allowed values:
0: OnesComplement: 1’s complement representation
1: TwosComplement: 2’s complement representation

COMP

Bits 14-15: Companding mode.

Allowed values:
0: NoCompanding: No companding algorithm
2: MuLaw: μ-Law algorithm
3: ALaw: A-Law algorithm

FRCR [B]

AFRCR

Offset: 0x2c, size: 32, reset: 0x00000007, access: read-write

2/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw
FSPOL
rw
FSDEF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw
FRL
rw
Toggle fields

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

Allowed values:
0: FallingEdge: FS is active low (falling edge)
1: RisingEdge: FS is active high (rising edge)

FSOFF

Bit 18: Frame synchronization offset.

Allowed values:
0: OnFirst: FS is asserted on the first bit of the slot 0
1: BeforeFirst: FS is asserted one bit before the first bit of the slot 0

SLOTR [B]

ASlot register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw
SLOTSZ
rw
FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

Allowed values:
0: DataSize: The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)
1: Bit16: 16-bit
2: Bit32: 32-bit

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

Allowed values:
0: Inactive: Inactive slot
1: Active: Active slot

IM [B]

AInterrupt mask register2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw
AFSDETIE
rw
CNRDYIE
rw
FREQIE
rw
WCKCFGIE
rw
MUTEDETIE
rw
OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

MUTEDETIE

Bit 1: Mute detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

WCKCFGIE

Bit 2: Wrong clock configuration interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

FREQIE

Bit 3: FIFO request interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

CNRDYIE

Bit 4: Codec not ready interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is enabled

SR [B]

AStatus register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r
AFSDET
r
CNRDY
r
FREQ
r
WCKCFG
r
MUTEDET
r
OVRUDR
r
Toggle fields

OVRUDR

Bit 0: Overrun / underrun.

Allowed values:
0: NoError: No overrun/underrun error
1: Overrun: Overrun/underrun error detection

MUTEDET

Bit 1: Mute detection.

Allowed values:
0: NoMute: No MUTE detection on the SD input line
1: Mute: MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

Allowed values:
0: Correct: Clock configuration is correct
1: Wrong: Clock configuration does not respect the rule concerning the frame length specification

FREQ

Bit 3: FIFO request.

Allowed values:
0: NoRequest: No FIFO request
1: Request: FIFO request to read or to write the SAI_xDR

CNRDY

Bit 4: Codec not ready.

Allowed values:
0: Ready: External AC’97 Codec is ready
1: NotReady: External AC’97 Codec is not ready

AFSDET

Bit 5: Anticipated frame synchronization detection.

Allowed values:
0: NoError: No error
1: EarlySync: Frame synchronization signal is detected earlier than expected

LFSDET

Bit 6: Late frame synchronization detection.

Allowed values:
0: NoError: No error
1: NoSync: Frame synchronization signal is not present at the right time

FLVL

Bits 16-18: FIFO level threshold.

Allowed values:
0: Empty: FIFO empty
1: Quarter1: FIFO <= 1⁄4 but not empty
2: Quarter2: 1⁄4 < FIFO <= 1⁄2
3: Quarter3: 1⁄2 < FIFO <= 3⁄4
4: Quarter4: 3⁄4 < FIFO but not full
5: Full: FIFO full

CLRFR [B]

AClear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w
CAFSDET
w
CCNRDY
w
CWCKCFG
w
CMUTEDET
w
COVRUDR
w
Toggle fields

COVRUDR

Bit 0: Clear overrun / underrun.

Allowed values:
1: Clear: Clears the OVRUDR flag

CMUTEDET

Bit 1: Mute detection flag.

Allowed values:
1: Clear: Clears the MUTEDET flag

CWCKCFG

Bit 2: Clear wrong clock configuration flag.

Allowed values:
1: Clear: Clears the WCKCFG flag

CCNRDY

Bit 4: Clear codec not ready flag.

Allowed values:
1: Clear: Clears the CNRDY flag

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

Allowed values:
1: Clear: Clears the AFSDET flag

CLFSDET

Bit 6: Clear late frame synchronization detection flag.

Allowed values:
1: Clear: Clears the LFSDET flag

DR [B]

AData register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN2
rw
CKEN1
rw
MICNBR
rw
PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: CKEN2.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM[4]R
rw
DLYM[4]L
rw
DLYM[3]R
rw
DLYM[3]L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM[2]R
rw
DLYM[2]L
rw
DLYM[1]R
rw
DLYM[1]L
rw
Toggle fields

DLYM[1]L

Bits 0-2: Delay line adjust for first microphone of pair 1.

DLYM[1]R

Bits 4-6: Delay line adjust for second microphone of pair 1.

DLYM[2]L

Bits 8-10: Delay line adjust for first microphone of pair 2.

DLYM[2]R

Bits 12-14: Delay line adjust for second microphone of pair 2.

DLYM[3]L

Bits 16-18: Delay line adjust for first microphone of pair 3.

DLYM[3]R

Bits 20-22: Delay line adjust for second microphone of pair 3.

DLYM[4]L

Bits 24-26: Delay line adjust for first microphone of pair 4.

DLYM[4]R

Bits 28-30: Delay line adjust for second microphone of pair 4.

SEC_SDMMC1

0x520c8000: SDMMC1

38/125 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASE0R
0x5c IDMABASE1R
0x80 FIFOR
0x3f4 VER
0x3f8 ID
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw
VSWITCHEN
rw
VSWITCH
rw
PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11..

VSWITCH

Bit 2: Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:.

VSWITCHEN

Bit 3: Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:.

DIRPOL

Bit 4: Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)..

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw
BUSSPEED
rw
DDR
rw
HWFC_EN
rw
NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw
PWRSAV
rw
CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc...

PWRSAV

Bit 12: Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:.

WIDBUS

Bits 14-15: Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

NEGEDGE

Bit 16: SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division >1 (CLKDIV > 0) & DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge..

HWFC_EN

Bit 17: Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11..

DDR

Bit 18: Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &gt;1. (CLKDIV &gt; 0).

BUSSPEED

Bit 19: Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

SELCLKRX

Bits 20-21: Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0).

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register..

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw
BOOTMODE
rw
DTHOLD
rw
CPSMEN
rw
WAITPEND
rw
WAITINT
rw
WAITRESP
rw
CMDSTOP
rw
CMDTRANS
rw
CMDINDEX
rw
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CMDINDEX

Bits 0-5: Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message..

CMDTRANS

Bit 6: The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent..

CMDSTOP

Bit 7: The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent..

WAITRESP

Bits 8-9: Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response..

WAITINT

Bit 10: CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode..

WAITPEND

Bit 11: CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card..

CPSMEN

Bit 12: Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0..

DTHOLD

Bit 13: Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state..

BOOTMODE

Bit 14: Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0).

BOOTEN

Bit 15: Enable boot mode procedure..

CMDSUSPEND

Bit 16: The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1..

RESPCMDR

SDMMC command response register

Offset: 0x10, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: Response command index.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
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CARDSTATUS1

Bits 0-31: see Table 432.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
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CARDSTATUS2

Bits 0-31: see Table404..

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
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CARDSTATUS3

Bits 0-31: see Table404..

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
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CARDSTATUS4

Bits 0-31: see Table404..

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
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DATATIME

Bits 0-31: Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods..

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
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DATALENGTH

Bits 0-24: Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0..

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw
BOOTACKEN
rw
SDIOEN
rw
RWMOD
rw
RWSTOP
rw
RWSTART
rw
DBLOCKSIZE
rw
DTMODE
rw
DTDIR
rw
DTEN
rw
Toggle fields

DTEN

Bit 0: Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards..

DTDIR

Bit 1: Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DTMODE

Bits 2-3: Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

DBLOCKSIZE

Bits 4-7: Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered).

RWSTART

Bit 8: Read wait start. If this bit is set, read wait operation starts..

RWSTOP

Bit 9: Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state..

RWMOD

Bit 10: Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

SDIOEN

Bit 11: SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation..

BOOTACKEN

Bit 12: Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

FIFORST

Bit 13: FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs..

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
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DATACOUNT

Bits 0-24: Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect..

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

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CCRCFAIL

Bit 0: Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DCRCFAIL

Bit 1: Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CTIMEOUT

Bit 2: Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods..

DTIMEOUT

Bit 3: Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

TXUNDERR

Bit 4: Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

RXOVERR

Bit 5: Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDREND

Bit 6: Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CMDSENT

Bit 7: Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DATAEND

Bit 8: Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DHOLD

Bit 9: Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DBCKEND

Bit 10: Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DABORT

Bit 11: Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

DPSMACT

Bit 12: Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

CPSMACT

Bit 13: Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt..

TXFIFOHE

Bit 14: Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full..

RXFIFOHF

Bit 15: Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty..

TXFIFOF

Bit 16: Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty..

RXFIFOF

Bit 17: Receive FIFO full This bit is cleared when one FIFO location becomes empty..

TXFIFOE

Bit 18: Transmit FIFO empty This bit is cleared when one FIFO location becomes full..

RXFIFOE

Bit 19: Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full..

BUSYD0

Bit 20: Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt..

BUSYD0END

Bit 21: end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

SDIOIT

Bit 22: SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKFAIL

Bit 23: Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ACKTIMEOUT

Bit 24: Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

VSWEND

Bit 25: Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

CKSTOP

Bit 26: SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMATE

Bit 27: IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

IDMABTC

Bit 28: IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR..

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

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CCRCFAILC

Bit 0: CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag..

DCRCFAILC

Bit 1: DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag..

CTIMEOUTC

Bit 2: CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag..

DTIMEOUTC

Bit 3: DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag..

TXUNDERRC

Bit 4: TXUNDERR flag clear bit Set by software to clear TXUNDERR flag..

RXOVERRC

Bit 5: RXOVERR flag clear bit Set by software to clear the RXOVERR flag..

CMDRENDC

Bit 6: CMDREND flag clear bit Set by software to clear the CMDREND flag..

CMDSENTC

Bit 7: CMDSENT flag clear bit Set by software to clear the CMDSENT flag..

DATAENDC

Bit 8: DATAEND flag clear bit Set by software to clear the DATAEND flag..

DHOLDC

Bit 9: DHOLD flag clear bit Set by software to clear the DHOLD flag..

DBCKENDC

Bit 10: DBCKEND flag clear bit Set by software to clear the DBCKEND flag..

DABORTC

Bit 11: DABORT flag clear bit Set by software to clear the DABORT flag..

BUSYD0ENDC

Bit 21: BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag..

SDIOITC

Bit 22: SDIOIT flag clear bit Set by software to clear the SDIOIT flag..

ACKFAILC

Bit 23: ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag..

ACKTIMEOUTC

Bit 24: ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag..

VSWENDC

Bit 25: VSWEND flag clear bit Set by software to clear the VSWEND flag..

CKSTOPC

Bit 26: CKSTOP flag clear bit Set by software to clear the CKSTOP flag..

IDMATEC

Bit 27: IDMA transfer error clear bit Set by software to clear the IDMATE flag..

IDMABTCC

Bit 28: IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag..

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

Toggle fields

CCRCFAILIE

Bit 0: Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure..

DCRCFAILIE

Bit 1: Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure..

CTIMEOUTIE

Bit 2: Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout..

DTIMEOUTIE

Bit 3: Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout..

TXUNDERRIE

Bit 4: Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error..

RXOVERRIE

Bit 5: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error..

CMDRENDIE

Bit 6: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response..

CMDSENTIE

Bit 7: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command..

DATAENDIE

Bit 8: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end..

DHOLDIE

Bit 9: Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state..

DBCKENDIE

Bit 10: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end..

DABORTIE

Bit 11: Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted..

TXFIFOHEIE

Bit 14: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty..

RXFIFOHFIE

Bit 15: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full..

RXFIFOFIE

Bit 17: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full..

TXFIFOEIE

Bit 18: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty..

BUSYD0ENDIE

Bit 21: BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response..

SDIOITIE

Bit 22: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt..

ACKFAILIE

Bit 23: Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail..

ACKTIMEOUTIE

Bit 24: Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout..

VSWENDIE

Bit 25: Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion..

CKSTOPIE

Bit 26: Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped..

IDMABTCIE

Bit 28: IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer..

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods..

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABACT
rw
IDMABMODE
rw
IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABMODE

Bit 1: Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABACT

Bit 2: Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware..

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
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IDMABNDT

Bits 5-12: Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)..

IDMABASE0R

The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE0
rw
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IDMABASE0

Bits 0-31: Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)..

IDMABASE1R

The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE1
rw
Toggle fields

IDMABASE1

Bits 0-31: Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)..

FIFOR

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words..

VER

SDMMC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r
MINREV
r
Toggle fields

MINREV

Bits 0-3: IP minor revision number..

MAJREV

Bits 4-7: IP major revision number..

ID

SDMMC IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: SDMMC IP identification..

SEC_SPI1

0x50013000: Serial peripheral interface

33/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

13/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
CRCL
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
r/w0c
TXE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

SEC_SPI2

0x50003800: Serial peripheral interface

33/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

13/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
CRCL
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
r/w0c
TXE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

SEC_SPI3

0x50003c00: Serial peripheral interface

33/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

13/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
CRCL
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
r/w0c
TXE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

SEC_SYSCFG

0x50010000: System configuration controller

1/93 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SECCFGR
0x4 CFGR1
0x8 FPUIMR
0xc CNSLCKR
0x10 CSLOCKR
0x14 CFGR2
0x18 SCSR
0x1c SKR
0x20 SWPR
0x24 SWPR2
0x2c RSSCMDR
Toggle registers

SECCFGR

SYSCFG secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPUSEC
rw
SRAM2SEC
rw
CLASSBSEC
rw
SYSCFGSEC
rw
Toggle fields

SYSCFGSEC

Bit 0: SYSCFG clock control security.

CLASSBSEC

Bit 1: ClassB security.

SRAM2SEC

Bit 2: SRAM2 security.

FPUSEC

Bit 3: FPUSEC.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C4_FMP
rw
I2C3_FMP
rw
I2C2_FMP
rw
I2C1_FMP
rw
I2C_PB9_FMP
rw
I2C_PB8_FMP
rw
I2C_PB7_FMP
rw
I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANASWVDD
rw
BOOSTEN
rw
Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

ANASWVDD

Bit 9: GPIO analog switch control voltage selection.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

I2C4_FMP

Bit 23: I2C4_FMP.

FPUIMR

FPU interrupt mask register

Offset: 0x8, size: 32, reset: 0x0000001F, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPU_IE
rw
Toggle fields

FPU_IE

Bits 0-5: Floating point unit interrupts enable bits.

CNSLCKR

SYSCFG CPU non-secure lock register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKNSMPU
rw
LOCKNSVTOR
rw
Toggle fields

LOCKNSVTOR

Bit 0: VTOR_NS register lock.

LOCKNSMPU

Bit 1: Non-secure MPU registers lock.

CSLOCKR

SYSCFG CPU secure lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKSAU
rw
LOCKSMPU
rw
LOCKSVTAIRCR
rw
Toggle fields

LOCKSVTAIRCR

Bit 0: LOCKSVTAIRCR.

LOCKSMPU

Bit 1: LOCKSMPU.

LOCKSAU

Bit 2: LOCKSAU.

CFGR2

CFGR2

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw
ECCL
w
PVDL
w
SPL
w
CLL
w
Toggle fields

CLL

Bit 0: LOCKUP (hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SCSR

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2BSY
r
SRAM2ER
rw
Toggle fields

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

SKR

SKR

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

SWPR

SWPR

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SWPR2

SWPR2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: P63WP.

RSSCMDR

RSSCMDR

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSSCMD
rw
Toggle fields

RSSCMD

Bits 0-7: RSS commands.

SEC_TAMP

0x50003400: Tamper and backup registers

43/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc FLTCR
0x10 ATCR1
0x14 ATSEEDR
0x18 ATOR
0x1c ATCR2
0x20 SMCR
0x24 PRIVCR
0x2c IER
0x30 SR
0x34 MISR
0x38 SMISR
0x3c SCR
0x40 COUNTR
0x50 CFGR
0x100 BKP[0]R
0x104 BKP[1]R
0x108 BKP[2]R
0x10c BKP[3]R
0x110 BKP[4]R
0x114 BKP[5]R
0x118 BKP[6]R
0x11c BKP[7]R
0x120 BKP[8]R
0x124 BKP[9]R
0x128 BKP[10]R
0x12c BKP[11]R
0x130 BKP[12]R
0x134 BKP[13]R
0x138 BKP[14]R
0x13c BKP[15]R
0x140 BKP[16]R
0x144 BKP[17]R
0x148 BKP[18]R
0x14c BKP[19]R
0x150 BKP[20]R
0x154 BKP[21]R
0x158 BKP[22]R
0x15c BKP[23]R
0x160 BKP[24]R
0x164 BKP[25]R
0x168 BKP[26]R
0x16c BKP[27]R
0x170 BKP[28]R
0x174 BKP[29]R
0x178 BKP[30]R
0x17c BKP[31]R
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw
ITAMP5E
rw
ITAMP3E
rw
ITAMP2E
rw
ITAMP1E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8E
rw
TAMP7E
rw
TAMP6E
rw
TAMP5E
rw
TAMP4E
rw
TAMP3E
rw
TAMP2E
rw
TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

TAMP4E

Bit 3: TAMP4E.

TAMP5E

Bit 4: TAMP5E.

TAMP6E

Bit 5: TAMP6E.

TAMP7E

Bit 6: TAMP7E.

TAMP8E

Bit 7: TAMP8E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP8E

Bit 23: ITAMP5E.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP4NOER

Bit 3: TAMP4NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKERASE

Bit 23: BKERASE.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

TAMP4TRG

Bit 27: TAMP4TRG.

TAMP5TRG

Bit 28: TAMP5TRG.

TAMP6TRG

Bit 29: TAMP6TRG.

TAMP7TRG

Bit 30: TAMP7TRG.

TAMP8TRG

Bit 31: TAMP8TRG.

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITAMP8NOER
rw
ITAMP5NOER
rw
ITAMP3NOER
rw
ITAMP2NOER
rw
ITAMP1NOER
rw
Toggle fields

ITAMP1NOER

Bit 0: ITAMP1NOER.

ITAMP2NOER

Bit 1: ITAMP2NOER.

ITAMP3NOER

Bit 2: ITAMP3NOER.

ITAMP5NOER

Bit 4: ITAMP5NOER.

ITAMP8NOER

Bit 7: ITAMP8NOER.

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw
TAMPPRCH
rw
TAMPFLT
rw
TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

TAMP active tamper control register 1

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTEN
rw
ATOSHARE
rw
ATPER
rw
ATCKSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL4
rw
ATOSEL3
rw
ATOSEL2
rw
ATOSEL1
rw
TAMP8AM
rw
TAMP7AM
rw
TAMP6AM
rw
TAMP5AM
rw
TAMP4AM
rw
TAMP3AM
rw
TAMP2AM
rw
TAMP1AM
rw
Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

TAMP4AM

Bit 3: TAMP4AM.

TAMP5AM

Bit 4: TAMP5AM.

TAMP6AM

Bit 5: TAMP6AM.

TAMP7AM

Bit 6: TAMP7AM.

TAMP8AM

Bit 7: TAMP8AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATOSEL4

Bits 14-15: ATOSEL4.

ATCKSEL

Bits 16-17: ATCKSEL.

ATPER

Bits 24-25: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: FLTEN.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
w
Toggle fields

SEED

Bits 0-31: Pseudo-random generator seed value.

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INITS
r
SEEDF
r
PRNG
r
Toggle fields

PRNG

Bits 0-7: Pseudo-random generator value.

SEEDF

Bit 14: Seed running flag.

INITS

Bit 15: Active tamper initialization status.

ATCR2

TAMP active tamper control register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATOSEL8
rw
ATOSEL7
rw
ATOSEL6
rw
ATOSEL5
rw
ATOSEL4
rw
ATOSEL3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL3
rw
ATOSEL2
rw
ATOSEL1
rw
Toggle fields

ATOSEL1

Bits 8-10: ATOSEL1.

ATOSEL2

Bits 11-13: ATOSEL2.

ATOSEL3

Bits 14-16: ATOSEL3.

ATOSEL4

Bits 17-19: ATOSEL4.

ATOSEL5

Bits 20-22: ATOSEL5.

ATOSEL6

Bits 23-25: ATOSEL6.

ATOSEL7

Bits 26-28: ATOSEL7.

ATOSEL8

Bits 29-31: ATOSEL8.

SMCR

TAMP secure mode register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPDPROT
rw
BKPWDPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPRWDPROT
rw
Toggle fields

BKPRWDPROT

Bits 0-7: Backup registers read/write protection offset.

BKPWDPROT

Bits 16-23: Backup registers write protection offset.

TAMPDPROT

Bit 31: Tamper protection.

PRIVCR

TAMP privilege mode control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPPRIV
rw
BKPWPRIV
rw
BKPRWPRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BKPRWPRIV

Bit 29: Backup registers zone 1 privilege protection.

BKPWPRIV

Bit 30: Backup registers zone 2 privilege protection.

TAMPPRIV

Bit 31: Tamper privilege protection.

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw
ITAMP5IE
rw
ITAMP3IE
rw
ITAMP2IE
rw
ITAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8IE
rw
TAMP7IE
rw
TAMP6IE
rw
TAMP5IE
rw
TAMP4IE
rw
TAMP3IE
rw
TAMP2IE
rw
TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

TAMP4IE

Bit 3: TAMP4IE.

TAMP5IE

Bit 4: TAMP5IE.

TAMP6IE

Bit 5: TAMP6IE.

TAMP7IE

Bit 6: TAMP7IE.

TAMP8IE

Bit 7: TAMP8IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP8IE

Bit 23: ITAMP8IE.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r
ITAMP5F
r
ITAMP3F
r
ITAMP2F
r
ITAMP1F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8F
r
TAMP7F
r
TAMP6F
r
TAMP5F
r
TAMP4F
r
TAMP3F
r
TAMP2F
r
TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

TAMP4F

Bit 3: TAMP4F.

TAMP5F

Bit 4: TAMP5F.

TAMP6F

Bit 5: TAMP6F.

TAMP7F

Bit 6: TAMP7F.

TAMP8F

Bit 7: TAMP8F.

ITAMP1F

Bit 16: ITAMP1F.

ITAMP2F

Bit 17: ITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP8F

Bit 23: ITAMP8F.

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r
ITAMP5MF
r
ITAMP3MF
r
ITAMP2MF
r
ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r
TAMP7MF
r
TAMP6MF
r
TAMP5MF
r
TAMP4MF
r
TAMP3MF
r
TAMP2MF
r
TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r
ITAMP5MF
r
ITAMP3MF
r
ITAMP2MF
r
ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r
TAMP7MF
r
TAMP6MF
r
TAMP5MF
r
TAMP4MF
r
TAMP3MF
r
TAMP2MF
r
TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w
CITAMP5F
w
CITAMP3F
w
CITAMP2F
w
CITAMP1F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP8F
w
CTAMP7F
w
CTAMP6F
w
CTAMP5F
w
CTAMP4F
w
CTAMP3F
w
CTAMP2F
w
CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CTAMP4F

Bit 3: CTAMP4F.

CTAMP5F

Bit 4: CTAMP5F.

CTAMP6F

Bit 5: CTAMP6F.

CTAMP7F

Bit 6: CTAMP7F.

CTAMP8F

Bit 7: CTAMP8F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP8F

Bit 23: CITAMP8F.

COUNTR

TAMP monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: COUNT.

CFGR

TAMP configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUTMONEN
rw
VMONEN
rw
TMONEN
rw
Toggle fields

TMONEN

Bit 1: TMONEN.

VMONEN

Bit 2: VMONEN.

WUTMONEN

Bit 3: WUTMONEN.

BKP[0]R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

TAMP backup register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

TAMP backup register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

TAMP backup register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

TAMP backup register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

TAMP backup register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

TAMP backup register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

TAMP backup register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

TAMP backup register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

TAMP backup register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

TAMP backup register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

TAMP backup register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

TAMP backup register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

SEC_TIM1

0x50012c00: Advanced-timers

153/186 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

13/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS[6]
rw
OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw
OIS[3]N
rw
OIS[3]
rw
OIS[2]N
rw
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c
CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw
CC[6]E
rw
CC[5]P
rw
CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw
CC[4]P
rw
CC[4]E
rw
CC[3]NP
rw
CC[3]NE
rw
CC[3]P
rw
CC[3]E
rw
CC[2]NP
rw
CC[2]NE
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw
BKBID
rw
BK2DSRM
rw
BKDSRM
rw
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
ETR_ADC1_RMP
rw
Toggle fields

ETR_ADC1_RMP

Bits 0-1: External trigger remap on ADC1 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw
OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw
OC[6]M
rw
OC[6]PE
rw
OC[6]FE
rw
OC[5]CE
rw
OC[5]M
rw
OC[5]PE
rw
OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDFBK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK0E

Bit 8: BRK DFSDM_BREAK0 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DFBK0E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

SEC_TIM15

0x50014000: General purpose timers

74/95 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 CCR[2]
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-5: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

TIM15 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]M
rw
OC[2]PE
rw
CC[2]S
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]NP
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

CCR[2]

capture/compare register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM15 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCODER_MODE
rw
TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 0: Input capture 1 remap.

ENCODER_MODE

Bits 1-2: Encoder mode.

OR2

TIM15 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

SEC_TIM16

0x50014400: General purpose timers

51/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw
OIS[1]
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
BIF
r/w0c
COMIF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK1E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK1E

Bit 8: BRK dfsdm1_break[1] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

SEC_TIM17

0x50014800: General purpose timers

51/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw
OIS[1]
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
BIF
r/w0c
COMIF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK2E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

SEC_TIM2

0x50000000: General-purpose-timers

96/110 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw
ETR1_RMP
rw
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

ETR1_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input Capture 4 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

SEC_TIM3

0x50000400: General-purpose-timers

97/109 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

SEC_TIM4

0x50000800: General-purpose-timers

97/109 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

SEC_TIM5

0x50000c00: General-purpose-timers

96/110 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw
ETR1_RMP
rw
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

ETR1_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input Capture 4 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

SEC_TIM6

0x50001000: General-purpose-timers

13/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR_bit0.

Allowed values: 0x0-0xffff

SEC_TIM7

0x50001400: General-purpose-timers

13/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR_bit0.

Allowed values: 0x0-0xffff

SEC_TIM8

0x50013400: Advanced-timers

153/185 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

13/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS[6]
rw
OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw
OIS[3]N
rw
OIS[3]
rw
OIS[2]N
rw
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c
CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw
CC[6]E
rw
CC[5]P
rw
CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw
CC[4]P
rw
CC[4]E
rw
CC[3]NP
rw
CC[3]NE
rw
CC[3]P
rw
CC[3]E
rw
CC[2]NP
rw
CC[2]NE
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw
BKBID
rw
BK2DSRM
rw
BKDSRM
rw
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw
OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw
OC[6]M
rw
OC[6]PE
rw
OC[6]FE
rw
OC[5]CE
rw
OC[5]M
rw
OC[5]PE
rw
OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK2E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DFBK3E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK3E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

SEC_TSC

0x50024000: Touch sensing controller

16/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IER
0x8 ICR
0xc ISR
0x10 IOHCR
0x18 IOASCR
0x20 IOSCR
0x28 IOCCR
0x30 IOGCSR
0x34 IOG1CR
0x38 IOG2CR
0x3c IOG3CR
0x40 IOG4CR
0x44 IOG5CR
0x48 IOG6CR
0x4c IOG7CR
0x50 IOG8CR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw
CTPL
rw
SSD
rw
SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw
PGPSC
rw
MCV
rw
IODEF
rw
SYNCPOL
rw
AM
rw
START
rw
TSCE
rw
Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw
EOAIE
rw
Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw
EOAIC
rw
Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw
EOAF
rw
Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
r
G7S
r
G6S
r
G5S
r
G4S
r
G3S
r
G2S
r
G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw
G7E
rw
G6E
rw
G5E
rw
G4E
rw
G3E
rw
G2E
rw
G1E
rw
Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG1CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG2CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG3CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG4CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG5CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG6CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG7CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG8CR

I/O group x counter register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

SEC_UART4

0x50004c00: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

SEC_UART5

0x50005000: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

SEC_UCPD1

0x5000dc00: USB Power Delivery interface

96/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFGR1
0x4 CFGR2
0x8 CFGR3
0xc CR
0x10 IMR
0x14 SR
0x18 ICR
0x1c TX_ORDSETR
0x20 TX_PAYSZR
0x24 TXDR
0x28 RX_ORDSETR
0x2c RX_PAYSZR
0x30 RXDR
0x34 RX_ORDEXTR1
0x38 RX_ORDEXTR2
Toggle registers

CFGR1

UCPD configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

HBITCLKDIV

Bits 0-5: HBITCLKDIV.

Allowed values: 0x0-0x3f

IFRGAP

Bits 6-10: IFRGAP.

Allowed values: 0x1-0x1f

TRANSWIN

Bits 11-15: TRANSWIN.

Allowed values: 0x1-0x1f

PSC_USBPDCLK

Bits 17-19: PSC_USBPDCLK.

Allowed values:
0: Div1: Divide by 1
1: Div2: Divide by 2
2: Div4: Divide by 4
3: Div8: Divide by 8
4: Div16: Divide by 16

RXORDSETEN0

Bit 20: SOP detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN1

Bit 21: SOP' detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN2

Bit 22: SOP'' detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN3

Bit 23: Hard Reset detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN4

Bit 24: Cable Detect reset.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN5

Bit 25: SOP'_Debug.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN6

Bit 26: SOP'' Debug.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN7

Bit 27: SOP extension #1.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN8

Bit 28: SOP extension #2.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

TXDMAEN

Bit 29: TXDMAEN.

Allowed values:
0: Disabled: DMA mode for transmission disabled
1: Enabled: DMA mode for transmission enabled

RXDMAEN

Bit 30: RXDMAEN:.

Allowed values:
0: Disabled: DMA mode for reception disabled
1: Enabled: DMA mode for reception enabled

UCPDEN

Bit 31: UCPDEN.

Allowed values:
0: Disabled: UCPD peripheral disabled
1: Enabled: UCPD peripheral enabled

CFGR2

UCPD configuration register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN
rw
FORCECLK
rw
RXFILT2N3
rw
RXFILTDIS
rw
Toggle fields

RXFILTDIS

Bit 0: RXFILTDIS.

Allowed values:
0: Enabled: Rx pre-filter enabled
1: Disabled: Rx pre-filter disabled

RXFILT2N3

Bit 1: RXFILT2N3.

Allowed values:
0: Samp3: 3 samples
1: Samp2: 2 samples

FORCECLK

Bit 2: FORCECLK.

Allowed values:
0: NoForce: Do not force clock request
1: Force: Force clock request

WUPEN

Bit 3: WUPEN.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

CFGR3

UCPD configuration register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRIM2_NG_CC3A0
rw
TRIM2_NG_CC1A5
rw
TRIM2_NG_CCRPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM1_NG_CC3A0
rw
TRIM1_NG_CC1A5
rw
TRIM1_NG_CCRPD
rw
Toggle fields

TRIM1_NG_CCRPD

Bits 0-3: TRIM1_NG_CCRPD.

Allowed values: 0x0-0xf

TRIM1_NG_CC1A5

Bits 4-8: TRIM1_NG_CC1A5.

Allowed values: 0x0-0xf

TRIM1_NG_CC3A0

Bits 9-12: TRIM1_NG_CC3A0.

Allowed values: 0x0-0xf

TRIM2_NG_CCRPD

Bits 16-19: TRIM2_NG_CCRPD.

Allowed values: 0x0-0xf

TRIM2_NG_CC1A5

Bits 20-24: TRIM2_NG_CC1A5.

Allowed values: 0x0-0xf

TRIM2_NG_CC3A0

Bits 25-28: TRIM2_NG_CC3A0.

Allowed values: 0x0-0xf

CR

UCPD control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC2TCDIS
rw
CC1TCDIS
rw
RDCH
rw
FRSTX
rw
FRSRXEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCENABLE
rw
ANAMODE
rw
ANASUBMODE
rw
PHYCCSEL
rw
PHYRXEN
rw
RXMODE
rw
TXHRST
rw
TXSEND
rw
TXMODE
rw
Toggle fields

TXMODE

Bits 0-1: TXMODE.

Allowed values:
0: RegisterSet: Transmission of Tx packet previously defined in other registers
1: CableReset: Cable Reset sequence
2: BISTTest: BIST test sequence (BIST Carrier Mode 2)

TXSEND

Bit 2: TXSEND.

Allowed values:
0: NoEffect: No effect
1: Start: Start Tx packet transmission

TXHRST

Bit 3: TXHRST.

Allowed values:
0: NoEffect: No effect
1: Start: Start Tx Hard Reset message

RXMODE

Bit 4: RXMODE.

Allowed values:
0: Normal: Normal receive mode
1: BIST: BIST receive mode (BIST test data mode)

PHYRXEN

Bit 5: PHYRXEN.

Allowed values:
0: Disabled: USB Power Delivery receiver disabled
1: Enabled: USB Power Delivery receiver enabled

PHYCCSEL

Bit 6: PHYCCSEL.

Allowed values:
0: CC1: Use CC1 IO for Power Delivery communication
1: CC2: Use CC2 IO for Power Delivery communication

ANASUBMODE

Bits 7-8: ANASUBMODE.

Allowed values:
0: Disabled: Disabled
1: Rp_DefaultUSB: Default USB Rp
2: Rp_1_5A: 1.5A Rp
3: Rp_3A: 3A Rp

ANAMODE

Bit 9: ANAMODE.

Allowed values:
0: Source: Source
1: Sink: Sink

CCENABLE

Bits 10-11: CCENABLE.

Allowed values:
0: Disabled: Both PHYs disabled
1: CC1Enabled: CC1 PHY enabled
2: CC2Enabled: CC2 PHY enabled
3: BothEnabled: CC1 and CC2 PHYs enabled

FRSRXEN

Bit 16: FRSRXEN.

Allowed values:
0: Disabled: FRS Rx event detection disabled
1: Enabled: FRS Rx event detection enabled

FRSTX

Bit 17: FRSTX.

Allowed values:
0: NoEffect: No effect
1: Enabled: FRS Tx signaling enabled

RDCH

Bit 18: RDCH.

Allowed values:
0: NoEffect: No effect
1: ConditionDrive: Rdch condition drive

CC1TCDIS

Bit 20: CC1TCDIS.

Allowed values:
0: Enabled: Type-C detector on the CCx line enabled
1: Disabled: Type-C detector on the CCx line disabled

CC2TCDIS

Bit 21: CC2TCDIS.

Allowed values:
0: Enabled: Type-C detector on the CCx line enabled
1: Disabled: Type-C detector on the CCx line disabled

IMR

UCPD Interrupt Mask Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2IE
rw
TYPECEVT1IE
rw
RXMSGENDIE
rw
RXOVRIE
rw
RXHRSTDETIE
rw
RXORDDETIE
rw
RXNEIE
rw
TXUNDIE
rw
HRSTSENTIE
rw
HRSTDISCIE
rw
TXMSGABTIE
rw
TXMSGSENTIE
rw
TXMSGDISCIE
rw
TXISIE
rw
Toggle fields

TXISIE

Bit 0: TXISIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXMSGDISCIE

Bit 1: TXMSGDISCIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXMSGSENTIE

Bit 2: TXMSGSENTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXMSGABTIE

Bit 3: TXMSGABTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HRSTDISCIE

Bit 4: HRSTDISCIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HRSTSENTIE

Bit 5: HRSTSENTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXUNDIE

Bit 6: TXUNDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXNEIE

Bit 8: RXNEIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXORDDETIE

Bit 9: RXORDDETIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXHRSTDETIE

Bit 10: RXHRSTDETIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXOVRIE

Bit 11: RXOVRIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXMSGENDIE

Bit 12: RXMSGENDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TYPECEVT1IE

Bit 14: TYPECEVT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TYPECEVT2IE

Bit 15: TYPECEVT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

FRSEVTIE

Bit 20: FRSEVTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

UCPD Status Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

Toggle fields

TXIS

Bit 0: TXIS.

Allowed values:
0: NotRequired: New Tx data write not required
1: Required: New Tx data write required

TXMSGDISC

Bit 1: TXMSGDISC.

Allowed values:
0: NotDiscarded: No Tx message discarded
1: Discarded: Tx message discarded

TXMSGSENT

Bit 2: TXMSGSENT.

Allowed values:
0: NotCompleted: No Tx message completed
1: Completed: Tx message completed

TXMSGABT

Bit 3: TXMSGABT.

Allowed values:
0: NoAbort: No transmit message abort
1: Abort: Transmit message abort

HRSTDISC

Bit 4: HRSTDISC.

Allowed values:
0: NotDiscarded: No Hard Reset discarded
1: Discarded: Hard Reset discarded

HRSTSENT

Bit 5: HRSTSENT.

Allowed values:
0: NotSent: No Hard Reset message sent
1: Sent: Hard Reset message sent

TXUND

Bit 6: TXUND.

Allowed values:
0: NoUnderrun: No Tx data underrun detected
1: Underrun: Tx data underrun detected

RXNE

Bit 8: RXNE.

Allowed values:
0: Empty: Rx data register empty
1: NotEmpty: Rx data register not empty

RXORDDET

Bit 9: RXORDDET.

Allowed values:
0: NoOrderedSet: No ordered set detected
1: OrderedSet: Ordered set detected

RXHRSTDET

Bit 10: RXHRSTDET.

Allowed values:
0: NoHardReset: Hard Reset not received
1: HardReset: Hard Reset received

RXOVR

Bit 11: RXOVR.

Allowed values:
0: NoOverflow: No overflow
1: Overflow: Overflow

RXMSGEND

Bit 12: RXMSGEND.

Allowed values:
0: NoNewMessage: No new Rx message received
1: NewMessage: A new Rx message received

RXERR

Bit 13: RXERR.

Allowed values:
0: NoError: No error detected
1: Error: Error(s) detected

TYPECEVT1

Bit 14: TYPECEVT1.

Allowed values:
0: NoNewEvent: No new event
1: NewEvent: A new Type-C event occurred

TYPECEVT2

Bit 15: TYPECEVT2.

Allowed values:
0: NoNewEvent: No new event
1: NewEvent: A new Type-C event occurred

TYPEC_VSTATE_CC1

Bits 16-17: TYPEC_VSTATE_CC1.

Allowed values:
0: Lowest: Lowest
1: Low: Low
2: High: High
3: Highest: Highest

TYPEC_VSTATE_CC2

Bits 18-19: TYPEC_VSTATE_CC2.

Allowed values:
0: Lowest: Lowest
1: Low: Low
2: High: High
3: Highest: Highest

FRSEVT

Bit 20: FRSEVT.

Allowed values:
0: NoNewEvent: No new event
1: NewEvent: New FRS receive event occurred

ICR

UCPD Interrupt Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2CF
rw
TYPECEVT1CF
rw
RXMSGENDCF
rw
RXOVRCF
rw
RXHRSTDETCF
rw
RXORDDETCF
rw
TXUNDCF
rw
HRSTSENTCF
rw
HRSTDISCCF
rw
TXMSGABTCF
rw
TXMSGSENTCF
rw
TXMSGDISCCF
rw
Toggle fields

TXMSGDISCCF

Bit 1: TXMSGDISCCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TXMSGSENTCF

Bit 2: TXMSGSENTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TXMSGABTCF

Bit 3: TXMSGABTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

HRSTDISCCF

Bit 4: HRSTDISCCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

HRSTSENTCF

Bit 5: HRSTSENTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TXUNDCF

Bit 6: TXUNDCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXORDDETCF

Bit 9: RXORDDETCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXHRSTDETCF

Bit 10: RXHRSTDETCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXOVRCF

Bit 11: RXOVRCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXMSGENDCF

Bit 12: RXMSGENDCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TYPECEVT1CF

Bit 14: TYPECEVT1CF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TYPECEVT2CF

Bit 15: TYPECEVT2CF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

FRSEVTCF

Bit 20: FRSEVTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TX_ORDSETR

UCPD Tx Ordered Set Type Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXORDSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXORDSET
rw
Toggle fields

TXORDSET

Bits 0-19: TXORDSET.

Allowed values: 0x0-0xfffff

TX_PAYSZR

UCPD Tx Paysize Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPAYSZ
rw
Toggle fields

TXPAYSZ

Bits 0-9: TXPAYSZ.

Allowed values: 0x0-0x3ff

TXDR

UCPD Tx Data Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

Allowed values: 0x0-0xff

RX_ORDSETR

UCPD Rx Ordered Set Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPKINVALID
r
RXSOP3OF4
r
RXORDSET
r
Toggle fields

RXORDSET

Bits 0-2: RXORDSET.

Allowed values:
0: SOP: SOP code detected in receiver
1: SOPPrime: SOP' code detected in receiver
2: SOPDoublePrime: SOP'' code detected in receiver
3: SOPPrimeDebug: SOP'_Debug detected in receiver
4: SOPDoublePrimeDebug: SOP''_Debug detected in receiver
5: CableReset: Cable Reset detected in receiver
6: SOPExtension1: SOP extension #1 detected in receiver
7: SOPExtension2: SOP extension #2 detected in receiver

RXSOP3OF4

Bit 3: RXSOP3OF4.

Allowed values:
0: AllCorrect: 4 correct K-codes out of 4
1: OneIncorrect: 3 correct K-codes out of 4

RXSOPKINVALID

Bits 4-6: RXSOPKINVALID.

Allowed values:
0: Valid: No K-code corrupted
1: FirstCorrupted: First K-code corrupted
2: SecondCorrupted: Second K-code corrupted
3: ThirdCorrupted: Third K-code corrupted
4: FourthCorrupted: Fourth K-code corrupted

RX_PAYSZR

UCPD Rx Paysize Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPAYSZ
r
Toggle fields

RXPAYSZ

Bits 0-9: RXPAYSZ.

Allowed values: 0x0-0x3ff

RXDR

UCPD Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

Allowed values: 0x0-0xff

RX_ORDEXTR1

UCPD Rx Ordered Set Extension Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX1
rw
Toggle fields

RXSOPX1

Bits 0-19: RXSOPX1.

Allowed values: 0x0-0xfffff

RX_ORDEXTR2

UCPD Rx Ordered Set Extension Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX2
rw
Toggle fields

RXSOPX2

Bits 0-19: RXSOPX2.

Allowed values: 0x0-0xfffff

SEC_USART1

0x50013800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

SEC_USART2

0x50004400: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

SEC_USART3

0x50004800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

SEC_USB

0x5000d400: Universal serial bus full-speed device interface

8/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) EP[0]R
0x4 (16-bit) EP[1]R
0x8 (16-bit) EP[2]R
0xc (16-bit) EP[3]R
0x10 (16-bit) EP[4]R
0x14 (16-bit) EP[5]R
0x18 (16-bit) EP[6]R
0x1c (16-bit) EP[7]R
0x40 (16-bit) CNTR
0x44 (16-bit) ISTR
0x48 (16-bit) FNR
0x4c (16-bit) DADDR
0x50 (16-bit) BTABLE
0x54 (16-bit) LPMCSR
0x58 (16-bit) BCDR
Toggle registers

EP[0]R

endpoint 0 register

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[1]R

endpoint 1 register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[2]R

endpoint 2 register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[3]R

endpoint 3 register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[4]R

endpoint 4 register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[5]R

endpoint 5 register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[6]R

endpoint 6 register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[7]R

endpoint 7 register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 16, reset: 0x00000003, access: read-write

0/15 fields covered.

Toggle fields

FRES

Bit 0: Force USB Reset.

PDWN

Bit 1: Power down.

LPMODE

Bit 2: Low-power mode.

FSUSP

Bit 3: Force suspend.

RESUME

Bit 4: Resume request.

L1RESUME

Bit 5: LPM L1 Resume request.

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RESETM

Bit 10: USB reset interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

ISTR

interrupt status register

Offset: 0x44, size: 16, reset: 0x00000000, access: Unspecified

3/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
r
PMAOVR
rw
ERR
rw
WKUP
rw
SUSP
rw
RESET
rw
SOF
rw
ESOF
rw
L1REQ
rw
DIR
r
EP_ID
r
Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 state request.

ESOF

Bit 8: Expected start frame.

SOF

Bit 9: start of frame.

RESET

Bit 10: reset request.

SUSP

Bit 11: Suspend mode request.

WKUP

Bit 12: Wakeup.

ERR

Bit 13: Error.

PMAOVR

Bit 14: Packet memory area over / underrun.

CTR

Bit 15: Correct transfer.

FNR

frame number register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r
RXDM
r
LCK
r
LSOF
r
FN
r
Toggle fields

FN

Bits 0-10: Frame number.

LSOF

Bits 11-12: Lost SOF.

LCK

Bit 13: Locked.

RXDM

Bit 14: Receive data - line status.

RXDP

Bit 15: Receive data + line status.

DADDR

device address

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw
ADD
rw
Toggle fields

ADD

Bits 0-6: Device address.

EF

Bit 7: Enable function.

BTABLE

Buffer table address

Offset: 0x50, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle fields

BTABLE

Bits 3-15: Buffer table.

LPMCSR

LPM control and status register

Offset: 0x54, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BESL
rw
REMWAKE
rw
LPMACK
rw
LPMEN
rw
Toggle fields

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM Token acknowledge enable.

REMWAKE

Bit 3: RemoteWake value.

BESL

Bits 4-7: BESL value.

BCDR

Battery charging detector

Offset: 0x58, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPPU
rw
PS2DET
rw
SDET
rw
PDET
rw
DCDET
rw
SDEN
rw
PDEN
rw
DCDEN
rw
BCDEN
rw
Toggle fields

BCDEN

Bit 0: Battery charging detector (BCD) enable.

DCDEN

Bit 1: Data contact detection (DCD) mode enable.

PDEN

Bit 2: Primary detection (PD) mode enable.

SDEN

Bit 3: Secondary detection (SD) mode enable.

DCDET

Bit 4: Data contact detection (DCD) status.

PDET

Bit 5: Primary detection (PD) status.

SDET

Bit 6: Secondary detection (SD) status.

PS2DET

Bit 7: DM pull-up detection status.

DPPU

Bit 15: DP pull-up control.

SEC_VREFBUF

0x50010030: Voltage reference buffer

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r
VRS
rw
HIZ
rw
ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code.

SEC_WWDG

0x50002c00: System window watchdog

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR
0x4 (16-bit) CFR
0x8 (16-bit) SR
Toggle registers

CR

Control register

Offset: 0x0, size: 16, reset: 0x0000007F, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 16, reset: 0x0000007F, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw
WDGTB
rw
W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

WDGTB

Bits 7-8: Timer base.

EWI

Bit 9: Early wakeup interrupt.

SR

Status register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: Early wakeup interrupt flag.

SPI1

0x40013000: Serial peripheral interface

33/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

13/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
CRCL
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
r/w0c
TXE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

SPI2

0x40003800: Serial peripheral interface

33/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

13/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
CRCL
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
r/w0c
TXE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

SPI3

0x40003c00: Serial peripheral interface

33/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0x8 (16-bit) SR
0xc (16-bit) DR
0xc (8-bit) DR8
0x10 (16-bit) CRCPR
0x14 (16-bit) RXCRCR
0x18 (16-bit) TXCRCR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

13/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDIMODE
rw
BIDIOE
rw
CRCEN
rw
CRCNEXT
rw
CRCL
rw
RXONLY
rw
SSM
rw
SSI
rw
LSBFIRST
rw
SPE
rw
BR
rw
MSTR
rw
CPOL
rw
CPHA
rw
Toggle fields

CPHA

Bit 0: Clock phase.

Allowed values:
0: FirstEdge: The first clock transition is the first data capture edge
1: SecondEdge: The second clock transition is the first data capture edge

CPOL

Bit 1: Clock polarity.

Allowed values:
0: IdleLow: CK to 0 when idle
1: IdleHigh: CK to 1 when idle

MSTR

Bit 2: Master selection.

Allowed values:
0: Slave: Slave configuration
1: Master: Master configuration

BR

Bits 3-5: Baud rate control.

Allowed values:
0: Div2: f_PCLK / 2
1: Div4: f_PCLK / 4
2: Div8: f_PCLK / 8
3: Div16: f_PCLK / 16
4: Div32: f_PCLK / 32
5: Div64: f_PCLK / 64
6: Div128: f_PCLK / 128
7: Div256: f_PCLK / 256

SPE

Bit 6: SPI enable.

Allowed values:
0: Disabled: Peripheral disabled
1: Enabled: Peripheral enabled

LSBFIRST

Bit 7: Frame format.

Allowed values:
0: MSBFirst: Data is transmitted/received with the MSB first
1: LSBFirst: Data is transmitted/received with the LSB first

SSI

Bit 8: Internal slave select.

Allowed values:
0: SlaveSelected: 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored
1: SlaveNotSelected: 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored

SSM

Bit 9: Software slave management.

Allowed values:
0: Disabled: Software slave management disabled
1: Enabled: Software slave management enabled

RXONLY

Bit 10: Receive only.

Allowed values:
0: FullDuplex: Full duplex (Transmit and receive)
1: OutputDisabled: Output disabled (Receive-only mode)

CRCL

Bit 11: CRC length.

CRCNEXT

Bit 12: CRC transfer next.

Allowed values:
0: TxBuffer: Next transmit value is from Tx buffer
1: CRC: Next transmit value is from Tx CRC register

CRCEN

Bit 13: Hardware CRC calculation enable.

Allowed values:
0: Disabled: CRC calculation disabled
1: Enabled: CRC calculation enabled

BIDIOE

Bit 14: Output enable in bidirectional mode.

Allowed values:
0: OutputDisabled: Output disabled (receive-only mode)
1: OutputEnabled: Output enabled (transmit-only mode)

BIDIMODE

Bit 15: Bidirectional data mode enable.

Allowed values:
0: Unidirectional: 2-line unidirectional data mode selected
1: Bidirectional: 1-line bidirectional data mode selected

CR2

control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

6/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LDMA_TX
rw
LDMA_RX
rw
FRXTH
rw
DS
rw
TXEIE
rw
RXNEIE
rw
ERRIE
rw
FRF
rw
NSSP
rw
SSOE
rw
TXDMAEN
rw
RXDMAEN
rw
Toggle fields

RXDMAEN

Bit 0: Rx buffer DMA enable.

Allowed values:
0: Disabled: Rx buffer DMA disabled
1: Enabled: Rx buffer DMA enabled

TXDMAEN

Bit 1: Tx buffer DMA enable.

Allowed values:
0: Disabled: Tx buffer DMA disabled
1: Enabled: Tx buffer DMA enabled

SSOE

Bit 2: SS output enable.

Allowed values:
0: Disabled: SS output is disabled in master mode
1: Enabled: SS output is enabled in master mode

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

Allowed values:
0: Masked: Error interrupt masked
1: NotMasked: Error interrupt not masked

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

Allowed values:
0: Masked: RXE interrupt masked
1: NotMasked: RXE interrupt not masked

TXEIE

Bit 7: Tx buffer empty interrupt enable.

Allowed values:
0: Masked: TXE interrupt masked
1: NotMasked: TXE interrupt not masked

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, size: 16, reset: 0x00000002, access: Unspecified

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTLVL
r
FRLVL
r
TIFRFE
r
BSY
r
OVR
r
MODF
r
CRCERR
r/w0c
TXE
r
RXNE
r
Toggle fields

RXNE

Bit 0: Receive buffer not empty.

Allowed values:
0: Empty: Rx buffer empty
1: NotEmpty: Rx buffer not empty

TXE

Bit 1: Transmit buffer empty.

Allowed values:
0: NotEmpty: Tx buffer not empty
1: Empty: Tx buffer empty

CRCERR

Bit 4: CRC error flag.

Allowed values:
0: Match: CRC value received matches the SPIx_RXCRCR value
1: NoMatch: CRC value received does not match the SPIx_RXCRCR value

MODF

Bit 5: Mode fault.

Allowed values:
0: NoFault: No mode fault occurred
1: Fault: Mode fault occurred

OVR

Bit 6: Overrun flag.

Allowed values:
0: NoOverrun: No overrun occurred
1: Overrun: Overrun occurred

BSY

Bit 7: Busy flag.

Allowed values:
0: NotBusy: SPI not busy
1: Busy: SPI busy

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-15: Data register.

Allowed values: 0x0-0xffff

DR8

Direct 8-bit access to data register

Offset: 0xc, size: 8, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-7: Data register.

Allowed values: 0x0-0xff

CRCPR

CRC polynomial register

Offset: 0x10, size: 16, reset: 0x00000007, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-15: CRC polynomial register.

Allowed values: 0x0-0xffff

RXCRCR

RX CRC register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCRC
r
Toggle fields

RxCRC

Bits 0-15: Rx CRC register.

Allowed values: 0x0-0xffff

TXCRCR

TX CRC register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TxCRC
r
Toggle fields

TxCRC

Bits 0-15: Tx CRC register.

Allowed values: 0x0-0xffff

SYSCFG

0x40010000: System configuration controller

1/93 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SECCFGR
0x4 CFGR1
0x8 FPUIMR
0xc CNSLCKR
0x10 CSLOCKR
0x14 CFGR2
0x18 SCSR
0x1c SKR
0x20 SWPR
0x24 SWPR2
0x2c RSSCMDR
Toggle registers

SECCFGR

SYSCFG secure configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPUSEC
rw
SRAM2SEC
rw
CLASSBSEC
rw
SYSCFGSEC
rw
Toggle fields

SYSCFGSEC

Bit 0: SYSCFG clock control security.

CLASSBSEC

Bit 1: ClassB security.

SRAM2SEC

Bit 2: SRAM2 security.

FPUSEC

Bit 3: FPUSEC.

CFGR1

configuration register 1

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C4_FMP
rw
I2C3_FMP
rw
I2C2_FMP
rw
I2C1_FMP
rw
I2C_PB9_FMP
rw
I2C_PB8_FMP
rw
I2C_PB7_FMP
rw
I2C_PB6_FMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANASWVDD
rw
BOOSTEN
rw
Toggle fields

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

ANASWVDD

Bit 9: GPIO analog switch control voltage selection.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C2_FMP

Bit 21: I2C2 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

I2C4_FMP

Bit 23: I2C4_FMP.

FPUIMR

FPU interrupt mask register

Offset: 0x8, size: 32, reset: 0x0000001F, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPU_IE
rw
Toggle fields

FPU_IE

Bits 0-5: Floating point unit interrupts enable bits.

CNSLCKR

SYSCFG CPU non-secure lock register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKNSMPU
rw
LOCKNSVTOR
rw
Toggle fields

LOCKNSVTOR

Bit 0: VTOR_NS register lock.

LOCKNSMPU

Bit 1: Non-secure MPU registers lock.

CSLOCKR

SYSCFG CPU secure lock register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKSAU
rw
LOCKSMPU
rw
LOCKSVTAIRCR
rw
Toggle fields

LOCKSVTAIRCR

Bit 0: LOCKSVTAIRCR.

LOCKSMPU

Bit 1: LOCKSMPU.

LOCKSAU

Bit 2: LOCKSAU.

CFGR2

CFGR2

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPF
rw
ECCL
w
PVDL
w
SPL
w
CLL
w
Toggle fields

CLL

Bit 0: LOCKUP (hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SCSR

SCSR

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2BSY
r
SRAM2ER
rw
Toggle fields

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

SKR

SKR

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: SRAM2 write protection key for software erase.

SWPR

SWPR

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

Toggle fields

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SWPR2

SWPR2

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

Toggle fields

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: P63WP.

RSSCMDR

RSSCMDR

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSSCMD
rw
Toggle fields

RSSCMD

Bits 0-7: RSS commands.

TAMP

0x40003400: Tamper and backup registers

43/177 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc FLTCR
0x10 ATCR1
0x14 ATSEEDR
0x18 ATOR
0x1c ATCR2
0x20 SMCR
0x24 PRIVCR
0x2c IER
0x30 SR
0x34 MISR
0x38 SMISR
0x3c SCR
0x40 COUNTR
0x50 CFGR
0x100 BKP[0]R
0x104 BKP[1]R
0x108 BKP[2]R
0x10c BKP[3]R
0x110 BKP[4]R
0x114 BKP[5]R
0x118 BKP[6]R
0x11c BKP[7]R
0x120 BKP[8]R
0x124 BKP[9]R
0x128 BKP[10]R
0x12c BKP[11]R
0x130 BKP[12]R
0x134 BKP[13]R
0x138 BKP[14]R
0x13c BKP[15]R
0x140 BKP[16]R
0x144 BKP[17]R
0x148 BKP[18]R
0x14c BKP[19]R
0x150 BKP[20]R
0x154 BKP[21]R
0x158 BKP[22]R
0x15c BKP[23]R
0x160 BKP[24]R
0x164 BKP[25]R
0x168 BKP[26]R
0x16c BKP[27]R
0x170 BKP[28]R
0x174 BKP[29]R
0x178 BKP[30]R
0x17c BKP[31]R
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw
ITAMP5E
rw
ITAMP3E
rw
ITAMP2E
rw
ITAMP1E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8E
rw
TAMP7E
rw
TAMP6E
rw
TAMP5E
rw
TAMP4E
rw
TAMP3E
rw
TAMP2E
rw
TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

TAMP4E

Bit 3: TAMP4E.

TAMP5E

Bit 4: TAMP5E.

TAMP6E

Bit 5: TAMP6E.

TAMP7E

Bit 6: TAMP7E.

TAMP8E

Bit 7: TAMP8E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP8E

Bit 23: ITAMP5E.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP4NOER

Bit 3: TAMP4NOER.

TAMP5NOER

Bit 4: TAMP5NOER.

TAMP6NOER

Bit 5: TAMP6NOER.

TAMP7NOER

Bit 6: TAMP7NOER.

TAMP8NOER

Bit 7: TAMP8NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

BKERASE

Bit 23: BKERASE.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

TAMP4TRG

Bit 27: TAMP4TRG.

TAMP5TRG

Bit 28: TAMP5TRG.

TAMP6TRG

Bit 29: TAMP6TRG.

TAMP7TRG

Bit 30: TAMP7TRG.

TAMP8TRG

Bit 31: TAMP8TRG.

CR3

control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITAMP8NOER
rw
ITAMP5NOER
rw
ITAMP3NOER
rw
ITAMP2NOER
rw
ITAMP1NOER
rw
Toggle fields

ITAMP1NOER

Bit 0: ITAMP1NOER.

ITAMP2NOER

Bit 1: ITAMP2NOER.

ITAMP3NOER

Bit 2: ITAMP3NOER.

ITAMP5NOER

Bit 4: ITAMP5NOER.

ITAMP8NOER

Bit 7: ITAMP8NOER.

FLTCR

TAMP filter control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw
TAMPPRCH
rw
TAMPFLT
rw
TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

TAMP active tamper control register 1

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTEN
rw
ATOSHARE
rw
ATPER
rw
ATCKSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL4
rw
ATOSEL3
rw
ATOSEL2
rw
ATOSEL1
rw
TAMP8AM
rw
TAMP7AM
rw
TAMP6AM
rw
TAMP5AM
rw
TAMP4AM
rw
TAMP3AM
rw
TAMP2AM
rw
TAMP1AM
rw
Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

TAMP4AM

Bit 3: TAMP4AM.

TAMP5AM

Bit 4: TAMP5AM.

TAMP6AM

Bit 5: TAMP6AM.

TAMP7AM

Bit 6: TAMP7AM.

TAMP8AM

Bit 7: TAMP8AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATOSEL4

Bits 14-15: ATOSEL4.

ATCKSEL

Bits 16-17: ATCKSEL.

ATPER

Bits 24-25: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: FLTEN.

ATSEEDR

TAMP active tamper seed register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
w
Toggle fields

SEED

Bits 0-31: Pseudo-random generator seed value.

ATOR

TAMP active tamper output register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INITS
r
SEEDF
r
PRNG
r
Toggle fields

PRNG

Bits 0-7: Pseudo-random generator value.

SEEDF

Bit 14: Seed running flag.

INITS

Bit 15: Active tamper initialization status.

ATCR2

TAMP active tamper control register 2

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATOSEL8
rw
ATOSEL7
rw
ATOSEL6
rw
ATOSEL5
rw
ATOSEL4
rw
ATOSEL3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL3
rw
ATOSEL2
rw
ATOSEL1
rw
Toggle fields

ATOSEL1

Bits 8-10: ATOSEL1.

ATOSEL2

Bits 11-13: ATOSEL2.

ATOSEL3

Bits 14-16: ATOSEL3.

ATOSEL4

Bits 17-19: ATOSEL4.

ATOSEL5

Bits 20-22: ATOSEL5.

ATOSEL6

Bits 23-25: ATOSEL6.

ATOSEL7

Bits 26-28: ATOSEL7.

ATOSEL8

Bits 29-31: ATOSEL8.

SMCR

TAMP secure mode register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPDPROT
rw
BKPWDPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPRWDPROT
rw
Toggle fields

BKPRWDPROT

Bits 0-7: Backup registers read/write protection offset.

BKPWDPROT

Bits 16-23: Backup registers write protection offset.

TAMPDPROT

Bit 31: Tamper protection.

PRIVCR

TAMP privilege mode control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPPRIV
rw
BKPWPRIV
rw
BKPRWPRIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

BKPRWPRIV

Bit 29: Backup registers zone 1 privilege protection.

BKPWPRIV

Bit 30: Backup registers zone 2 privilege protection.

TAMPPRIV

Bit 31: Tamper privilege protection.

IER

TAMP interrupt enable register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw
ITAMP5IE
rw
ITAMP3IE
rw
ITAMP2IE
rw
ITAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8IE
rw
TAMP7IE
rw
TAMP6IE
rw
TAMP5IE
rw
TAMP4IE
rw
TAMP3IE
rw
TAMP2IE
rw
TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

TAMP4IE

Bit 3: TAMP4IE.

TAMP5IE

Bit 4: TAMP5IE.

TAMP6IE

Bit 5: TAMP6IE.

TAMP7IE

Bit 6: TAMP7IE.

TAMP8IE

Bit 7: TAMP8IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP8IE

Bit 23: ITAMP8IE.

SR

TAMP status register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r
ITAMP5F
r
ITAMP3F
r
ITAMP2F
r
ITAMP1F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8F
r
TAMP7F
r
TAMP6F
r
TAMP5F
r
TAMP4F
r
TAMP3F
r
TAMP2F
r
TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

TAMP4F

Bit 3: TAMP4F.

TAMP5F

Bit 4: TAMP5F.

TAMP6F

Bit 5: TAMP6F.

TAMP7F

Bit 6: TAMP7F.

TAMP8F

Bit 7: TAMP8F.

ITAMP1F

Bit 16: ITAMP1F.

ITAMP2F

Bit 17: ITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP8F

Bit 23: ITAMP8F.

MISR

TAMP masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r
ITAMP5MF
r
ITAMP3MF
r
ITAMP2MF
r
ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r
TAMP7MF
r
TAMP6MF
r
TAMP5MF
r
TAMP4MF
r
TAMP3MF
r
TAMP2MF
r
TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r
ITAMP5MF
r
ITAMP3MF
r
ITAMP2MF
r
ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP8MF
r
TAMP7MF
r
TAMP6MF
r
TAMP5MF
r
TAMP4MF
r
TAMP3MF
r
TAMP2MF
r
TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF:.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

TAMP4MF

Bit 3: TAMP4MF.

TAMP5MF

Bit 4: TAMP5MF.

TAMP6MF

Bit 5: TAMP6MF.

TAMP7MF

Bit 6: TAMP7MF:.

TAMP8MF

Bit 7: TAMP8MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w
CITAMP5F
w
CITAMP3F
w
CITAMP2F
w
CITAMP1F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP8F
w
CTAMP7F
w
CTAMP6F
w
CTAMP5F
w
CTAMP4F
w
CTAMP3F
w
CTAMP2F
w
CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CTAMP4F

Bit 3: CTAMP4F.

CTAMP5F

Bit 4: CTAMP5F.

CTAMP6F

Bit 5: CTAMP6F.

CTAMP7F

Bit 6: CTAMP7F.

CTAMP8F

Bit 7: CTAMP8F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP8F

Bit 23: CITAMP8F.

COUNTR

TAMP monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: COUNT.

CFGR

TAMP configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUTMONEN
rw
VMONEN
rw
TMONEN
rw
Toggle fields

TMONEN

Bit 1: TMONEN.

VMONEN

Bit 2: VMONEN.

WUTMONEN

Bit 3: WUTMONEN.

BKP[0]R

TAMP backup register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

TAMP backup register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

TAMP backup register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

TAMP backup register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

TAMP backup register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

TAMP backup register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

TAMP backup register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

TAMP backup register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

TAMP backup register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

TAMP backup register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

TAMP backup register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

TAMP backup register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

TAMP backup register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

TAMP backup register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

TAMP backup register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

TAMP backup register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

TAMP backup register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

TAMP backup register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

TAMP backup register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

TAMP backup register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

TAMP backup register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

TAMP backup register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

TAMP backup register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

TAMP backup register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

TAMP backup register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

TAMP backup register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

TAMP backup register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

TAMP backup register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

TAMP backup register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

TAMP backup register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

TAMP backup register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

TAMP backup register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

TIM1

0x40012c00: Advanced-timers

153/186 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

13/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS[6]
rw
OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw
OIS[3]N
rw
OIS[3]
rw
OIS[2]N
rw
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c
CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw
CC[6]E
rw
CC[5]P
rw
CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw
CC[4]P
rw
CC[4]E
rw
CC[3]NP
rw
CC[3]NE
rw
CC[3]P
rw
CC[3]E
rw
CC[2]NP
rw
CC[2]NE
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw
BKBID
rw
BK2DSRM
rw
BKDSRM
rw
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
ETR_ADC1_RMP
rw
Toggle fields

ETR_ADC1_RMP

Bits 0-1: External trigger remap on ADC1 analog watchdog.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw
OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw
OC[6]M
rw
OC[6]PE
rw
OC[6]FE
rw
OC[5]CE
rw
OC[5]M
rw
OC[5]PE
rw
OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDFBK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDFBK0E

Bit 8: BRK DFSDM_BREAK0 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DFBK0E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM15

0x40014000: General purpose timers

74/95 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 CCR[2]
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

6/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-5: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

SMCR

TIM15 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/slave mode.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

11/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
COMDE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
TIE
rw
COMIE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
TG
w
COMG
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]M
rw
OC[2]PE
rw
CC[2]S
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved
7: PwmMode2: Inversely to PwmMode1 / Reserved

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[2]NP
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

CCR[2]

capture/compare register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM15 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENCODER_MODE
rw
TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 0: Input capture 1 remap.

ENCODER_MODE

Bits 1-2: Encoder mode.

OR2

TIM15 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK0E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK0E

Bit 8: BRK dfsdm1_break[0] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

TIM16

0x40014400: General purpose timers

51/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw
OIS[1]
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
BIF
r/w0c
COMIF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK1E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK1E

Bit 8: BRK dfsdm1_break[1] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM17

0x40014800: General purpose timers

51/67 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[1]N
rw
OIS[1]
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

6/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw
CC[1]DE
rw
UDE
rw
BIE
rw
COMIE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]OF
r/w0c
BIF
r/w0c
COMIF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w
COMG
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

4/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
7: PwmMode2: Inversely to PwmMode1

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: Repetition counter value.

Allowed values: 0x0-0xff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

8/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw
BKDSRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKDSRM

Bit 26: Break Disarm.

BKBID

Bit 28: Break Bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMA register for burst accesses.

OR1

TIM16 option register 1

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bits 0-1: Input capture 1 remap.

OR2

TIM17 option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK2E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM2

0x40000000: General-purpose-timers

96/110 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw
ETR1_RMP
rw
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

ETR1_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input Capture 4 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

TIM3

0x40000400: General-purpose-timers

97/109 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

TIM4

0x40000800: General-purpose-timers

97/109 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: Counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

TIM5

0x40000c00: General-purpose-timers

96/110 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x48 DCR
0x4c DMAR
0x50 OR1
0x60 OR2
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw
MMS
rw
CCDS
rw
Toggle fields

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw
CC[4]DE
rw
CC[3]DE
rw
CC[2]DE
rw
CC[1]DE
rw
UDE
rw
TIE
rw
CC[4]IE
rw
CC[3]IE
rw
CC[2]IE
rw
CC[1]IE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
TIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

8/12 fields covered.

Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-31: Counter value.

Allowed values: 0x0-0xffffffff

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-31: Auto-reload value.

Allowed values: 0x0-0xffffffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-31: Capture/Compare value.

Allowed values: 0x0-0xffffffff

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: Low Capture/Compare 2 value.

OR1

TIM2 option register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI4_RMP
rw
ETR1_RMP
rw
ITR1_RMP
rw
Toggle fields

ITR1_RMP

Bit 0: Internal trigger 1 remap.

ETR1_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input Capture 4 remap.

OR2

TIM3 option register 2

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
Toggle fields

ETRSEL

Bits 14-16: ETR source selection.

TIM6

0x40001000: General-purpose-timers

13/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR_bit0.

Allowed values: 0x0-0xffff

TIM7

0x40001400: General-purpose-timers

13/15 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc DIER
0x10 SR
0x14 EGR
0x24 CNT
0x28 PSC
0x2c ARR
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

5/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMA
rw
ARPE
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

UIFREMA

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MMS
rw
Toggle fields

MMS

Bits 4-6: Master mode selection.

Allowed values:
0: Reset: Use UG bit from TIMx_EGR register
1: Enable: Use CNT bit from TIMx_CEN register
2: Update: Use the update event

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDE
rw
UIE
rw
Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIFCPY or Res.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0xFFFFFFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR_bit0.

Allowed values: 0x0-0xffff

TIM8

0x40013400: Advanced-timers

153/185 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 SMCR
0xc DIER
0x10 SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x1c CCMR2_Input
0x1c CCMR2_Output
0x20 CCER
0x24 CNT
0x28 PSC
0x2c ARR
0x30 RCR
0x34 CCR[1]
0x38 CCR[2]
0x3c CCR[3]
0x40 CCR[4]
0x44 BDTR
0x48 DCR
0x4c DMAR
0x50 OR1
0x54 CCMR3_Output
0x58 CCR5
0x5c CCR6
0x60 OR2
0x64 OR3
Toggle registers

CR1

control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

8/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw
CKD
rw
ARPE
rw
CMS
rw
DIR
rw
OPM
rw
URS
rw
UDIS
rw
CEN
rw
Toggle fields

CEN

Bit 0: Counter enable.

Allowed values:
0: Disabled: Counter disabled
1: Enabled: Counter enabled

UDIS

Bit 1: Update disable.

Allowed values:
0: Enabled: Update event enabled
1: Disabled: Update event disabled

URS

Bit 2: Update request source.

Allowed values:
0: AnyEvent: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
1: CounterOnly: Only counter overflow/underflow generates an update interrupt or DMA request

OPM

Bit 3: One-pulse mode.

Allowed values:
0: Disabled: Counter is not stopped at update event
1: Enabled: Counter stops counting at the next update event (clearing the CEN bit)

DIR

Bit 4: Direction.

Allowed values:
0: Up: Counter used as upcounter
1: Down: Counter used as downcounter

CMS

Bits 5-6: Center-aligned mode selection.

Allowed values:
0: EdgeAligned: The counter counts up or down depending on the direction bit
1: CenterAligned1: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.
2: CenterAligned2: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.
3: CenterAligned3: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.

ARPE

Bit 7: Auto-reload preload enable.

Allowed values:
0: Disabled: TIMx_APRR register is not buffered
1: Enabled: TIMx_APRR register is buffered

CKD

Bits 8-9: Clock division.

Allowed values:
0: Div1: t_DTS = t_CK_INT
1: Div2: t_DTS = 2 × t_CK_INT
2: Div4: t_DTS = 4 × t_CK_INT

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

13/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw
OIS[6]
rw
OIS[5]
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS[4]
rw
OIS[3]N
rw
OIS[3]
rw
OIS[2]N
rw
OIS[2]
rw
OIS[1]N
rw
OIS[1]
rw
TI1S
rw
MMS
rw
CCDS
rw
CCUS
rw
CCPC
rw
Toggle fields

CCPC

Bit 0: Capture/compare preloaded control.

Allowed values:
0: NotPreloaded: CCxE, CCxNE and OCxM bits are not preloaded
1: Preloaded: CCxE, CCxNE and OCxM bits are preloaded

CCUS

Bit 2: Capture/compare control update selection.

Allowed values:
0: Sw: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
1: SwOrEdge: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI

CCDS

Bit 3: Capture/compare DMA selection.

Allowed values:
0: OnCompare: CCx DMA request sent when CCx event occurs
1: OnUpdate: CCx DMA request sent when update event occurs

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

Allowed values:
0: Normal: The TIMx_CH1 pin is connected to TI1 input
1: XOR: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input

OIS[1]

Bit 8: Output Idle state (OC1 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[1]N

Bit 9: Output Idle state (OC1N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[2]

Bit 10: Output Idle state (OC2 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[2]N

Bit 11: Output Idle state (OC2N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[3]

Bit 12: Output Idle state (OC3 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[3]N

Bit 13: Output Idle state (OC3N output).

Allowed values:
0: Reset: OCxN=0 after a dead-time when MOE=0
1: Set: OCxN=1 after a dead-time when MOE=0

OIS[4]

Bit 14: Output Idle state (OC4 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[5]

Bit 16: Output Idle state (OC5 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

OIS[6]

Bit 18: Output Idle state (OC6 output).

Allowed values:
0: Reset: OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0
1: Set: OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

5/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw
ECE
rw
ETPS
rw
ETF
rw
MSM
rw
TS
rw
SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

Allowed values:
0: NoSync: No action
1: Sync: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.

ETF

Bits 8-11: External trigger filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

ETPS

Bits 12-13: External trigger prescaler.

Allowed values:
0: Div1: Prescaler OFF
1: Div2: ETRP frequency divided by 2
2: Div4: ETRP frequency divided by 4
3: Div8: ETRP frequency divided by 8

ECE

Bit 14: External clock enable.

Allowed values:
0: Disabled: External clock mode 2 disabled
1: Enabled: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

ETP

Bit 15: External trigger polarity.

Allowed values:
0: NotInverted: ETR is noninverted, active at high level or rising edge
1: Inverted: ETR is inverted, active at low level or falling edge

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

Toggle fields

UIE

Bit 0: Update interrupt enable.

Allowed values:
0: Disabled: Update interrupt disabled
1: Enabled: Update interrupt enabled

CC[1]IE

Bit 1: Capture/Compare 1 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[2]IE

Bit 2: Capture/Compare 2 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[3]IE

Bit 3: Capture/Compare 3 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

CC[4]IE

Bit 4: Capture/Compare 4 interrupt enable.

Allowed values:
0: Disabled: CCx interrupt disabled
1: Enabled: CCx interrupt enabled

COMIE

Bit 5: COM interrupt enable.

Allowed values:
0: Disabled: COM interrupt disabled
1: Enabled: COM interrupt enabled

TIE

Bit 6: Trigger interrupt enable.

Allowed values:
0: Disabled: Trigger interrupt disabled
1: Enabled: Trigger interrupt enabled

BIE

Bit 7: Break interrupt enable.

Allowed values:
0: Disabled: Break interrupt disabled
1: Enabled: Break interrupt enabled

UDE

Bit 8: Update DMA request enable.

Allowed values:
0: Disabled: Update DMA request disabled
1: Enabled: Update DMA request enabled

CC[1]DE

Bit 9: Capture/Compare 1 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[2]DE

Bit 10: Capture/Compare 2 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[3]DE

Bit 11: Capture/Compare 3 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

CC[4]DE

Bit 12: Capture/Compare 4 DMA request enable.

Allowed values:
0: Disabled: CCx DMA request disabled
1: Enabled: CCx DMA request enabled

COMDE

Bit 13: COM DMA request enable.

Allowed values:
0: Disabled: COM DMA request disabled
1: Enabled: COM DMA request enabled

TDE

Bit 14: Trigger DMA request enable.

Allowed values:
0: Disabled: Trigger DMA request disabled
1: Enabled: Trigger DMA request enabled

SR

status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
r/w0c
CC5IF
r/w0c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
r/w0c
CC[4]OF
r/w0c
CC[3]OF
r/w0c
CC[2]OF
r/w0c
CC[1]OF
r/w0c
BIF
r/w0c
TIF
r/w0c
COMIF
r/w0c
CC[4]IF
r/w0c
CC[3]IF
r/w0c
CC[2]IF
r/w0c
CC[1]IF
r/w0c
UIF
r/w0c
Toggle fields

UIF

Bit 0: Update interrupt flag.

Allowed values:
0: NoUpdateOccurred: No update occurred
1: UpdatePending: Update interrupt pending

CC[1]IF

Bit 1: Capture/compare 1 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[2]IF

Bit 2: Capture/compare 2 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[3]IF

Bit 3: Capture/compare 3 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC[4]IF

Bit 4: Capture/compare 4 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

COMIF

Bit 5: COM interrupt flag.

Allowed values:
0: NoCOM: No COM event occurred
1: COM: COM interrupt pending

TIF

Bit 6: Trigger interrupt flag.

Allowed values:
0: NoTrigger: No trigger event occurred
1: Trigger: Trigger interrupt pending

BIF

Bit 7: Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC[1]OF

Bit 9: Capture/Compare 1 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[2]OF

Bit 10: Capture/Compare 2 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[3]OF

Bit 11: Capture/Compare 3 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

CC[4]OF

Bit 12: Capture/Compare 4 overcapture flag.

Allowed values:
0: NoOvercapture: No overcapture has been detected
1: Overcapture: The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set

SBIF

Bit 13: System Break interrupt flag.

Allowed values:
0: NoTrigger: No break event occurred
1: Trigger: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register

CC5IF

Bit 16: Compare 5 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

CC6IF

Bit 17: Compare 6 interrupt flag.

Allowed values:
0: NoMatch: No campture/compare has been detected
1: Match: If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

9/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w
BG
w
TG
w
COMG
w
CC[4]G
w
CC[3]G
w
CC[2]G
w
CC[1]G
w
UG
w
Toggle fields

UG

Bit 0: Update generation.

Allowed values:
1: Update: Re-initializes the timer counter and generates an update of the registers.

CC[1]G

Bit 1: Capture/compare 1 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[2]G

Bit 2: Capture/compare 2 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[3]G

Bit 3: Capture/compare 3 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

CC[4]G

Bit 4: Capture/compare 4 generation.

Allowed values:
1: Trigger: If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.

COMG

Bit 5: Capture/Compare control update generation.

Allowed values:
1: Trigger: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated

TG

Bit 6: Trigger generation.

Allowed values:
1: Trigger: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.

BG

Bit 7: Break generation.

Allowed values:
1: Trigger: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled

B2G

Bit 8: Break 2 generation.

Allowed values:
1: Trigger: A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[2]F
rw
IC[2]PSC
rw
CC2S
rw
IC[1]F
rw
IC[1]PSC
rw
CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
1: TI1: CC1 channel is configured as input, IC1 is mapped on TI1
2: TI2: CC1 channel is configured as input, IC1 is mapped on TI2
3: TRC: CC1 channel is configured as input, IC1 is mapped on TRC

IC[1]PSC

Bits 2-3: Input capture 1 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[1]F

Bits 4-7: Input capture 1 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC2S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
1: TI2: CC2 channel is configured as input, IC2 is mapped on TI2
2: TI1: CC2 channel is configured as input, IC2 is mapped on TI1
3: TRC: CC2 channel is configured as input, IC2 is mapped on TRC

IC[2]PSC

Bits 10-11: Input capture 2 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[2]F

Bits 12-15: Input capture 2 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[2]M_3
rw
OC[1]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[2]CE
rw
OC[2]M
rw
OC[2]PE
rw
OC[2]FE
rw
CC[2]S
rw
OC[1]CE
rw
OC[1]M
rw
OC[1]PE
rw
OC[1]FE
rw
CC[1]S
rw
Toggle fields

CC[1]S

Bits 0-1: Capture/Compare 1 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[1]FE

Bit 2: Output compare 1 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[1]PE

Bit 3: Output compare 1 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[1]M

Bits 4-6: Output compare 1 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[1]CE

Bit 7: Output compare 1 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[2]S

Bits 8-9: Capture/Compare 2 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[2]FE

Bit 10: Output compare 2 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[2]PE

Bit 11: Output compare 2 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[2]M

Bits 12-14: Output compare 2 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[2]CE

Bit 15: Output compare 2 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[1]M_3

Bit 16: Output compare 1 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[2]M_3

Bit 24: Output compare 2 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC[4]F
rw
IC[4]PSC
rw
CC4S
rw
IC[3]F
rw
IC[3]PSC
rw
CC3S
rw
Toggle fields

CC3S

Bits 0-1: Capture/compare 3 selection.

Allowed values:
1: TI3: CC3 channel is configured as input, IC3 is mapped on TI3
2: TI4: CC3 channel is configured as input, IC3 is mapped on TI4
3: TRC: CC3 channel is configured as input, IC3 is mapped on TRC

IC[3]PSC

Bits 2-3: Input capture 3 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[3]F

Bits 4-7: Input capture 3 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CC4S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
1: TI4: CC4 channel is configured as input, IC4 is mapped on TI4
2: TI3: CC4 channel is configured as input, IC4 is mapped on TI3
3: TRC: CC4 channel is configured as input, IC4 is mapped on TRC

IC[4]PSC

Bits 10-11: Input capture 4 prescaler.

Allowed values:
0: NoPrescaler: No prescaler, capture is done each time an edge is detected on the capture input
1: TwoEvents: Capture is done once every 2 events
2: FourEvents: Capture is done once every 4 events
3: EightEvents: Capture is done once every 8 events

IC[4]F

Bits 12-15: Input capture 4 filter.

Allowed values:
0: NoFilter: No filter, sampling is done at fDTS
1: FCK_INT_N2: fSAMPLING=fCK_INT, N=2
2: FCK_INT_N4: fSAMPLING=fCK_INT, N=4
3: FCK_INT_N8: fSAMPLING=fCK_INT, N=8
4: FDTS_Div2_N6: fSAMPLING=fDTS/2, N=6
5: FDTS_Div2_N8: fSAMPLING=fDTS/2, N=8
6: FDTS_Div4_N6: fSAMPLING=fDTS/4, N=6
7: FDTS_Div4_N8: fSAMPLING=fDTS/4, N=8
8: FDTS_Div8_N6: fSAMPLING=fDTS/8, N=6
9: FDTS_Div8_N8: fSAMPLING=fDTS/8, N=8
10: FDTS_Div16_N5: fSAMPLING=fDTS/16, N=5
11: FDTS_Div16_N6: fSAMPLING=fDTS/16, N=6
12: FDTS_Div16_N8: fSAMPLING=fDTS/16, N=8
13: FDTS_Div32_N5: fSAMPLING=fDTS/32, N=5
14: FDTS_Div32_N6: fSAMPLING=fDTS/32, N=6
15: FDTS_Div32_N8: fSAMPLING=fDTS/32, N=8

CCMR2_Output

capture/compare mode register 2 (output mode)

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

12/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[4]M_3
rw
OC[3]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[4]CE
rw
OC[4]M
rw
OC[4]PE
rw
OC[4]FE
rw
CC[4]S
rw
OC[3]CE
rw
OC[3]M
rw
OC[3]PE
rw
OC[3]FE
rw
CC[3]S
rw
Toggle fields

CC[3]S

Bits 0-1: Capture/Compare 3 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[3]FE

Bit 2: Output compare 3 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[3]PE

Bit 3: Output compare 3 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[3]M

Bits 4-6: Output compare 3 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[3]CE

Bit 7: Output compare 3 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

CC[4]S

Bits 8-9: Capture/Compare 4 selection.

Allowed values:
0: Output: CCx channel is configured as output

OC[4]FE

Bit 10: Output compare 4 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[4]PE

Bit 11: Output compare 4 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[4]M

Bits 12-14: Output compare 4 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[4]CE

Bit 15: Output compare 4 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[3]M_3

Bit 16: Output compare 3 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[4]M_3

Bit 24: Output compare 4 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCER

capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

19/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC[6]P
rw
CC[6]E
rw
CC[5]P
rw
CC[5]E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC[4]NP
rw
CC[4]P
rw
CC[4]E
rw
CC[3]NP
rw
CC[3]NE
rw
CC[3]P
rw
CC[3]E
rw
CC[2]NP
rw
CC[2]NE
rw
CC[2]P
rw
CC[2]E
rw
CC[1]NP
rw
CC[1]NE
rw
CC[1]P
rw
CC[1]E
rw
Toggle fields

CC[1]E

Bit 0: Capture/Compare 1 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[1]P

Bit 1: Capture/Compare 1 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[1]NE

Bit 2: Capture/Compare 1 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[1]NP

Bit 3: Capture/Compare 1 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[2]E

Bit 4: Capture/Compare 2 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[2]P

Bit 5: Capture/Compare 2 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[2]NE

Bit 6: Capture/Compare 2 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[2]NP

Bit 7: Capture/Compare 2 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[3]E

Bit 8: Capture/Compare 3 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[3]P

Bit 9: Capture/Compare 3 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[3]NE

Bit 10: Capture/Compare 3 complementary output enable.

Allowed values:
0: Disabled: Complementary output disabled
1: Enabled: Complementary output enabled

CC[3]NP

Bit 11: Capture/Compare 3 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[4]E

Bit 12: Capture/Compare 4 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[4]P

Bit 13: Capture/Compare 4 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[4]NP

Bit 15: Capture/Compare 4 output Polarity.

Allowed values:
0: ActiveHigh: OCxN active high
1: ActiveLow: OCxN active low

CC[5]E

Bit 16: Capture/Compare 5 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[5]P

Bit 17: Capture/Compare 5 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CC[6]E

Bit 20: Capture/Compare 6 output enable.

Allowed values:
0: Disabled: Capture disabled
1: Enabled: Capture enabled

CC[6]P

Bit 21: Capture/Compare 6 output Polarity.

Allowed values:
0: RisingEdge: Noninverted/rising edge
1: FallingEdge: Inverted/falling edge

CNT

counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: counter value.

Allowed values: 0x0-0xffff

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: Prescaler value.

Allowed values: 0x0-0xffff

ARR

auto-reload register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: Auto-reload value.

Allowed values: 0x0-0xffff

RCR

repetition counter register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: Repetition counter value.

Allowed values: 0x0-0xffff

CCR[1]

capture/compare register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[2]

capture/compare register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[3]

capture/compare register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

CCR[4]

capture/compare register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

BDTR

break and dead-time register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

10/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw
BKBID
rw
BK2DSRM
rw
BKDSRM
rw
BK2P
rw
BK2E
rw
BK2F
rw
BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw
AOE
rw
BKP
rw
BKE
rw
OSSR
rw
OSSI
rw
LOCK
rw
DTG
rw
Toggle fields

DTG

Bits 0-7: Dead-time generator setup.

Allowed values: 0x0-0xff

LOCK

Bits 8-9: Lock configuration.

Allowed values:
0: Off: No bit is write protected
1: Level1: Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written
2: Level2: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written
3: Level3: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written

OSSI

Bit 10: Off-state selection for Idle mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are forced to idle level

OSSR

Bit 11: Off-state selection for Run mode.

Allowed values:
0: HiZ: When inactive, OC/OCN outputs are disabled
1: IdleLevel: When inactive, OC/OCN outputs are enabled with their inactive level

BKE

Bit 12: Break enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BKP

Bit 13: Break polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

AOE

Bit 14: Automatic output enable.

Allowed values:
0: Manual: MOE can be set only by software
1: Automatic: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)

MOE

Bit 15: Main output enable.

Allowed values:
0: DisabledIdle: OC/OCN are disabled or forced idle depending on OSSI
1: Enabled: OC/OCN are enabled if CCxE/CCxNE are set

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

Allowed values:
0: Disabled: Break function x disabled
1: Enabled: Break function x enabled

BK2P

Bit 25: Break 2 polarity.

Allowed values:
0: ActiveLow: Break input BRKx is active low
1: ActiveHigh: Break input BRKx is active high

BKDSRM

Bit 26: Break Disarm.

BK2DSRM

Bit 27: Break2 Disarm.

BKBID

Bit 28: Break Bidirectional.

BK2BID

Bit 29: Break2 bidirectional.

DCR

DMA control register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw
DBA
rw
Toggle fields

DBA

Bits 0-4: DMA base address.

Allowed values: 0x0-0x1f

DBL

Bits 8-12: DMA burst length.

Allowed values: 0x0-0x12

DMAR

DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMA register for burst accesses.

OR1

DMA address for full transfer

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1_RMP
rw
Toggle fields

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC[6]M_3
rw
OC[5]M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC[6]CE
rw
OC[6]M
rw
OC[6]PE
rw
OC[6]FE
rw
OC[5]CE
rw
OC[5]M
rw
OC[5]PE
rw
OC[5]FE
rw
Toggle fields

OC[5]FE

Bit 2: Output compare 5 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[5]PE

Bit 3: Output compare 5 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[5]M

Bits 4-6: Output compare 5 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[5]CE

Bit 7: Output compare 5 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[6]FE

Bit 10: Output compare 6 fast enable.

Allowed values:
0: Disabled: Fast output disabled
1: Enabled: Fast output enabled

OC[6]PE

Bit 11: Output compare 6 preload enable.

Allowed values:
0: Disabled: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
1: Enabled: Preload register on CCRx enabled. Preload value is loaded into active register on each update event

OC[6]M

Bits 12-14: Output compare 6 mode.

Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1

OC[6]CE

Bit 15: Output compare 6 clear enable.

Allowed values:
0: Disabled: OCxRef is not affected by the ETRF signal
1: Enabled: OCxRef is cleared as soon as a High level is detected on ETRF signal

OC[5]M_3

Bit 16: Output compare 5 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

OC[6]M_3

Bit 24: Output compare 6 mode, bit 3.

Allowed values:
0: Normal: Normal output compare mode (modes 0-7)
1: Extended: Extended output compare mode (modes 7-15)

CCR5

capture/compare register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

1/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw
GC5C2
rw
GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR
rw
Toggle fields

CCR

Bits 0-15: Capture/Compare value.

Allowed values: 0x0-0xffff

OR2

DMA address for full transfer

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw
BKCMP2P
rw
BKCMP1P
rw
BKINP
rw
BKDF1BK2E
rw
BKCMP2E
rw
BKCMP1E
rw
BKINE
rw
Toggle fields

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKDF1BK2E

Bit 8: BRK dfsdm1_break[2] enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

OR3

DMA address for full transfer

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2CMP2P
rw
BK2CMP1P
rw
BK2INP
rw
BK2DFBK3E
rw
BK2CMP2E
rw
BK2CMP1E
rw
BK2INE
rw
Toggle fields

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK3E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TSC

0x40024000: Touch sensing controller

16/170 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IER
0x8 ICR
0xc ISR
0x10 IOHCR
0x18 IOASCR
0x20 IOSCR
0x28 IOCCR
0x30 IOGCSR
0x34 IOG1CR
0x38 IOG2CR
0x3c IOG3CR
0x40 IOG4CR
0x44 IOG5CR
0x48 IOG6CR
0x4c IOG7CR
0x50 IOG8CR
Toggle registers

CR

control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH
rw
CTPL
rw
SSD
rw
SSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSPSC
rw
PGPSC
rw
MCV
rw
IODEF
rw
SYNCPOL
rw
AM
rw
START
rw
TSCE
rw
Toggle fields

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIE
rw
EOAIE
rw
Toggle fields

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEIC
rw
EOAIC
rw
Toggle fields

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCEF
rw
EOAF
rw
Toggle fields

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOCCR

I/O channel control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

Toggle fields

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

G8_IO1

Bit 28: G8_IO1.

G8_IO2

Bit 29: G8_IO2.

G8_IO3

Bit 30: G8_IO3.

G8_IO4

Bit 31: G8_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, size: 32, reset: 0x00000000, access: Unspecified

8/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8S
r
G7S
r
G6S
r
G5S
r
G4S
r
G3S
r
G2S
r
G1S
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G8E
rw
G7E
rw
G6E
rw
G5E
rw
G4E
rw
G3E
rw
G2E
rw
G1E
rw
Toggle fields

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G8E

Bit 7: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

G8S

Bit 23: Analog I/O group x status.

IOG1CR

I/O group x counter register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG2CR

I/O group x counter register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG3CR

I/O group x counter register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG4CR

I/O group x counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG5CR

I/O group x counter register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG6CR

I/O group x counter register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG7CR

I/O group x counter register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

IOG8CR

I/O group x counter register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-13: Counter value.

UART4

0x40004c00: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

UART5

0x40005000: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

UCPD1

0x4000dc00: USB Power Delivery interface

96/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFGR1
0x4 CFGR2
0x8 CFGR3
0xc CR
0x10 IMR
0x14 SR
0x18 ICR
0x1c TX_ORDSETR
0x20 TX_PAYSZR
0x24 TXDR
0x28 RX_ORDSETR
0x2c RX_PAYSZR
0x30 RXDR
0x34 RX_ORDEXTR1
0x38 RX_ORDEXTR2
Toggle registers

CFGR1

UCPD configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

16/16 fields covered.

Toggle fields

HBITCLKDIV

Bits 0-5: HBITCLKDIV.

Allowed values: 0x0-0x3f

IFRGAP

Bits 6-10: IFRGAP.

Allowed values: 0x1-0x1f

TRANSWIN

Bits 11-15: TRANSWIN.

Allowed values: 0x1-0x1f

PSC_USBPDCLK

Bits 17-19: PSC_USBPDCLK.

Allowed values:
0: Div1: Divide by 1
1: Div2: Divide by 2
2: Div4: Divide by 4
3: Div8: Divide by 8
4: Div16: Divide by 16

RXORDSETEN0

Bit 20: SOP detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN1

Bit 21: SOP' detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN2

Bit 22: SOP'' detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN3

Bit 23: Hard Reset detection.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN4

Bit 24: Cable Detect reset.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN5

Bit 25: SOP'_Debug.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN6

Bit 26: SOP'' Debug.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN7

Bit 27: SOP extension #1.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

RXORDSETEN8

Bit 28: SOP extension #2.

Allowed values:
0: Disabled: Flag disabled
1: Enabled: Flag enabled

TXDMAEN

Bit 29: TXDMAEN.

Allowed values:
0: Disabled: DMA mode for transmission disabled
1: Enabled: DMA mode for transmission enabled

RXDMAEN

Bit 30: RXDMAEN:.

Allowed values:
0: Disabled: DMA mode for reception disabled
1: Enabled: DMA mode for reception enabled

UCPDEN

Bit 31: UCPDEN.

Allowed values:
0: Disabled: UCPD peripheral disabled
1: Enabled: UCPD peripheral enabled

CFGR2

UCPD configuration register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUPEN
rw
FORCECLK
rw
RXFILT2N3
rw
RXFILTDIS
rw
Toggle fields

RXFILTDIS

Bit 0: RXFILTDIS.

Allowed values:
0: Enabled: Rx pre-filter enabled
1: Disabled: Rx pre-filter disabled

RXFILT2N3

Bit 1: RXFILT2N3.

Allowed values:
0: Samp3: 3 samples
1: Samp2: 2 samples

FORCECLK

Bit 2: FORCECLK.

Allowed values:
0: NoForce: Do not force clock request
1: Force: Force clock request

WUPEN

Bit 3: WUPEN.

Allowed values:
0: Disabled: Disabled
1: Enabled: Enabled

CFGR3

UCPD configuration register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRIM2_NG_CC3A0
rw
TRIM2_NG_CC1A5
rw
TRIM2_NG_CCRPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM1_NG_CC3A0
rw
TRIM1_NG_CC1A5
rw
TRIM1_NG_CCRPD
rw
Toggle fields

TRIM1_NG_CCRPD

Bits 0-3: TRIM1_NG_CCRPD.

Allowed values: 0x0-0xf

TRIM1_NG_CC1A5

Bits 4-8: TRIM1_NG_CC1A5.

Allowed values: 0x0-0xf

TRIM1_NG_CC3A0

Bits 9-12: TRIM1_NG_CC3A0.

Allowed values: 0x0-0xf

TRIM2_NG_CCRPD

Bits 16-19: TRIM2_NG_CCRPD.

Allowed values: 0x0-0xf

TRIM2_NG_CC1A5

Bits 20-24: TRIM2_NG_CC1A5.

Allowed values: 0x0-0xf

TRIM2_NG_CC3A0

Bits 25-28: TRIM2_NG_CC3A0.

Allowed values: 0x0-0xf

CR

UCPD control register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC2TCDIS
rw
CC1TCDIS
rw
RDCH
rw
FRSTX
rw
FRSRXEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCENABLE
rw
ANAMODE
rw
ANASUBMODE
rw
PHYCCSEL
rw
PHYRXEN
rw
RXMODE
rw
TXHRST
rw
TXSEND
rw
TXMODE
rw
Toggle fields

TXMODE

Bits 0-1: TXMODE.

Allowed values:
0: RegisterSet: Transmission of Tx packet previously defined in other registers
1: CableReset: Cable Reset sequence
2: BISTTest: BIST test sequence (BIST Carrier Mode 2)

TXSEND

Bit 2: TXSEND.

Allowed values:
0: NoEffect: No effect
1: Start: Start Tx packet transmission

TXHRST

Bit 3: TXHRST.

Allowed values:
0: NoEffect: No effect
1: Start: Start Tx Hard Reset message

RXMODE

Bit 4: RXMODE.

Allowed values:
0: Normal: Normal receive mode
1: BIST: BIST receive mode (BIST test data mode)

PHYRXEN

Bit 5: PHYRXEN.

Allowed values:
0: Disabled: USB Power Delivery receiver disabled
1: Enabled: USB Power Delivery receiver enabled

PHYCCSEL

Bit 6: PHYCCSEL.

Allowed values:
0: CC1: Use CC1 IO for Power Delivery communication
1: CC2: Use CC2 IO for Power Delivery communication

ANASUBMODE

Bits 7-8: ANASUBMODE.

Allowed values:
0: Disabled: Disabled
1: Rp_DefaultUSB: Default USB Rp
2: Rp_1_5A: 1.5A Rp
3: Rp_3A: 3A Rp

ANAMODE

Bit 9: ANAMODE.

Allowed values:
0: Source: Source
1: Sink: Sink

CCENABLE

Bits 10-11: CCENABLE.

Allowed values:
0: Disabled: Both PHYs disabled
1: CC1Enabled: CC1 PHY enabled
2: CC2Enabled: CC2 PHY enabled
3: BothEnabled: CC1 and CC2 PHYs enabled

FRSRXEN

Bit 16: FRSRXEN.

Allowed values:
0: Disabled: FRS Rx event detection disabled
1: Enabled: FRS Rx event detection enabled

FRSTX

Bit 17: FRSTX.

Allowed values:
0: NoEffect: No effect
1: Enabled: FRS Tx signaling enabled

RDCH

Bit 18: RDCH.

Allowed values:
0: NoEffect: No effect
1: ConditionDrive: Rdch condition drive

CC1TCDIS

Bit 20: CC1TCDIS.

Allowed values:
0: Enabled: Type-C detector on the CCx line enabled
1: Disabled: Type-C detector on the CCx line disabled

CC2TCDIS

Bit 21: CC2TCDIS.

Allowed values:
0: Enabled: Type-C detector on the CCx line enabled
1: Disabled: Type-C detector on the CCx line disabled

IMR

UCPD Interrupt Mask Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2IE
rw
TYPECEVT1IE
rw
RXMSGENDIE
rw
RXOVRIE
rw
RXHRSTDETIE
rw
RXORDDETIE
rw
RXNEIE
rw
TXUNDIE
rw
HRSTSENTIE
rw
HRSTDISCIE
rw
TXMSGABTIE
rw
TXMSGSENTIE
rw
TXMSGDISCIE
rw
TXISIE
rw
Toggle fields

TXISIE

Bit 0: TXISIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXMSGDISCIE

Bit 1: TXMSGDISCIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXMSGSENTIE

Bit 2: TXMSGSENTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXMSGABTIE

Bit 3: TXMSGABTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HRSTDISCIE

Bit 4: HRSTDISCIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

HRSTSENTIE

Bit 5: HRSTSENTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TXUNDIE

Bit 6: TXUNDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXNEIE

Bit 8: RXNEIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXORDDETIE

Bit 9: RXORDDETIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXHRSTDETIE

Bit 10: RXHRSTDETIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXOVRIE

Bit 11: RXOVRIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

RXMSGENDIE

Bit 12: RXMSGENDIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TYPECEVT1IE

Bit 14: TYPECEVT1IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

TYPECEVT2IE

Bit 15: TYPECEVT2IE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

FRSEVTIE

Bit 20: FRSEVTIE.

Allowed values:
0: Disabled: Interrupt disabled
1: Enabled: Interrupt enabled

SR

UCPD Status Register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

18/18 fields covered.

Toggle fields

TXIS

Bit 0: TXIS.

Allowed values:
0: NotRequired: New Tx data write not required
1: Required: New Tx data write required

TXMSGDISC

Bit 1: TXMSGDISC.

Allowed values:
0: NotDiscarded: No Tx message discarded
1: Discarded: Tx message discarded

TXMSGSENT

Bit 2: TXMSGSENT.

Allowed values:
0: NotCompleted: No Tx message completed
1: Completed: Tx message completed

TXMSGABT

Bit 3: TXMSGABT.

Allowed values:
0: NoAbort: No transmit message abort
1: Abort: Transmit message abort

HRSTDISC

Bit 4: HRSTDISC.

Allowed values:
0: NotDiscarded: No Hard Reset discarded
1: Discarded: Hard Reset discarded

HRSTSENT

Bit 5: HRSTSENT.

Allowed values:
0: NotSent: No Hard Reset message sent
1: Sent: Hard Reset message sent

TXUND

Bit 6: TXUND.

Allowed values:
0: NoUnderrun: No Tx data underrun detected
1: Underrun: Tx data underrun detected

RXNE

Bit 8: RXNE.

Allowed values:
0: Empty: Rx data register empty
1: NotEmpty: Rx data register not empty

RXORDDET

Bit 9: RXORDDET.

Allowed values:
0: NoOrderedSet: No ordered set detected
1: OrderedSet: Ordered set detected

RXHRSTDET

Bit 10: RXHRSTDET.

Allowed values:
0: NoHardReset: Hard Reset not received
1: HardReset: Hard Reset received

RXOVR

Bit 11: RXOVR.

Allowed values:
0: NoOverflow: No overflow
1: Overflow: Overflow

RXMSGEND

Bit 12: RXMSGEND.

Allowed values:
0: NoNewMessage: No new Rx message received
1: NewMessage: A new Rx message received

RXERR

Bit 13: RXERR.

Allowed values:
0: NoError: No error detected
1: Error: Error(s) detected

TYPECEVT1

Bit 14: TYPECEVT1.

Allowed values:
0: NoNewEvent: No new event
1: NewEvent: A new Type-C event occurred

TYPECEVT2

Bit 15: TYPECEVT2.

Allowed values:
0: NoNewEvent: No new event
1: NewEvent: A new Type-C event occurred

TYPEC_VSTATE_CC1

Bits 16-17: TYPEC_VSTATE_CC1.

Allowed values:
0: Lowest: Lowest
1: Low: Low
2: High: High
3: Highest: Highest

TYPEC_VSTATE_CC2

Bits 18-19: TYPEC_VSTATE_CC2.

Allowed values:
0: Lowest: Lowest
1: Low: Low
2: High: High
3: Highest: Highest

FRSEVT

Bit 20: FRSEVT.

Allowed values:
0: NoNewEvent: No new event
1: NewEvent: New FRS receive event occurred

ICR

UCPD Interrupt Clear Register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRSEVTCF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TYPECEVT2CF
rw
TYPECEVT1CF
rw
RXMSGENDCF
rw
RXOVRCF
rw
RXHRSTDETCF
rw
RXORDDETCF
rw
TXUNDCF
rw
HRSTSENTCF
rw
HRSTDISCCF
rw
TXMSGABTCF
rw
TXMSGSENTCF
rw
TXMSGDISCCF
rw
Toggle fields

TXMSGDISCCF

Bit 1: TXMSGDISCCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TXMSGSENTCF

Bit 2: TXMSGSENTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TXMSGABTCF

Bit 3: TXMSGABTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

HRSTDISCCF

Bit 4: HRSTDISCCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

HRSTSENTCF

Bit 5: HRSTSENTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TXUNDCF

Bit 6: TXUNDCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXORDDETCF

Bit 9: RXORDDETCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXHRSTDETCF

Bit 10: RXHRSTDETCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXOVRCF

Bit 11: RXOVRCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

RXMSGENDCF

Bit 12: RXMSGENDCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TYPECEVT1CF

Bit 14: TYPECEVT1CF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TYPECEVT2CF

Bit 15: TYPECEVT2CF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

FRSEVTCF

Bit 20: FRSEVTCF.

Allowed values:
1: Clear: Clear flag in UCPD_SR

TX_ORDSETR

UCPD Tx Ordered Set Type Register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXORDSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXORDSET
rw
Toggle fields

TXORDSET

Bits 0-19: TXORDSET.

Allowed values: 0x0-0xfffff

TX_PAYSZR

UCPD Tx Paysize Register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPAYSZ
rw
Toggle fields

TXPAYSZ

Bits 0-9: TXPAYSZ.

Allowed values: 0x0-0x3ff

TXDR

UCPD Tx Data Register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

Allowed values: 0x0-0xff

RX_ORDSETR

UCPD Rx Ordered Set Register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPKINVALID
r
RXSOP3OF4
r
RXORDSET
r
Toggle fields

RXORDSET

Bits 0-2: RXORDSET.

Allowed values:
0: SOP: SOP code detected in receiver
1: SOPPrime: SOP' code detected in receiver
2: SOPDoublePrime: SOP'' code detected in receiver
3: SOPPrimeDebug: SOP'_Debug detected in receiver
4: SOPDoublePrimeDebug: SOP''_Debug detected in receiver
5: CableReset: Cable Reset detected in receiver
6: SOPExtension1: SOP extension #1 detected in receiver
7: SOPExtension2: SOP extension #2 detected in receiver

RXSOP3OF4

Bit 3: RXSOP3OF4.

Allowed values:
0: AllCorrect: 4 correct K-codes out of 4
1: OneIncorrect: 3 correct K-codes out of 4

RXSOPKINVALID

Bits 4-6: RXSOPKINVALID.

Allowed values:
0: Valid: No K-code corrupted
1: FirstCorrupted: First K-code corrupted
2: SecondCorrupted: Second K-code corrupted
3: ThirdCorrupted: Third K-code corrupted
4: FourthCorrupted: Fourth K-code corrupted

RX_PAYSZR

UCPD Rx Paysize Register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXPAYSZ
r
Toggle fields

RXPAYSZ

Bits 0-9: RXPAYSZ.

Allowed values: 0x0-0x3ff

RXDR

UCPD Receive Data Register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

Allowed values: 0x0-0xff

RX_ORDEXTR1

UCPD Rx Ordered Set Extension Register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX1
rw
Toggle fields

RXSOPX1

Bits 0-19: RXSOPX1.

Allowed values: 0x0-0xfffff

RX_ORDEXTR2

UCPD Rx Ordered Set Extension Register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXSOPX2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSOPX2
rw
Toggle fields

RXSOPX2

Bits 0-19: RXSOPX2.

Allowed values: 0x0-0xfffff

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART2

0x40004400: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USART3

0x40004800: Universal synchronous asynchronous receiver transmitter

124/124 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw
TXFEIE
rw
FIFOEN
rw
M1
rw
EOBIE
rw
RTOIE
rw
DEAT
rw
DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw
CMIE
rw
MME
rw
M0
rw
WAKE
rw
PCE
rw
PS
rw
PEIE
rw
TXEIE
rw
TCIE
rw
RXNEIE
rw
IDLEIE
rw
TE
rw
RE
rw
UESM
rw
UE
rw
Toggle fields

UE

Bit 0: USART enable.

Allowed values:
0: Disabled: UART is disabled
1: Enabled: UART is enabled

UESM

Bit 1: USART enable in Stop mode.

Allowed values:
0: Disabled: USART not able to wake up the MCU from Stop mode
1: Enabled: USART able to wake up the MCU from Stop mode

RE

Bit 2: Receiver enable.

Allowed values:
0: Disabled: Receiver is disabled
1: Enabled: Receiver is enabled

TE

Bit 3: Transmitter enable.

Allowed values:
0: Disabled: Transmitter is disabled
1: Enabled: Transmitter is enabled

IDLEIE

Bit 4: IDLE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever IDLE=1 in the ISR register

RXNEIE

Bit 5: RXNE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register

TCIE

Bit 6: Transmission complete interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TC=1 in the ISR register

TXEIE

Bit 7: interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever TXE=1 in the ISR register

PEIE

Bit 8: PE interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated whenever PE=1 in the ISR register

PS

Bit 9: Parity selection.

Allowed values:
0: Even: Even parity
1: Odd: Odd parity

PCE

Bit 10: Parity control enable.

Allowed values:
0: Disabled: Parity control disabled
1: Enabled: Parity control enabled

WAKE

Bit 11: Receiver wakeup method.

Allowed values:
0: Idle: Idle line
1: Address: Address mask

M0

Bit 12: Word length.

Allowed values:
0: Bit8: 1 start bit, 8 data bits, n stop bits
1: Bit9: 1 start bit, 9 data bits, n stop bits

MME

Bit 13: Mute mode enable.

Allowed values:
0: Disabled: Receiver in active mode permanently
1: Enabled: Receiver can switch between mute mode and active mode

CMIE

Bit 14: Character match interrupt enable.

Allowed values:
0: Disabled: Interrupt is disabled
1: Enabled: Interrupt is generated when the CMF bit is set in the ISR register

OVER8

Bit 15: Oversampling mode.

Allowed values:
0: Oversampling16: Oversampling by 16
1: Oversampling8: Oversampling by 8

DEDT

Bits 16-20: Driver Enable de-assertion time.

Allowed values: 0x0-0x1f

DEAT

Bits 21-25: Driver Enable assertion time.

Allowed values: 0x0-0x1f

RTOIE

Bit 26: Receiver timeout interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated when the RTOF bit is set in the ISR register

EOBIE

Bit 27: End of Block interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: A USART interrupt is generated when the EOBF flag is set in the ISR register

M1

Bit 28: Word length.

Allowed values:
0: M0: Use M0 to set the data bits
1: Bit7: 1 start bit, 7 data bits, n stop bits

FIFOEN

Bit 29: FIFOEN.

Allowed values:
0: Disabled: FIFO mode is disabled
1: Enabled: FIFO mode is enabled

TXFEIE

Bit 30: TXFEIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when TXFE = 1 in the USART_ISR register

RXFFIE

Bit 31: RXFFIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when RXFF = 1 in the USART_ISR register

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD
rw
RTOEN
rw
ABRMOD
rw
ABREN
rw
MSBFIRST
rw
DATAINV
rw
TXINV
rw
RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw
LINEN
rw
STOP
rw
CLKEN
rw
CPOL
rw
CPHA
rw
LBCL
rw
LBDIE
rw
LBDL
rw
ADDM7
rw
DIS_NSS
rw
SLVEN
rw
Toggle fields

SLVEN

Bit 0: SLVEN.

Allowed values:
0: Disabled: Slave mode disabled
1: Enabled: Slave mode enabled

DIS_NSS

Bit 3: DIS_NSS.

Allowed values:
0: Disabled: SPI slave selection depends on NSS input pin
1: Enabled: SPI slave is always selected and NSS input pin is ignored

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

Allowed values:
0: Bit4: 4-bit address detection
1: Bit7: 7-bit address detection

LBDL

Bit 5: LIN break detection length.

Allowed values:
0: Bit10: 10-bit break detection
1: Bit11: 11-bit break detection

LBDIE

Bit 6: LIN break detection interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever LBDF=1 in the ISR register

LBCL

Bit 8: Last bit clock pulse.

Allowed values:
0: NotOutput: The clock pulse of the last data bit is not output to the CK pin
1: Output: The clock pulse of the last data bit is output to the CK pin

CPHA

Bit 9: Clock phase.

Allowed values:
0: First: The first clock transition is the first data capture edge
1: Second: The second clock transition is the first data capture edge

CPOL

Bit 10: Clock polarity.

Allowed values:
0: Low: Steady low value on CK pin outside transmission window
1: High: Steady high value on CK pin outside transmission window

CLKEN

Bit 11: Clock enable.

Allowed values:
0: Disabled: CK pin disabled
1: Enabled: CK pin enabled

STOP

Bits 12-13: STOP bits.

Allowed values:
0: Stop1: 1 stop bit
1: Stop0p5: 0.5 stop bit
2: Stop2: 2 stop bit
3: Stop1p5: 1.5 stop bit

LINEN

Bit 14: LIN mode enable.

Allowed values:
0: Disabled: LIN mode disabled
1: Enabled: LIN mode enabled

SWAP

Bit 15: Swap TX/RX pins.

Allowed values:
0: Standard: TX/RX pins are used as defined in standard pinout
1: Swapped: The TX and RX pins functions are swapped

RXINV

Bit 16: RX pin active level inversion.

Allowed values:
0: Standard: RX pin signal works using the standard logic levels
1: Inverted: RX pin signal values are inverted

TXINV

Bit 17: TX pin active level inversion.

Allowed values:
0: Standard: TX pin signal works using the standard logic levels
1: Inverted: TX pin signal values are inverted

DATAINV

Bit 18: Binary data inversion.

Allowed values:
0: Positive: Logical data from the data register are send/received in positive/direct logic
1: Negative: Logical data from the data register are send/received in negative/inverse logic

MSBFIRST

Bit 19: Most significant bit first.

Allowed values:
0: LSB: data is transmitted/received with data bit 0 first, following the start bit
1: MSB: data is transmitted/received with MSB (bit 7/8/9) first, following the start bit

ABREN

Bit 20: Auto baud rate enable.

Allowed values:
0: Disabled: Auto baud rate detection is disabled
1: Enabled: Auto baud rate detection is enabled

ABRMOD

Bits 21-22: Auto baud rate mode.

Allowed values:
0: Start: Measurement of the start bit is used to detect the baud rate
1: Edge: Falling edge to falling edge measurement
2: Frame7F: 0x7F frame detection
3: Frame55: 0x55 frame detection

RTOEN

Bit 23: Receiver timeout enable.

Allowed values:
0: Disabled: Receiver timeout feature disabled
1: Enabled: Receiver timeout feature enabled

ADD

Bits 24-31: Address of the USART node.

Allowed values: 0x0-0xff

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

24/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw
RXFTIE
rw
RXFTCFG
rw
TCBGTIE
rw
TXFTIE
rw
WUFIE
rw
WUS
rw
SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw
DEM
rw
DDRE
rw
OVRDIS
rw
ONEBIT
rw
CTSIE
rw
CTSE
rw
RTSE
rw
DMAT
rw
DMAR
rw
SCEN
rw
NACK
rw
HDSEL
rw
IRLP
rw
IREN
rw
EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register

IREN

Bit 1: Ir mode enable.

Allowed values:
0: Disabled: IrDA disabled
1: Enabled: IrDA enabled

IRLP

Bit 2: Ir low-power.

Allowed values:
0: Normal: Normal mode
1: LowPower: Low-power mode

HDSEL

Bit 3: Half-duplex selection.

Allowed values:
0: NotSelected: Half duplex mode is not selected
1: Selected: Half duplex mode is selected

NACK

Bit 4: Smartcard NACK enable.

Allowed values:
0: Disabled: NACK transmission in case of parity error is disabled
1: Enabled: NACK transmission during parity error is enabled

SCEN

Bit 5: Smartcard mode enable.

Allowed values:
0: Disabled: Smartcard Mode disabled
1: Enabled: Smartcard Mode enabled

DMAR

Bit 6: DMA enable receiver.

Allowed values:
0: Disabled: DMA mode is disabled for reception
1: Enabled: DMA mode is enabled for reception

DMAT

Bit 7: DMA enable transmitter.

Allowed values:
0: Disabled: DMA mode is disabled for transmission
1: Enabled: DMA mode is enabled for transmission

RTSE

Bit 8: RTS enable.

Allowed values:
0: Disabled: RTS hardware flow control disabled
1: Enabled: RTS output enabled, data is only requested when there is space in the receive buffer

CTSE

Bit 9: CTS enable.

Allowed values:
0: Disabled: CTS hardware flow control disabled
1: Enabled: CTS mode enabled, data is only transmitted when the CTS input is asserted

CTSIE

Bit 10: CTS interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An interrupt is generated whenever CTSIF=1 in the ISR register

ONEBIT

Bit 11: One sample bit method enable.

Allowed values:
0: Sample3: Three sample bit method
1: Sample1: One sample bit method

OVRDIS

Bit 12: Overrun Disable.

Allowed values:
0: Enabled: Overrun Error Flag, ORE, is set when received data is not read before receiving new data
1: Disabled: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register

DDRE

Bit 13: DMA Disable on Reception Error.

Allowed values:
0: NotDisabled: DMA is not disabled in case of reception error
1: Disabled: DMA is disabled following a reception error

DEM

Bit 14: Driver enable mode.

Allowed values:
0: Disabled: DE function is disabled
1: Enabled: The DE signal is output on the RTS pin

DEP

Bit 15: Driver enable polarity selection.

Allowed values:
0: High: DE signal is active high
1: Low: DE signal is active low

SCARCNT

Bits 17-19: Smartcard auto-retry count.

Allowed values: 0x0-0x7

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

Allowed values:
0: Address: WUF active on address match
2: Start: WuF active on Start bit detection
3: RXNE: WUF active on RXNE

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

Allowed values:
0: Disabled: Interrupt is inhibited
1: Enabled: An USART interrupt is generated whenever WUF=1 in the ISR register

TXFTIE

Bit 23: TXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG

TCBGTIE

Bit 24: TCBGTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated whenever TCBGT=1 in the USART_ISR register

RXFTCFG

Bits 25-27: RXFTCFG.

Allowed values:
0: Depth_1_8: RXFIFO reaches 1/8 of its depth
1: Depth_1_4: RXFIFO reaches 1/4 of its depth
2: Depth_1_2: RXFIFO reaches 1/2 of its depth
3: Depth_3_4: RXFIFO reaches 3/4 of its depth
4: Depth_7_8: RXFIFO reaches 7/8 of its depth
5: Full: RXFIFO becomes full

RXFTIE

Bit 28: RXFTIE.

Allowed values:
0: Disabled: Interrupt inhibited
1: Enabled: USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG

TXFTCFG

Bits 29-31: TXFTCFG.

Allowed values:
0: Depth_1_8: TXFIFO reaches 1/8 of its depth
1: Depth_1_4: TXFIFO reaches 1/4 of its depth
2: Depth_1_2: TXFIFO reaches 1/2 of its depth
3: Depth_3_4: TXFIFO reaches 3/4 of its depth
4: Depth_7_8: TXFIFO reaches 7/8 of its depth
5: Empty: TXFIFO becomes empty

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR
rw
Toggle fields

BRR

Bits 0-15: BRR.

Allowed values: 0x0-0xffff

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw
PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

Allowed values: 0x0-0xff

GT

Bits 8-15: Guard time value.

Allowed values: 0x0-0xff

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw
RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

Allowed values: 0x0-0xffffff

BLEN

Bits 24-31: Block Length.

Allowed values: 0x0-0xff

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w
RXFRQ
w
MMRQ
w
SBKRQ
w
ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

Allowed values:
1: Request: resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame

SBKRQ

Bit 1: Send break request.

Allowed values:
1: Break: sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available

MMRQ

Bit 2: Mute mode request.

Allowed values:
1: Mute: Puts the USART in mute mode and sets the RWU flag

RXFRQ

Bit 3: Receive data flush request.

Allowed values:
1: Discard: clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition

TXFRQ

Bit 4: Transmit data flush request.

Allowed values:
1: Discard: Set the TXE flags. This allows to discard the transmit data

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r
RXFT
r
TCBGT
r
RXFF
r
TXFE
r
REACK
r
TEACK
r
WUF
r
RWU
r
SBKF
r
CMF
r
BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r
ABRE
r
UDR
r
EOBF
r
RTOF
r
CTS
r
CTSIF
r
LBDF
r
TXE
r
TC
r
RXNE
r
IDLE
r
ORE
r
NF
r
FE
r
PE
r
Toggle fields

PE

Bit 0: PE.

Allowed values:
0: NoError: No parity error
1: Error: Parity error

FE

Bit 1: FE.

Allowed values:
0: NoError: No Framing error is detected
1: Error: Framing error or break character is detected

NF

Bit 2: NF.

Allowed values:
0: NoNoise: No noise is detected
1: Noise: Noise is detected

ORE

Bit 3: ORE.

Allowed values:
0: NoOverrun: No Overrun error
1: Overrun: Overrun error is detected

IDLE

Bit 4: IDLE.

Allowed values:
0: NoIdle: No Idle Line is detected
1: Idle: Idle Line is detected

RXNE

Bit 5: RXNE.

Allowed values:
0: NoData: Data is not received
1: DataReady: Received data is ready to be read

TC

Bit 6: TC.

Allowed values:
0: TxNotComplete: Transmission is not complete
1: TxComplete: Transmission is complete

TXE

Bit 7: TXE.

Allowed values:
0: Full: Transmit FIFO is full
1: NotFull: Transmit FIFO is not full

LBDF

Bit 8: LBDF.

Allowed values:
0: NotDetected: LIN break not detected
1: Detected: LIN break detected

CTSIF

Bit 9: CTSIF.

Allowed values:
0: NotChanged: No change occurred on the CTS status line
1: Changed: A change occurred on the CTS status line

CTS

Bit 10: CTS.

Allowed values:
0: Set: CTS line set
1: Reset: CTS line reset

RTOF

Bit 11: RTOF.

Allowed values:
0: NotReached: Timeout value not reached
1: Reached: Timeout value reached without any data reception

EOBF

Bit 12: EOBF.

Allowed values:
0: NotReached: End of Block not reached
1: Reached: End of Block (number of characters) reached

UDR

Bit 13: SPI slave underrun error flag In Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..

Allowed values:
0: NoUnderrun: No underrun error
1: Underrun: underrun error

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

Allowed values:
0: Idle: USART is idle (no reception)
1: Busy: Reception on going

CMF

Bit 17: CMF.

Allowed values:
0: NoMatch: No Character match detected
1: Match: Character match detected

SBKF

Bit 18: SBKF.

Allowed values:
0: NoBreak: No break character transmitted
1: Break: Break character transmitted

RWU

Bit 19: RWU.

Allowed values:
0: Active: Receiver in Active mode
1: Mute: Receiver in Mute mode

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFE.

Allowed values:
0: NotEmpty: TXFIFO not empty.
1: Empty: TXFIFO empty.

RXFF

Bit 24: RXFF.

Allowed values:
0: NotFull: RXFIFO not full.
1: Full: RXFIFO Full.

TCBGT

Bit 25: TCBGT.

Allowed values:
0: NotCompleted: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
1: Completed: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)

RXFT

Bit 26: RXFT.

Allowed values:
0: NotReached: Receive FIFO does not reach the programmed threshold.
1: Reached: Receive FIFO reached the programmed threshold.

TXFT

Bit 27: TXFT.

Allowed values:
0: NotReached: TXFIFO does not reach the programmed threshold.
1: Reached: TXFIFO reached the programmed threshold.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

15/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w1c
CMCF
w1c
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w1c
EOBCF
w1c
RTOCF
w1c
CTSCF
w1c
LBDCF
w1c
TCBGTCF
w1c
TCCF
w1c
TXFECF
w1c
IDLECF
w1c
ORECF
w1c
NCF
w1c
FECF
w1c
PECF
w1c
Toggle fields

PECF

Bit 0: Parity error clear flag.

Allowed values:
1: Clear: Clears the PE flag in the ISR register

FECF

Bit 1: Framing error clear flag.

Allowed values:
1: Clear: Clears the FE flag in the ISR register

NCF

Bit 2: Noise detected clear flag.

Allowed values:
1: Clear: Clears the NF flag in the ISR register

ORECF

Bit 3: Overrun error clear flag.

Allowed values:
1: Clear: Clears the ORE flag in the ISR register

IDLECF

Bit 4: Idle line detected clear flag.

Allowed values:
1: Clear: Clears the IDLE flag in the ISR register

TXFECF

Bit 5: TXFECF.

Allowed values:
1: Clear: Clear the TXFE flag in the ISR register

TCCF

Bit 6: Transmission complete clear flag.

Allowed values:
1: Clear: Clears the TC flag in the ISR register

TCBGTCF

Bit 7: TCBGTCF.

Allowed values:
1: Clear: Clear the TCBGT flag in the ISR register

LBDCF

Bit 8: LIN break detection clear flag.

Allowed values:
1: Clear: Clears the LBDF flag in the ISR register

CTSCF

Bit 9: CTS clear flag.

Allowed values:
1: Clear: Clears the CTSIF flag in the ISR register

RTOCF

Bit 11: Receiver timeout clear flag.

Allowed values:
1: Clear: Clears the RTOF flag in the ISR register

EOBCF

Bit 12: End of block clear flag.

Allowed values:
1: Clear: Clears the EOBF flag in the ISR register

UDRCF

Bit 13: UDRCF.

Allowed values:
1: Clear: Clear the UDR flag in the ISR register

CMCF

Bit 17: Character match clear flag.

Allowed values:
1: Clear: Clears the CMF flag in the ISR register

WUCF

Bit 20: Wakeup from Stop mode clear flag.

Allowed values:
1: Clear: Clears the WUF flag in the ISR register

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

Allowed values: 0x0-0x1ff

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

Allowed values: 0x0-0x1ff

PRESC

PRESC

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: PRESCALER.

Allowed values:
0: Div1: Input clock divided by 1
1: Div2: Input clock divided by 2
2: Div4: Input clock divided by 4
3: Div6: Input clock divided by 6
4: Div8: Input clock divided by 8
5: Div10: Input clock divided by 10
6: Div12: Input clock divided by 12
7: Div16: Input clock divided by 16
8: Div32: Input clock divided by 32
9: Div64: Input clock divided by 64
10: Div128: Input clock divided by 128
11: Div256: Input clock divided by 256

USB

0x4000d400: Universal serial bus full-speed device interface

8/127 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) EP[0]R
0x4 (16-bit) EP[1]R
0x8 (16-bit) EP[2]R
0xc (16-bit) EP[3]R
0x10 (16-bit) EP[4]R
0x14 (16-bit) EP[5]R
0x18 (16-bit) EP[6]R
0x1c (16-bit) EP[7]R
0x40 (16-bit) CNTR
0x44 (16-bit) ISTR
0x48 (16-bit) FNR
0x4c (16-bit) DADDR
0x50 (16-bit) BTABLE
0x54 (16-bit) LPMCSR
0x58 (16-bit) BCDR
Toggle registers

EP[0]R

endpoint 0 register

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[1]R

endpoint 1 register

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[2]R

endpoint 2 register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[3]R

endpoint 3 register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[4]R

endpoint 4 register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[5]R

endpoint 5 register

Offset: 0x14, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[6]R

endpoint 6 register

Offset: 0x18, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP[7]R

endpoint 7 register

Offset: 0x1c, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR_RX
rw
DTOG_RX
rw
STAT_RX
rw
SETUP
rw
EP_TYPE
rw
EP_KIND
rw
CTR_TX
rw
DTOG_TX
rw
STAT_TX
rw
EA
rw
Toggle fields

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, size: 16, reset: 0x00000003, access: read-write

0/15 fields covered.

Toggle fields

FRES

Bit 0: Force USB Reset.

PDWN

Bit 1: Power down.

LPMODE

Bit 2: Low-power mode.

FSUSP

Bit 3: Force suspend.

RESUME

Bit 4: Resume request.

L1RESUME

Bit 5: LPM L1 Resume request.

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RESETM

Bit 10: USB reset interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

ISTR

interrupt status register

Offset: 0x44, size: 16, reset: 0x00000000, access: Unspecified

3/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTR
r
PMAOVR
rw
ERR
rw
WKUP
rw
SUSP
rw
RESET
rw
SOF
rw
ESOF
rw
L1REQ
rw
DIR
r
EP_ID
r
Toggle fields

EP_ID

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 state request.

ESOF

Bit 8: Expected start frame.

SOF

Bit 9: start of frame.

RESET

Bit 10: reset request.

SUSP

Bit 11: Suspend mode request.

WKUP

Bit 12: Wakeup.

ERR

Bit 13: Error.

PMAOVR

Bit 14: Packet memory area over / underrun.

CTR

Bit 15: Correct transfer.

FNR

frame number register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDP
r
RXDM
r
LCK
r
LSOF
r
FN
r
Toggle fields

FN

Bits 0-10: Frame number.

LSOF

Bits 11-12: Lost SOF.

LCK

Bit 13: Locked.

RXDM

Bit 14: Receive data - line status.

RXDP

Bit 15: Receive data + line status.

DADDR

device address

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EF
rw
ADD
rw
Toggle fields

ADD

Bits 0-6: Device address.

EF

Bit 7: Enable function.

BTABLE

Buffer table address

Offset: 0x50, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BTABLE
rw
Toggle fields

BTABLE

Bits 3-15: Buffer table.

LPMCSR

LPM control and status register

Offset: 0x54, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BESL
rw
REMWAKE
rw
LPMACK
rw
LPMEN
rw
Toggle fields

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM Token acknowledge enable.

REMWAKE

Bit 3: RemoteWake value.

BESL

Bits 4-7: BESL value.

BCDR

Battery charging detector

Offset: 0x58, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPPU
rw
PS2DET
rw
SDET
rw
PDET
rw
DCDET
rw
SDEN
rw
PDEN
rw
DCDEN
rw
BCDEN
rw
Toggle fields

BCDEN

Bit 0: Battery charging detector (BCD) enable.

DCDEN

Bit 1: Data contact detection (DCD) mode enable.

PDEN

Bit 2: Primary detection (PD) mode enable.

SDEN

Bit 3: Secondary detection (SD) mode enable.

DCDET

Bit 4: Data contact detection (DCD) status.

PDET

Bit 5: Primary detection (PD) status.

SDET

Bit 6: Secondary detection (SD) status.

PS2DET

Bit 7: DM pull-up detection status.

DPPU

Bit 15: DP pull-up control.

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRR
r
VRS
rw
HIZ
rw
ENVR
rw
Toggle fields

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: Trimming code.

WWDG

0x40002c00: System window watchdog

0/6 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR
0x4 (16-bit) CFR
0x8 (16-bit) SR
Toggle registers

CR

Control register

Offset: 0x0, size: 16, reset: 0x0000007F, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw
T
rw
Toggle fields

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, size: 16, reset: 0x0000007F, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWI
rw
WDGTB
rw
W
rw
Toggle fields

W

Bits 0-6: 7-bit window value.

WDGTB

Bits 7-8: Timer base.

EWI

Bit 9: Early wakeup interrupt.

SR

Status register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
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EWIF

Bit 0: Early wakeup interrupt flag.