Overall: 3939/20543 fields covered

ADC

0x48003000: ADC

5/161 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x1c PCSEL
0x20 LTR1
0x24 HTR1
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 LTR2
0xb4 HTR2
0xb8 LTR3
0xbc HTR3
0xc0 DIFSEL
0xc4 CALFACT
0xc8 CALFACT2
Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x20000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw 		LINCALRDYW6
rw 		LINCALRDYW5
rw 		LINCALRDYW4
rw 		LINCALRDYW3
rw 		LINCALRDYW2
rw 		LINCALRDYW1
rw 		ADCALLIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOST
rw 		JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

BOOST

Bit 8: BOOST.

ADCALLIN

Bit 16: ADCALLIN.

LINCALRDYW1

Bit 22: LINCALRDYW1.

LINCALRDYW2

Bit 23: LINCALRDYW2.

LINCALRDYW3

Bit 24: LINCALRDYW3.

LINCALRDYW4

Bit 25: LINCALRDYW4.

LINCALRDYW5

Bit 26: LINCALRDYW5.

LINCALRDYW6

Bit 27: LINCALRDYW6.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

ADC configuration register

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWD1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		RES
rw 		DMNGT
rw
Toggle fields

DMNGT

Bits 0-1: DMNGT.

RES

Bits 2-4: RES.

EXTSEL

Bits 5-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWD1CH

Bits 26-30: AWD1CH.

JQDIS

Bit 31: JQDIS.

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSHIFT
rw 		OSVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSHIFT4
rw 		RSHIFT3
rw 		RSHIFT2
rw 		RSHIFT1
rw 		ROVSM
rw 		TROVS
rw 		OVSS
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: ROVSE.

JOVSE

Bit 1: JOVSE.

OVSS

Bits 5-8: OVSS.

TROVS

Bit 9: TROVS.

ROVSM

Bit 10: ROVSM.

RSHIFT1

Bit 11: RSHIFT1.

RSHIFT2

Bit 12: RSHIFT2.

RSHIFT3

Bit 13: RSHIFT3.

RSHIFT4

Bit 14: RSHIFT4.

OSVR

Bits 16-25: OSVR.

LSHIFT

Bits 28-31: LSHIFT.

SMPR1

ADC sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPR2

ADC sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP19
rw 		SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

SMP19

Bits 27-29: SMP19.

PCSEL

ADC channel preselection register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCSEL19
rw 		PCSEL18
rw 		PCSEL17
rw 		PCSEL16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCSEL15
rw 		PCSEL14
rw 		PCSEL13
rw 		PCSEL12
rw 		PCSEL11
rw 		PCSEL10
rw 		PCSEL9
rw 		PCSEL8
rw 		PCSEL7
rw 		PCSEL6
rw 		PCSEL5
rw 		PCSEL4
rw 		PCSEL3
rw 		PCSEL2
rw 		PCSEL1
rw 		PCSEL0
rw
Toggle fields

PCSEL0

Bit 0: PCSEL0.

PCSEL1

Bit 1: PCSEL1.

PCSEL2

Bit 2: PCSEL2.

PCSEL3

Bit 3: PCSEL3.

PCSEL4

Bit 4: PCSEL4.

PCSEL5

Bit 5: PCSEL5.

PCSEL6

Bit 6: PCSEL6.

PCSEL7

Bit 7: PCSEL7.

PCSEL8

Bit 8: PCSEL8.

PCSEL9

Bit 9: PCSEL9.

PCSEL10

Bit 10: PCSEL10.

PCSEL11

Bit 11: PCSEL11.

PCSEL12

Bit 12: PCSEL12.

PCSEL13

Bit 13: PCSEL13.

PCSEL14

Bit 14: PCSEL14.

PCSEL15

Bit 15: PCSEL15.

PCSEL16

Bit 16: PCSEL16.

PCSEL17

Bit 17: PCSEL17.

PCSEL18

Bit 18: PCSEL18.

PCSEL19

Bit 19: PCSEL19.

LTR1

ADC watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR1
rw
Toggle fields

LTR1

Bits 0-25: LTR1.

HTR1

ADC watchdog threshold register 1

Offset: 0x24, size: 32, reset: 0x03FFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR1
rw
Toggle fields

HTR1

Bits 0-25: HTR1.

SQR1

ADC regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

ADC regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

ADC regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

ADC regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

ADC regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-31: RDATA.

JSQR

ADC injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-6: JEXTSEL.

JEXTEN

Bits 7-8: JEXTEN.

JSQ1

Bits 9-13: JSQ1.

JSQ2

Bits 15-19: JSQ2.

JSQ3

Bits 21-25: JSQ3.

JSQ4

Bits 27-31: JSQ4.

OFR1

ADC offset register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET1_CH
rw 		OFFSET1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-25: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

SSATE

Bit 31: SSATE.

OFR2

ADC offset register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET2_CH
rw 		OFFSET2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-25: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

SSATE

Bit 31: SSATE.

OFR3

ADC offset register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET3_CH
rw 		OFFSET3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-25: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

SSATE

Bit 31: SSATE.

OFR4

ADC offset register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET4_CH
rw 		OFFSET4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-25: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

SSATE

Bit 31: SSATE.

JDR1

ADC injected data register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

JDR2

ADC injected data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

JDR3

ADC injected data register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

JDR4

ADC injected data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-19: AWD2CH.

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-19: AWD3CH.

LTR2

ADC watchdog lower threshold register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR2
rw
Toggle fields

LTR2

Bits 0-25: LTR2.

HTR2

ADC watchdog higher threshold register 2

Offset: 0xb4, size: 32, reset: 0x03FFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR2
rw
Toggle fields

HTR2

Bits 0-25: HTR2.

LTR3

ADC watchdog lower threshold register 3

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR3
rw
Toggle fields

LTR3

Bits 0-25: LTR3.

HTR3

ADC watchdog higher threshold register 3

Offset: 0xbc, size: 32, reset: 0x03FFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR3
rw
Toggle fields

HTR3

Bits 0-25: HTR3.

DIFSEL

ADC differential mode selection register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL
rw
Toggle fields

DIFSEL

Bits 0-19: DIFSEL.

CALFACT

ADC calibration factors register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-10: CALFACT_S.

CALFACT_D

Bits 16-26: CALFACT_D.

CALFACT2

ADC calibration factor register 2

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINCALFACT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCALFACT
rw
Toggle fields

LINCALFACT

Bits 0-29: LINCALFACT.

ADC2

0x48003100: ADC2

5/162 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 IER
0x8 CR
0xc CFGR
0x10 CFGR2
0x14 SMPR1
0x18 SMPR2
0x1c PCSEL
0x20 LTR1
0x24 HTR1
0x30 SQR1
0x34 SQR2
0x38 SQR3
0x3c SQR4
0x40 DR
0x4c JSQR
0x60 OFR1
0x64 OFR2
0x68 OFR3
0x6c OFR4
0x80 JDR1
0x84 JDR2
0x88 JDR3
0x8c JDR4
0xa0 AWD2CR
0xa4 AWD3CR
0xb0 LTR2
0xb4 HTR2
0xb8 LTR3
0xbc HTR3
0xc0 DIFSEL
0xc4 CALFACT
0xc8 CALFACT2
0xd0 OR
Toggle registers

ISR

ADC interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF
rw 		AWD3
rw 		AWD2
rw 		AWD1
rw 		JEOS
rw 		JEOC
rw 		OVR
rw 		EOS
rw 		EOC
rw 		EOSMP
rw 		ADRDY
rw
Toggle fields

ADRDY

Bit 0: ADRDY.

EOSMP

Bit 1: EOSMP.

EOC

Bit 2: EOC.

EOS

Bit 3: EOS.

OVR

Bit 4: OVR.

JEOC

Bit 5: JEOC.

JEOS

Bit 6: JEOS.

AWD1

Bit 7: AWD1.

AWD2

Bit 8: AWD2.

AWD3

Bit 9: AWD3.

JQOVF

Bit 10: JQOVF.

IER

ADC interrupt enable register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVFIE
rw 		AWD3IE
rw 		AWD2IE
rw 		AWD1IE
rw 		JEOSIE
rw 		JEOCIE
rw 		OVRIE
rw 		EOSIE
rw 		EOCIE
rw 		EOSMPIE
rw 		ADRDYIE
rw
Toggle fields

ADRDYIE

Bit 0: ADRDYIE.

EOSMPIE

Bit 1: EOSMPIE.

EOCIE

Bit 2: EOCIE.

EOSIE

Bit 3: EOSIE.

OVRIE

Bit 4: OVRIE.

JEOCIE

Bit 5: JEOCIE.

JEOSIE

Bit 6: JEOSIE.

AWD1IE

Bit 7: AWD1IE.

AWD2IE

Bit 8: AWD2IE.

AWD3IE

Bit 9: AWD3IE.

JQOVFIE

Bit 10: JQOVFIE.

CR

ADC control register

Offset: 0x8, size: 32, reset: 0x20000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCAL
rw 		ADCALDIF
rw 		DEEPPWD
rw 		ADVREGEN
rw 		LINCALRDYW6
rw 		LINCALRDYW5
rw 		LINCALRDYW4
rw 		LINCALRDYW3
rw 		LINCALRDYW2
rw 		LINCALRDYW1
rw 		ADCALLIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOST
rw 		JADSTP
rw 		ADSTP
rw 		JADSTART
rw 		ADSTART
rw 		ADDIS
rw 		ADEN
rw
Toggle fields

ADEN

Bit 0: ADEN.

ADDIS

Bit 1: ADDIS.

ADSTART

Bit 2: ADSTART.

JADSTART

Bit 3: JADSTART.

ADSTP

Bit 4: ADSTP.

JADSTP

Bit 5: JADSTP.

BOOST

Bit 8: BOOST.

ADCALLIN

Bit 16: ADCALLIN.

LINCALRDYW1

Bit 22: LINCALRDYW1.

LINCALRDYW2

Bit 23: LINCALRDYW2.

LINCALRDYW3

Bit 24: LINCALRDYW3.

LINCALRDYW4

Bit 25: LINCALRDYW4.

LINCALRDYW5

Bit 26: LINCALRDYW5.

LINCALRDYW6

Bit 27: LINCALRDYW6.

ADVREGEN

Bit 28: ADVREGEN.

DEEPPWD

Bit 29: DEEPPWD.

ADCALDIF

Bit 30: ADCALDIF.

ADCAL

Bit 31: ADCAL.

CFGR

ADC configuration register

Offset: 0xc, size: 32, reset: 0x80000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQDIS
rw 		AWD1CH
rw 		JAUTO
rw 		JAWD1EN
rw 		AWD1EN
rw 		AWD1SGL
rw 		JQM
rw 		JDISCEN
rw 		DISCNUM
rw 		DISCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTDLY
rw 		CONT
rw 		OVRMOD
rw 		EXTEN
rw 		EXTSEL
rw 		RES
rw 		DMNGT
rw
Toggle fields

DMNGT

Bits 0-1: DMNGT.

RES

Bits 2-4: RES.

EXTSEL

Bits 5-9: EXTSEL.

EXTEN

Bits 10-11: EXTEN.

OVRMOD

Bit 12: OVRMOD.

CONT

Bit 13: CONT.

AUTDLY

Bit 14: AUTDLY.

DISCEN

Bit 16: DISCEN.

DISCNUM

Bits 17-19: DISCNUM.

JDISCEN

Bit 20: JDISCEN.

JQM

Bit 21: JQM.

AWD1SGL

Bit 22: AWD1SGL.

AWD1EN

Bit 23: AWD1EN.

JAWD1EN

Bit 24: JAWD1EN.

JAUTO

Bit 25: JAUTO.

AWD1CH

Bits 26-30: AWD1CH.

JQDIS

Bit 31: JQDIS.

CFGR2

ADC configuration register 2

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSHIFT
rw 		OSVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSHIFT4
rw 		RSHIFT3
rw 		RSHIFT2
rw 		RSHIFT1
rw 		ROVSM
rw 		TROVS
rw 		OVSS
rw 		JOVSE
rw 		ROVSE
rw
Toggle fields

ROVSE

Bit 0: ROVSE.

JOVSE

Bit 1: JOVSE.

OVSS

Bits 5-8: OVSS.

TROVS

Bit 9: TROVS.

ROVSM

Bit 10: ROVSM.

RSHIFT1

Bit 11: RSHIFT1.

RSHIFT2

Bit 12: RSHIFT2.

RSHIFT3

Bit 13: RSHIFT3.

RSHIFT4

Bit 14: RSHIFT4.

OSVR

Bits 16-25: OSVR.

LSHIFT

Bits 28-31: LSHIFT.

SMPR1

ADC sample time register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP9
rw 		SMP8
rw 		SMP7
rw 		SMP6
rw 		SMP5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5
rw 		SMP4
rw 		SMP3
rw 		SMP2
rw 		SMP1
rw 		SMP0
rw
Toggle fields

SMP0

Bits 0-2: SMP0.

SMP1

Bits 3-5: SMP1.

SMP2

Bits 6-8: SMP2.

SMP3

Bits 9-11: SMP3.

SMP4

Bits 12-14: SMP4.

SMP5

Bits 15-17: SMP5.

SMP6

Bits 18-20: SMP6.

SMP7

Bits 21-23: SMP7.

SMP8

Bits 24-26: SMP8.

SMP9

Bits 27-29: SMP9.

SMPR2

ADC sample time register 2

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMP19
rw 		SMP18
rw 		SMP17
rw 		SMP16
rw 		SMP15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15
rw 		SMP14
rw 		SMP13
rw 		SMP12
rw 		SMP11
rw 		SMP10
rw
Toggle fields

SMP10

Bits 0-2: SMP10.

SMP11

Bits 3-5: SMP11.

SMP12

Bits 6-8: SMP12.

SMP13

Bits 9-11: SMP13.

SMP14

Bits 12-14: SMP14.

SMP15

Bits 15-17: SMP15.

SMP16

Bits 18-20: SMP16.

SMP17

Bits 21-23: SMP17.

SMP18

Bits 24-26: SMP18.

SMP19

Bits 27-29: SMP19.

PCSEL

ADC channel preselection register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCSEL19
rw 		PCSEL18
rw 		PCSEL17
rw 		PCSEL16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCSEL15
rw 		PCSEL14
rw 		PCSEL13
rw 		PCSEL12
rw 		PCSEL11
rw 		PCSEL10
rw 		PCSEL9
rw 		PCSEL8
rw 		PCSEL7
rw 		PCSEL6
rw 		PCSEL5
rw 		PCSEL4
rw 		PCSEL3
rw 		PCSEL2
rw 		PCSEL1
rw 		PCSEL0
rw
Toggle fields

PCSEL0

Bit 0: PCSEL0.

PCSEL1

Bit 1: PCSEL1.

PCSEL2

Bit 2: PCSEL2.

PCSEL3

Bit 3: PCSEL3.

PCSEL4

Bit 4: PCSEL4.

PCSEL5

Bit 5: PCSEL5.

PCSEL6

Bit 6: PCSEL6.

PCSEL7

Bit 7: PCSEL7.

PCSEL8

Bit 8: PCSEL8.

PCSEL9

Bit 9: PCSEL9.

PCSEL10

Bit 10: PCSEL10.

PCSEL11

Bit 11: PCSEL11.

PCSEL12

Bit 12: PCSEL12.

PCSEL13

Bit 13: PCSEL13.

PCSEL14

Bit 14: PCSEL14.

PCSEL15

Bit 15: PCSEL15.

PCSEL16

Bit 16: PCSEL16.

PCSEL17

Bit 17: PCSEL17.

PCSEL18

Bit 18: PCSEL18.

PCSEL19

Bit 19: PCSEL19.

LTR1

ADC watchdog threshold register 1

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR1
rw
Toggle fields

LTR1

Bits 0-25: LTR1.

HTR1

ADC watchdog threshold register 1

Offset: 0x24, size: 32, reset: 0x03FFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR1
rw
Toggle fields

HTR1

Bits 0-25: HTR1.

SQR1

ADC regular sequence register 1

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ4
rw 		SQ3
rw 		SQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2
rw 		SQ1
rw 		L
rw
Toggle fields

L

Bits 0-3: L.

SQ1

Bits 6-10: SQ1.

SQ2

Bits 12-16: SQ2.

SQ3

Bits 18-22: SQ3.

SQ4

Bits 24-28: SQ4.

SQR2

ADC regular sequence register 2

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ9
rw 		SQ8
rw 		SQ7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7
rw 		SQ6
rw 		SQ5
rw
Toggle fields

SQ5

Bits 0-4: SQ5.

SQ6

Bits 6-10: SQ6.

SQ7

Bits 12-16: SQ7.

SQ8

Bits 18-22: SQ8.

SQ9

Bits 24-28: SQ9.

SQR3

ADC regular sequence register 3

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SQ14
rw 		SQ13
rw 		SQ12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12
rw 		SQ11
rw 		SQ10
rw
Toggle fields

SQ10

Bits 0-4: SQ10.

SQ11

Bits 6-10: SQ11.

SQ12

Bits 12-16: SQ12.

SQ13

Bits 18-22: SQ13.

SQ14

Bits 24-28: SQ14.

SQR4

ADC regular sequence register 4

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ16
rw 		SQ15
rw
Toggle fields

SQ15

Bits 0-4: SQ15.

SQ16

Bits 6-10: SQ16.

DR

ADC regular Data Register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r
Toggle fields

RDATA

Bits 0-31: RDATA.

JSQR

ADC injected sequence register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JSQ4
rw 		JSQ3
rw 		JSQ2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2
rw 		JSQ1
rw 		JEXTEN
rw 		JEXTSEL
rw 		JL
rw
Toggle fields

JL

Bits 0-1: JL.

JEXTSEL

Bits 2-6: JEXTSEL.

JEXTEN

Bits 7-8: JEXTEN.

JSQ1

Bits 9-13: JSQ1.

JSQ2

Bits 15-19: JSQ2.

JSQ3

Bits 21-25: JSQ3.

JSQ4

Bits 27-31: JSQ4.

OFR1

ADC offset register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET1_CH
rw 		OFFSET1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET1
rw
Toggle fields

OFFSET1

Bits 0-25: OFFSET1.

OFFSET1_CH

Bits 26-30: OFFSET1_CH.

SSATE

Bit 31: SSATE.

OFR2

ADC offset register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET2_CH
rw 		OFFSET2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET2
rw
Toggle fields

OFFSET2

Bits 0-25: OFFSET2.

OFFSET2_CH

Bits 26-30: OFFSET2_CH.

SSATE

Bit 31: SSATE.

OFR3

ADC offset register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET3_CH
rw 		OFFSET3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET3
rw
Toggle fields

OFFSET3

Bits 0-25: OFFSET3.

OFFSET3_CH

Bits 26-30: OFFSET3_CH.

SSATE

Bit 31: SSATE.

OFR4

ADC offset register

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSATE
rw 		OFFSET4_CH
rw 		OFFSET4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET4
rw
Toggle fields

OFFSET4

Bits 0-25: OFFSET4.

OFFSET4_CH

Bits 26-30: OFFSET4_CH.

SSATE

Bit 31: SSATE.

JDR1

ADC injected data register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

JDR2

ADC injected data register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

JDR3

ADC injected data register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

JDR4

ADC injected data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r
Toggle fields

JDATA

Bits 0-31: JDATA.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD2CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD2CH
rw
Toggle fields

AWD2CH

Bits 0-19: AWD2CH.

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWD3CH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWD3CH
rw
Toggle fields

AWD3CH

Bits 0-19: AWD3CH.

LTR2

ADC watchdog lower threshold register 2

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR2
rw
Toggle fields

LTR2

Bits 0-25: LTR2.

HTR2

ADC watchdog higher threshold register 2

Offset: 0xb4, size: 32, reset: 0x03FFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR2
rw
Toggle fields

HTR2

Bits 0-25: HTR2.

LTR3

ADC watchdog lower threshold register 3

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LTR3
rw
Toggle fields

LTR3

Bits 0-25: LTR3.

HTR3

ADC watchdog higher threshold register 3

Offset: 0xbc, size: 32, reset: 0x03FFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTR3
rw
Toggle fields

HTR3

Bits 0-25: HTR3.

DIFSEL

ADC differential mode selection register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIFSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIFSEL
rw
Toggle fields

DIFSEL

Bits 0-19: DIFSEL.

CALFACT

ADC calibration factors register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALFACT_D
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALFACT_S
rw
Toggle fields

CALFACT_S

Bits 0-10: CALFACT_S.

CALFACT_D

Bits 16-26: CALFACT_D.

CALFACT2

ADC calibration factor register 2

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LINCALFACT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINCALFACT
rw
Toggle fields

LINCALFACT

Bits 0-29: LINCALFACT.

OR

ADC2 option register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDDCOREEN
rw
Toggle fields

VDDCOREEN

Bit 0: VDDCOREEN.

ADC_common

0x48003300: Analog-to-Digital Converter

25/34 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x8 CCR
0xc CDR
0x10 CDR2
Toggle registers

CSR

ADC Common status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

22/22 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_SLV
r 		AWD3_SLV
r 		AWD2_SLV
r 		AWD1_SLV
r 		JEOS_SLV
r 		JEOC_SLV
r 		OVR_SLV
r 		EOS_SLV
r 		EOC_SLV
r 		EOSMP_SLV
r 		ADRDY_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_MST
r 		AWD3_MST
r 		AWD2_MST
r 		AWD1_MST
r 		JEOS_MST
r 		JEOC_MST
r 		OVR_MST
r 		EOS_MST
r 		EOC_MST
r 		EOSMP_MST
r 		ADDRDY_MST
r
Toggle fields

ADDRDY_MST

Bit 0: ADDRDY_MST.

EOSMP_MST

Bit 1: EOSMP_MST.

EOC_MST

Bit 2: EOC_MST.

EOS_MST

Bit 3: EOS_MST.

OVR_MST

Bit 4: OVR_MST.

JEOC_MST

Bit 5: JEOC_MST.

JEOS_MST

Bit 6: JEOS_MST.

AWD1_MST

Bit 7: AWD1_MST.

AWD2_MST

Bit 8: AWD2_MST.

AWD3_MST

Bit 9: AWD3_MST.

JQOVF_MST

Bit 10: JQOVF_MST.

ADRDY_SLV

Bit 16: ADRDY_SLV.

EOSMP_SLV

Bit 17: EOSMP_SLV.

EOC_SLV

Bit 18: EOC_SLV.

EOS_SLV

Bit 19: EOS_SLV.

OVR_SLV

Bit 20: OVR_SLV.

JEOC_SLV

Bit 21: JEOC_SLV.

JEOS_SLV

Bit 22: JEOS_SLV.

AWD1_SLV

Bit 23: AWD1_SLV.

AWD2_SLV

Bit 24: AWD2_SLV.

AWD3_SLV

Bit 25: AWD3_SLV.

JQOVF_SLV

Bit 26: JQOVF_SLV.

CCR

ADC common control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18SEL
rw 		CH17SEL
rw 		VREFEN
rw 		PRESC
rw 		CKMODE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMA
rw 		DMACFG
rw 		DELAY
rw 		DUAL
rw
Toggle fields

DUAL

Bits 0-4: DUAL.

DELAY

Bits 8-10: DELAY.

DMACFG

Bit 13: DMACFG.

MDMA

Bits 14-15: MDMA.

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: VREFINT enable.

CH17SEL

Bit 23: CH17SEL.

CH18SEL

Bit 24: CH18SEL.

CDR

Common regular data register for dual mode

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST
r
Toggle fields

RDATA_MST

Bits 0-15: RDATA_MST.

RDATA_SLV

Bits 16-31: RDATA_SLV.

CDR2

Common regular data register for dual mode

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_ALT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_ALT
r
Toggle fields

RDATA_ALT

Bits 0-31: RDATA_ALT.

AXIMC_Mx

0x57042024: AXIMC_Mx

15/76 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 M0_FN_MOD2
0xdc M0_READ_QOS
0xe0 M0_FN_MOD
0xe4 M0_WRITE_QOS
0x1000 M1_FN_MOD2
0x10dc M1_READ_QOS
0x10e0 M1_WRITE_QOS
0x10e4 M1_FN_MOD
0x1fd0 PERIPH_ID_4
0x1fd4 PERIPH_ID_5
0x1fd8 PERIPH_ID_6
0x1fdc PERIPH_ID_7
0x1fe0 PERIPH_ID_0
0x1fe4 PERIPH_ID_1
0x1fe8 PERIPH_ID_2
0x1fec PERIPH_ID_3
0x1ff0 COMP_ID_0
0x1ff4 COMP_ID_1
0x1ff8 COMP_ID_2
0x1ffc COMP_ID_3
0x2000 M2_FN_MOD2
0x20dc M2_READ_QOS
0x20e0 M2_WRITE_QOS
0x20e4 M2_FN_MOD
0x3000 M5_FN_MOD2
0x30dc M5_READ_QOS
0x30e0 M5_WRITE_QOS
0x30e4 M5_FN_MOD
0x40dc M3_READ_QOS
0x40e0 M3_WRITE_QOS
0x40e4 M3_FN_MOD
0x50dc M7_READ_QOS
0x50e0 M7_WRITE_QOS
0x50e4 M7_FN_MOD
0x60dc M8_READ_QOS
0x60e0 M8_WRITE_QOS
0x60e4 M8_FN_MOD
0x8000 M4_FN_MOD2
0x80dc M4_READ_QOS
0x80e0 M4_WRITE_QOS
0x80e4 M4_FN_MOD
0x90dc M9_READ_QOS
0x90e0 M9_WRITE_QOS
0x90e4 M9_FN_MOD
0xa0dc M10_READ_QOS
0xa0e0 M10_WRITE_QOS
0xa0e4 M10_FN_MOD
0xb000 M6_FN_MOD2
0xb0dc M6_READ_QOS
0xb0e0 M6_WRITE_QOS
0xb0e4 M6_FN_MOD
0x42028 M0_FN_MOD_AHB
0x43028 M1_FN_MOD_AHB
0x44028 M2_FN_MOD_AHB
0x45028 M5_FN_MOD_AHB
0x4a02c FN_MOD_LB
0x4d028 M6_FN_MOD_AHB
Toggle registers

M0_FN_MOD2

AXIMC master 0 packing functionality register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: BYPASS_MERGE.

M0_READ_QOS

AXIMC master 0 read priority register

Offset: 0xdc, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M0_FN_MOD

AXIMC master 0 issuing capability override functionality register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M0_WRITE_QOS

AXIMC master 0 write priority register

Offset: 0xe4, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M1_FN_MOD2

AXIMC master 1 packing functionality register

Offset: 0x1000, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: BYPASS_MERGE.

M1_READ_QOS

AXIMC master 1 read priority register

Offset: 0x10dc, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M1_WRITE_QOS

AXIMC master 1 write priority register

Offset: 0x10e0, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M1_FN_MOD

AXIMC master 1 issuing capability override functionality register

Offset: 0x10e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

PERIPH_ID_4

AXIMC peripheral ID4 register

Offset: 0x1fd0, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K4COUNT
r 		JEP106CON
r
Toggle fields

JEP106CON

Bits 0-3: JEP106CON.

K4COUNT

Bits 4-7: K4COUNT.

PERIPH_ID_5

AXIMC peripheral ID5 register

Offset: 0x1fd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH_ID_5
r
Toggle fields

PERIPH_ID_5

Bits 0-7: PERIPH_ID_5.

PERIPH_ID_6

AXIMC peripheral ID6 register

Offset: 0x1fd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH_ID_6
r
Toggle fields

PERIPH_ID_6

Bits 0-7: PERIPH_ID_6.

PERIPH_ID_7

AXIMC peripheral ID7 register

Offset: 0x1fdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH_ID_7
r
Toggle fields

PERIPH_ID_7

Bits 0-7: PERIPH_ID_7.

PERIPH_ID_0

AXIMC peripheral ID0 register

Offset: 0x1fe0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH_ID_0
r
Toggle fields

PERIPH_ID_0

Bits 0-7: PERIPH_ID_0.

PERIPH_ID_1

AXIMC peripheral ID1 register

Offset: 0x1fe4, size: 32, reset: 0x000000B4, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH_ID_1
r
Toggle fields

PERIPH_ID_1

Bits 0-7: PERIPH_ID_1.

PERIPH_ID_2

AXIMC peripheral ID2 register

Offset: 0x1fe8, size: 32, reset: 0x0000003B, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PERIPH_ID_2
r
Toggle fields

PERIPH_ID_2

Bits 0-7: PERIPH_ID_2.

PERIPH_ID_3

AXIMC peripheral ID3 register

Offset: 0x1fec, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_AND
r 		CUST_MOD_NUM
r
Toggle fields

CUST_MOD_NUM

Bits 0-3: CUST_MOD_NUM.

REV_AND

Bits 4-7: REV_AND.

COMP_ID_0

AXIMC component ID0 register

Offset: 0x1ff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-7: PREAMBLE.

COMP_ID_1

AXIMC component ID1 register

Offset: 0x1ff4, size: 32, reset: 0x000000F0, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLASS
r 		PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-3: PREAMBLE.

CLASS

Bits 4-7: CLASS.

COMP_ID_2

AXIMC component ID2 register

Offset: 0x1ff8, size: 32, reset: 0x00000005, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-7: PREAMBLE.

COMP_ID_3

AXIMC component ID3 register

Offset: 0x1ffc, size: 32, reset: 0x000000B1, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREAMBLE
r
Toggle fields

PREAMBLE

Bits 0-7: PREAMBLE.

M2_FN_MOD2

AXIMC master 2 packing functionality register

Offset: 0x2000, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: BYPASS_MERGE.

M2_READ_QOS

AXIMC master 2 read priority register

Offset: 0x20dc, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M2_WRITE_QOS

AXIMC master 2 write priority register

Offset: 0x20e0, size: 32, reset: 0x00000006, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M2_FN_MOD

AXIMC master 2 issuing capability override functionality register

Offset: 0x20e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M5_FN_MOD2

AXIMC master 5 packing functionality register

Offset: 0x3000, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: BYPASS_MERGE.

M5_READ_QOS

AXIMC master 5 read priority register

Offset: 0x30dc, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M5_WRITE_QOS

AXIMC master 5 write priority register

Offset: 0x30e0, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M5_FN_MOD

AXIMC master 5 issuing capability override functionality register

Offset: 0x30e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M3_READ_QOS

AXIMC master 3 read priority register

Offset: 0x40dc, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M3_WRITE_QOS

AXIMC master 3 write priority register

Offset: 0x40e0, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M3_FN_MOD

AXIMC master 3 packing functionality register

Offset: 0x40e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M7_READ_QOS

AXIMC master 7 read priority register

Offset: 0x50dc, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M7_WRITE_QOS

AXIMC master 7 write priority register

Offset: 0x50e0, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M7_FN_MOD

AXIMC master 7 issuing capability override functionality register

Offset: 0x50e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M8_READ_QOS

AXIMC master 8 read priority register

Offset: 0x60dc, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M8_WRITE_QOS

AXIMC master 8 write priority register

Offset: 0x60e0, size: 32, reset: 0x00000008, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M8_FN_MOD

AXIMC master 8 issuing capability override functionality register

Offset: 0x60e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M4_FN_MOD2

AXIMC master 4 packing functionality register

Offset: 0x8000, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: BYPASS_MERGE.

M4_READ_QOS

AXIMC master 4 read priority register

Offset: 0x80dc, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M4_WRITE_QOS

AXIMC master 4 write priority register

Offset: 0x80e0, size: 32, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M4_FN_MOD

AXIMC master 4 packing functionality register

Offset: 0x80e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M9_READ_QOS

AXIMC master 9 read priority register

Offset: 0x90dc, size: 32, reset: 0x0000000B, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M9_WRITE_QOS

AXIMC master 9 write priority register

Offset: 0x90e0, size: 32, reset: 0x0000000B, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M9_FN_MOD

AXIMC master 9 issuing capability override functionality register

Offset: 0x90e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M10_READ_QOS

AXIMC master 10 read priority register

Offset: 0xa0dc, size: 32, reset: 0x0000000B, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M10_WRITE_QOS

AXIMC master 10 write priority register

Offset: 0xa0e0, size: 32, reset: 0x0000000B, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M10_FN_MOD

AXIMC master 10 issuing capability override functionality register

Offset: 0xa0e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M6_FN_MOD2

AXIMC master 6 packing functionality register

Offset: 0xb000, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPASS_MERGE
rw
Toggle fields

BYPASS_MERGE

Bit 0: BYPASS_MERGE.

M6_READ_QOS

AXIMC master 6 read priority register

Offset: 0xb0dc, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR_QOS
rw
Toggle fields

AR_QOS

Bits 0-3: AR_QOS.

M6_WRITE_QOS

AXIMC master 6 write priority register

Offset: 0xb0e0, size: 32, reset: 0x00000004, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AW_QOS
rw
Toggle fields

AW_QOS

Bits 0-3: AW_QOS.

M6_FN_MOD

AXIMC master 6 issuing capability override functionality register

Offset: 0xb0e4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITE_ISS_OVERRIDE
rw 		READ_ISS_OVERRIDE
rw
Toggle fields

READ_ISS_OVERRIDE

Bit 0: READ_ISS_OVERRIDE.

WRITE_ISS_OVERRIDE

Bit 1: WRITE_ISS_OVERRIDE.

M0_FN_MOD_AHB

AXIMC master 0 AHB conversion override functionality register

Offset: 0x42028, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw 		RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: RD_INC_OVERRIDE.

WR_INC_OVERRIDE

Bit 1: WR_INC_OVERRIDE.

M1_FN_MOD_AHB

AXIMC master 1 AHB conversion override functionality register

Offset: 0x43028, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw 		RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: RD_INC_OVERRIDE.

WR_INC_OVERRIDE

Bit 1: WR_INC_OVERRIDE.

M2_FN_MOD_AHB

AXIMC master 2 AHB conversion override functionality register

Offset: 0x44028, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw 		RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: RD_INC_OVERRIDE.

WR_INC_OVERRIDE

Bit 1: WR_INC_OVERRIDE.

M5_FN_MOD_AHB

AXIMC master 5 AHB conversion override functionality register

Offset: 0x45028, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw 		RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: RD_INC_OVERRIDE.

WR_INC_OVERRIDE

Bit 1: WR_INC_OVERRIDE.

FN_MOD_LB

AXIMC long burst capability inhibition register

Offset: 0x4a02c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FN_MOD_LB
rw
Toggle fields

FN_MOD_LB

Bit 0: FN_MOD_LB.

M6_FN_MOD_AHB

AXIMC master 6 AHB conversion override functionality register

Offset: 0x4d028, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_INC_OVERRIDE
rw 		RD_INC_OVERRIDE
rw
Toggle fields

RD_INC_OVERRIDE

Bit 0: RD_INC_OVERRIDE.

WR_INC_OVERRIDE

Bit 1: WR_INC_OVERRIDE.

BSEC

0x5c005000: BSEC2

24/153 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 OTP_CONFIG
0x4 OTP_CONTROL
0x8 OTP_WRDATA
0xc OTP_STATUS
0x10 OTP_LOCK
0x14 DENABLE
0x1c OTP_DISTURBED0
0x20 OTP_DISTURBED1
0x24 OTP_DISTURBED2
0x34 OTP_ERROR0
0x38 OTP_ERROR1
0x3c OTP_ERROR2
0x4c OTP_WRLOCK0
0x50 OTP_WRLOCK1
0x54 OTP_WRLOCK2
0x64 OTP_SPLOCK0
0x68 OTP_SPLOCK1
0x6c OTP_SPLOCK2
0x7c OTP_SWLOCK0
0x80 OTP_SWLOCK1
0x84 OTP_SWLOCK2
0x94 OTP_SRLOCK0
0x98 OTP_SRLOCK1
0x9c OTP_SRLOCK2
0xac JTAGIN
0xb0 JTAGOUT
0xb4 SCRATCH
0x200 OTP_DATA0
0x204 OTP_DATA1
0x208 OTP_DATA2
0x20c OTP_DATA3
0x210 OTP_DATA4
0x214 OTP_DATA5
0x218 OTP_DATA6
0x21c OTP_DATA7
0x220 OTP_DATA8
0x224 OTP_DATA9
0x228 OTP_DATA10
0x22c OTP_DATA11
0x230 OTP_DATA12
0x234 OTP_DATA13
0x238 OTP_DATA14
0x23c OTP_DATA15
0x240 OTP_DATA16
0x244 OTP_DATA17
0x248 OTP_DATA18
0x24c OTP_DATA19
0x250 OTP_DATA20
0x254 OTP_DATA21
0x258 OTP_DATA22
0x25c OTP_DATA23
0x260 OTP_DATA24
0x264 OTP_DATA25
0x268 OTP_DATA26
0x26c OTP_DATA27
0x270 OTP_DATA28
0x274 OTP_DATA29
0x278 OTP_DATA30
0x27c OTP_DATA31
0x280 OTP_DATA32
0x284 OTP_DATA33
0x288 OTP_DATA34
0x28c OTP_DATA35
0x290 OTP_DATA36
0x294 OTP_DATA37
0x298 OTP_DATA38
0x29c OTP_DATA39
0x2a0 OTP_DATA40
0x2a4 OTP_DATA41
0x2a8 OTP_DATA42
0x2ac OTP_DATA43
0x2b0 OTP_DATA44
0x2b4 OTP_DATA45
0x2b8 OTP_DATA46
0x2bc OTP_DATA47
0x2c0 OTP_DATA48
0x2c4 OTP_DATA49
0x2c8 OTP_DATA50
0x2cc OTP_DATA51
0x2d0 OTP_DATA52
0x2d4 OTP_DATA53
0x2d8 OTP_DATA54
0x2dc OTP_DATA55
0x2e0 OTP_DATA56
0x2e4 OTP_DATA57
0x2e8 OTP_DATA58
0x2ec OTP_DATA59
0x2f0 OTP_DATA60
0x2f4 OTP_DATA61
0x2f8 OTP_DATA62
0x2fc OTP_DATA63
0x300 OTP_DATA64
0x304 OTP_DATA65
0x308 OTP_DATA66
0x30c OTP_DATA67
0x310 OTP_DATA68
0x314 OTP_DATA69
0x318 OTP_DATA70
0x31c OTP_DATA71
0x320 OTP_DATA72
0x324 OTP_DATA73
0x328 OTP_DATA74
0x32c OTP_DATA75
0x330 OTP_DATA76
0x334 OTP_DATA77
0x338 OTP_DATA78
0x33c OTP_DATA79
0x340 OTP_DATA80
0x344 OTP_DATA81
0x348 OTP_DATA82
0x34c OTP_DATA83
0x350 OTP_DATA84
0x354 OTP_DATA85
0x358 OTP_DATA86
0x35c OTP_DATA87
0x360 OTP_DATA88
0x364 OTP_DATA89
0x368 OTP_DATA90
0x36c OTP_DATA91
0x370 OTP_DATA92
0x374 OTP_DATA93
0x378 OTP_DATA94
0x37c OTP_DATA95
0xff0 HWCFGR
0xff4 VERR
0xff8 IPIDR
0xffc SIDR
Toggle registers

OTP_CONFIG

BSEC OTP configuration register

Offset: 0x0, size: 32, reset: 0x0000000E, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREAD
rw 		PRGWIDTH
rw 		FRC
rw 		PWRUP
rw
Toggle fields

PWRUP

Bit 0: PWRUP.

FRC

Bits 1-2: FRC.

PRGWIDTH

Bits 3-6: PRGWIDTH.

TREAD

Bits 7-8: TREAD.

OTP_CONTROL

BSEC OTP control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
rw 		PROG
rw 		ADDR
rw
Toggle fields

ADDR

Bits 0-6: ADDR.

PROG

Bit 8: PROG.

LOCK

Bit 9: LOCK.

OTP_WRDATA

BSEC OTP write data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRDATA
rw
Toggle fields

WRDATA

Bits 0-31: WRDATA.

OTP_STATUS

BSEC OTP status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIST2LOCK
r 		BIST1LOCK
r 		PWRON
r 		PROGFAIL
r 		BUSY
r 		INVALID
r 		FULLDBG
r 		SECURE
r
Toggle fields

SECURE

Bit 0: SECURE.

FULLDBG

Bit 1: FULLDBG.

INVALID

Bit 2: INVALID.

BUSY

Bit 3: BUSY.

PROGFAIL

Bit 4: PROGFAIL.

PWRON

Bit 5: PWRON.

BIST1LOCK

Bit 6: BIST1LOCK.

BIST2LOCK

Bit 7: BIST2LOCK.

OTP_LOCK

BSEC OTP lock configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPLOCK
rw 		DENREG
rw 		ROMLOCK
rw 		OTP
rw
Toggle fields

OTP

Bit 0: OTP.

ROMLOCK

Bit 1: ROMLOCK.

DENREG

Bit 2: DENREG.

GPLOCK

Bit 4: GPLOCK.

DENABLE

reset value depends on OTP secure mode according toTable18: BSEC_DENABLE default values after reset on page181.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBGSWENABLE
rw 		CFGSDISABLE
rw 		CP15SDISABLE
rw 		SPNIDEN
rw 		SPIDEN
rw 		HDPEN
rw 		DEVICEEN
rw 		NIDEN
rw 		DBGEN
rw 		DFTEN
rw
Toggle fields

DFTEN

Bit 0: DFTEN.

DBGEN

Bit 1: DBGEN.

NIDEN

Bit 2: NIDEN.

DEVICEEN

Bit 3: DEVICEEN.

HDPEN

Bit 4: HDPEN.

SPIDEN

Bit 5: SPIDEN.

SPNIDEN

Bit 6: SPNIDEN.

CP15SDISABLE

Bits 7-8: CP15SDISABLE.

CFGSDISABLE

Bit 9: CFGSDISABLE.

DBGSWENABLE

Bit 10: DBGSWENABLE.

OTP_DISTURBED0

BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS
r
Toggle fields

DIS

Bits 0-31: DIS.

OTP_DISTURBED1

BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS
r
Toggle fields

DIS

Bits 0-31: DIS.

OTP_DISTURBED2

BSEC_OTP_DISTURBED0 is used to report disturbed state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP). BSEC_OTP_DISTURBED1 is used to report disturbed state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_DISTURBED2 is used to report disturbed state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS
r
Toggle fields

DIS

Bits 0-31: DIS.

OTP_ERROR0

BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC.

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR
r
Toggle fields

ERR

Bits 0-31: ERR.

OTP_ERROR1

BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR
r
Toggle fields

ERR

Bits 0-31: ERR.

OTP_ERROR2

BSEC_OTP_ERROR0 is used to report error state of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 (lower 1Kbits OTP which are protected by 2:1 redundancy). BSEC_OTP_ERROR1 is used to report error state of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 which are protected by 6-bit ECC. BSEC_OTP_ERROR2 is used to report error state of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 which are protected by 6-bit ECC.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERR
r
Toggle fields

ERR

Bits 0-31: ERR.

OTP_WRLOCK0

BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178).

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRLOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRLOCK
r
Toggle fields

WRLOCK

Bits 0-31: WRLOCK.

OTP_WRLOCK1

BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178).

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRLOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRLOCK
r
Toggle fields

WRLOCK

Bits 0-31: WRLOCK.

OTP_WRLOCK2

BSEC_OTP_WLOCK0 is used to report permanent write lock of BSEC_OTP_DATA0 to BSEC_OTP_DATA31. BSEC_OTP_WLOCK1 is used to report permanent write lock of BSEC_OTP_DATA32 to BSEC_OTP_DATA63. BSEC_OTP_WLOCK2 is used to report permanent write lock of BSEC_OTP_DATA64 to BSEC_OTP_DATA95. Permanent write lock requires a programming sequence to lock a word (see section:Section3.3.6: OTP operations on page178).

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRLOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRLOCK
r
Toggle fields

WRLOCK

Bits 0-31: WRLOCK.

OTP_SPLOCK0

BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPLOCK
rw
Toggle fields

SPLOCK

Bits 0-31: SPLOCK.

OTP_SPLOCK1

BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored.

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPLOCK
rw
Toggle fields

SPLOCK

Bits 0-31: SPLOCK.

OTP_SPLOCK2

BSEC_OTP_SPLOCK0 is used to lock the programming of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset BSEC_OTP_SPLOCK1 is used to lock the programming of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset BSEC_OTP_SPLOCK2 is used to lock the programming of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset Attempt to sticky program locked OTP word are silently ignored.

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPLOCK
rw
Toggle fields

SPLOCK

Bits 0-31: SPLOCK.

OTP_SWLOCK0

BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented.

Offset: 0x7c, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWLOCK
rw
Toggle fields

SWLOCK

Bits 0-31: SWLOCK.

OTP_SWLOCK1

BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented.

Offset: 0x80, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWLOCK
rw
Toggle fields

SWLOCK

Bits 0-31: SWLOCK.

OTP_SWLOCK2

BSEC_OTP_SWLOCK0 is used to prevent writing to BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SWLOCK1 is used to prevent writing to BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SWLOCK2 is used to prevent writing to BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Write to shadow write locked BSEC_OTP_DATA word are silently ignored. Writing to OTP word 0 shadow is always prevented.

Offset: 0x84, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWLOCK
rw
Toggle fields

SWLOCK

Bits 0-31: SWLOCK.

OTP_SRLOCK0

BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRLOCK
rw
Toggle fields

SRLOCK

Bits 0-31: SRLOCK.

OTP_SRLOCK1

BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect.

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRLOCK
rw
Toggle fields

SRLOCK

Bits 0-31: SRLOCK.

OTP_SRLOCK2

BSEC_OTP_SRLOCK0 is used to prevent reloading of BSEC_OTP_DATA0 to BSEC_OTP_DATA31 until next system-reset. BSEC_OTP_SRLOCK1 is used to prevent reloading of BSEC_OTP_DATA32 to BSEC_OTP_DATA63 until next system-reset. BSEC_OTP_SRLOCK2 is used to prevent reloading of BSEC_OTP_DATA64 to BSEC_OTP_DATA95 until next system-reset. Setting SRLOCK bits or attempt to reload a locked OTP do not clear the corresponding BSEC_OTP_DATAx shadow register. BSEC_OTP_SRLOCK0 bit 0 is controlled by hardware according to fuse_ok, writing to this bit has no effect.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRLOCK
rw
Toggle fields

SRLOCK

Bits 0-31: SRLOCK.

JTAGIN

BSEC JTAG input register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
r
Toggle fields

DATA

Bits 0-15: DATA.

JTAGOUT

BSEC JTAG output register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-15: DATA.

SCRATCH

BSEC scratch register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA0

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA1

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA2

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA3

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA4

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA5

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA6

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA7

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA8

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA9

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA10

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA11

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA12

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA13

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA14

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x238, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA15

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x23c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA16

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x240, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA17

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x244, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA18

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x248, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA19

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x24c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA20

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA21

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA22

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA23

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA24

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA25

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA26

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA27

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA28

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA29

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA30

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x278, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA31

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA32

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA33

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA34

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA35

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA36

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA37

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA38

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA39

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA40

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA41

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA42

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA43

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA44

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA45

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA46

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA47

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA48

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA49

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA50

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA51

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA52

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA53

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA54

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA55

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA56

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA57

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA58

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA59

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA60

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA61

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA62

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2f8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA63

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x2fc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA64

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA65

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA66

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA67

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA68

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA69

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA70

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA71

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA72

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA73

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA74

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA75

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA76

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA77

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA78

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA79

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA80

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA81

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA82

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA83

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA84

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA85

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA86

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x358, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA87

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x35c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA88

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x360, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA89

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA90

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA91

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x36c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA92

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA93

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA94

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x378, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

OTP_DATA95

Several OTP directly impact BSEC behavior, such as: BSEC_OTP_DATA0[6:0] (see Table15: OTP modes definition on page175) BSEC_OTP_DATA1, 16 lsb used for SoC features control BSEC_OTP_DATA2, 2 lsb used to control the RAM handling The reset value depends on the actual OTP programmed value and the OTP mode.

Offset: 0x37c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

HWCFGR

BSEC hardware configuration register

Offset: 0xff0, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_USE
r 		SIZE
r
Toggle fields

SIZE

Bits 0-3: SIZE.

ECC_USE

Bits 4-7: ECC_USE.

VERR

BSEC version register

Offset: 0xff4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

BSEC identification register

Offset: 0xff8, size: 32, reset: 0x00100032, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

BSEC size identification register

Offset: 0xffc, size: 32, reset: 0xA3C5DD04, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

CCU

0x44010000: CCU

10/21 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 CCFG
0x8 CSTAT
0xc CWD
0x10 IR
0x14 IE
Toggle registers

CREL

Clock calibration unit core release register

Offset: 0x0, size: 32, reset: 0x11141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r 		STEP
r 		SUBSTEP
r 		YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r 		DAY
r
Toggle fields

DAY

Bits 0-7: DAY.

MON

Bits 8-15: MON.

YEAR

Bits 16-19: YEAR.

SUBSTEP

Bits 20-23: SUBSTEP.

STEP

Bits 24-27: STEP.

REL

Bits 28-31: REL.

CCFG

Calibration configuration register

Offset: 0x4, size: 32, reset: 0x00000004, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWR
rw 		CDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCPM
rw 		CFL
rw 		BCC
rw 		TQBT
rw
Toggle fields

TQBT

Bits 0-4: TQBT.

BCC

Bit 6: BCC.

CFL

Bit 7: CFL.

OCPM

Bits 8-15: OCPM.

CDIV

Bits 16-19: CDIV.

SWR

Bit 31: SWR.

CSTAT

Calibration status register

Offset: 0x8, size: 32, reset: 0x0203FFFF, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CALS
r 		TQC
r 		OCPC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCPC
r
Toggle fields

OCPC

Bits 0-17: OCPC.

TQC

Bits 18-28: TQC.

CALS

Bits 30-31: CALS.

CWD

The calibration watchdog is started after the first falling edge when the calibration FSM is in state Not_Calibrated (CCU_CSTAT.CALS = 00). In this state the calibration watchdog monitors the message received. In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM stays in state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When in state Basic_Calibrated (CCU_CSTAT.CALS = 01), the calibration watchdog is restarted with each received message . In case no message was received until the calibration watchdog has counted down to 0, the calibration FSM returns to state Not_Calibrated (CCU_CSTAT.CALS = 00), the counter is reloaded with FDCAN_RWD.WDC and basic calibration is restarted after the next falling edge. When a quartz message is received, state Precision_Calibrated (CCU_CSTAT.CALS = 10) is entered and the calibration watchdog is restarted. In this state the calibration watchdog monitors the quartz message received input. In case no message from a quartz controlled node is received by the attached TTCAN until the calibration watchdog has counted down to 0, the calibration FSM transits back to state Basic_Calibrated (CCU_CSTAT.CALS = 01). The signal is active when the CAN protocol engine on the attached TTCAN is started i.e. when the INIT bit is reset. A calibration watchdog event also sets interrupt flag CCU_IR.CWE. If enabled by CCU_IE.CWEE, interrupt line is activated (set to high). Interrupt line remains active until interrupt flag CCU_IR.CWE is reset.

Offset: 0xc, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDC
rw
Toggle fields

WDC

Bits 0-15: WDC.

WDV

Bits 16-31: WDV.

IR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of CCU_IE controls whether an interrupt is generated or not.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSC
rw 		CWE
rw
Toggle fields

CWE

Bit 0: CWE.

CSC

Bit 1: CSC.

IE

The settings in the CU interrupt enable register determine whether a status change in the CU interrupt register will be signaled on an interrupt line.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCE
rw 		CWEE
rw
Toggle fields

CWEE

Bit 0: CWEE.

CSCE

Bit 1: CSCE.

CRC1

0x58009000: CRC1

0/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

CRC data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: DR.

IDR

CRC independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-31: IDR.

CR

CRC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
rw
Toggle fields

RESET

Bit 0: RESET.

POLYSIZE

Bits 3-4: POLYSIZE.

REV_IN

Bits 5-6: REV_IN.

REV_OUT

Bit 7: REV_OUT.

INIT

CRC initial value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle fields

CRC_INIT

Bits 0-31: CRC_INIT.

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle fields

POL

Bits 0-31: POL.

CRC2

0x4c004000: CRC1

0/8 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DR
0x4 IDR
0x8 CR
0x10 INIT
0x14 POL
Toggle registers

DR

CRC data register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
rw
Toggle fields

DR

Bits 0-31: DR.

IDR

CRC independent data register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR
rw
Toggle fields

IDR

Bits 0-31: IDR.

CR

CRC control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_OUT
rw 		REV_IN
rw 		POLYSIZE
rw 		RESET
rw
Toggle fields

RESET

Bit 0: RESET.

POLYSIZE

Bits 3-4: POLYSIZE.

REV_IN

Bits 5-6: REV_IN.

REV_OUT

Bit 7: REV_OUT.

INIT

CRC initial value

Offset: 0x10, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRC_INIT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC_INIT
rw
Toggle fields

CRC_INIT

Bits 0-31: CRC_INIT.

POL

CRC polynomial

Offset: 0x14, size: 32, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
POL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POL
rw
Toggle fields

POL

Bits 0-31: POL.

CRYP1

0x54001000: CRYP1

17/183 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DIN
0xc DOUT
0x10 DMACR
0x14 IMSCR
0x18 RISR
0x1c MISR
0x20 K0LR
0x24 K0RR
0x28 K1LR
0x2c K1RR
0x30 K2LR
0x34 K2RR
0x38 K3LR
0x3c K3RR
0x40 IV0LR
0x44 IV0RR
0x48 IV1LR
0x4c IV1RR
0x50 CSGCMCCM0R
0x54 CSGCMCCM1R
0x58 CSGCMCCM2R
0x5c CSGCMCCM3R
0x60 CSGCMCCM4R
0x64 CSGCMCCM5R
0x68 CSGCMCCM6R
0x6c CSGCMCCM7R
0x70 CSGCM0R
0x74 CSGCM1R
0x78 CSGCM2R
0x7c CSGCM3R
0x80 CSGCM4R
0x84 CSGCM5R
0x88 CSGCM6R
0x8c CSGCM7R
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc MID
Toggle registers

CR

CRYP control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw 		ALGOMODE3
rw 		GCM_CCMPH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRYPEN
rw 		FFLUSH
w 		KEYSIZE
rw 		DATATYPE
rw 		ALGOMODE
rw 		ALGODIR
rw
Toggle fields

ALGODIR

Bit 2: ALGODIR.

ALGOMODE

Bits 3-5: ALGOMODE.

DATATYPE

Bits 6-7: DATATYPE.

KEYSIZE

Bits 8-9: KEYSIZE.

FFLUSH

Bit 14: FFLUSH.

CRYPEN

Bit 15: CRYPEN.

GCM_CCMPH

Bits 16-17: GCM_CCMPH.

ALGOMODE3

Bit 19: ALGOMODE3.

NPBLB

Bits 20-23: NPBLB.

SR

CRYP status register

Offset: 0x4, size: 32, reset: 0x00000003, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		OFFU
r 		OFNE
r 		IFNF
r 		IFEM
r
Toggle fields

IFEM

Bit 0: IFEM.

IFNF

Bit 1: IFNF.

OFNE

Bit 2: OFNE.

OFFU

Bit 3: OFFU.

BUSY

Bit 4: BUSY.

DIN

The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: DATAIN.

DOUT

The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUT
r
Toggle fields

DATAOUT

Bits 0-31: DATAOUT.

DMACR

CRYP DMA control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOEN
rw 		DIEN
rw
Toggle fields

DIEN

Bit 0: DIEN.

DOEN

Bit 1: DOEN.

IMSCR

The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTIM
rw 		INIM
rw
Toggle fields

INIM

Bit 0: INIM.

OUTIM

Bit 1: OUTIM.

RISR

The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.

Offset: 0x18, size: 32, reset: 0x00000001, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTRIS
r 		INRIS
r
Toggle fields

INRIS

Bit 0: INRIS.

OUTRIS

Bit 1: OUTRIS.

MISR

The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTMIS
r 		INMIS
r
Toggle fields

INMIS

Bit 0: INMIS.

OUTMIS

Bit 1: OUTMIS.

K0LR

CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K0RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K1LR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K1RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K2LR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K2RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K3LR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K3RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

IV0LR

The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV0
rw 		IV1
rw 		IV2
rw 		IV3
rw 		IV4
rw 		IV5
rw 		IV6
rw 		IV7
rw 		IV8
rw 		IV9
rw 		IV10
rw 		IV11
rw 		IV12
rw 		IV13
rw 		IV14
rw 		IV15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV16
rw 		IV17
rw 		IV18
rw 		IV19
rw 		IV20
rw 		IV21
rw 		IV22
rw 		IV23
rw 		IV24
rw 		IV25
rw 		IV26
rw 		IV27
rw 		IV28
rw 		IV29
rw 		IV30
rw 		IV31
rw
Toggle fields

IV31

Bit 0: IV31.

IV30

Bit 1: IV30.

IV29

Bit 2: IV29.

IV28

Bit 3: IV28.

IV27

Bit 4: IV27.

IV26

Bit 5: IV26.

IV25

Bit 6: IV25.

IV24

Bit 7: IV24.

IV23

Bit 8: IV23.

IV22

Bit 9: IV22.

IV21

Bit 10: IV21.

IV20

Bit 11: IV20.

IV19

Bit 12: IV19.

IV18

Bit 13: IV18.

IV17

Bit 14: IV17.

IV16

Bit 15: IV16.

IV15

Bit 16: IV15.

IV14

Bit 17: IV14.

IV13

Bit 18: IV13.

IV12

Bit 19: IV12.

IV11

Bit 20: IV11.

IV10

Bit 21: IV10.

IV9

Bit 22: IV9.

IV8

Bit 23: IV8.

IV7

Bit 24: IV7.

IV6

Bit 25: IV6.

IV5

Bit 26: IV5.

IV4

Bit 27: IV4.

IV3

Bit 28: IV3.

IV2

Bit 29: IV2.

IV1

Bit 30: IV1.

IV0

Bit 31: IV0.

IV0RR

Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV32
rw 		IV33
rw 		IV34
rw 		IV35
rw 		IV36
rw 		IV37
rw 		IV38
rw 		IV39
rw 		IV40
rw 		IV41
rw 		IV42
rw 		IV43
rw 		IV44
rw 		IV45
rw 		IV46
rw 		IV47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV48
rw 		IV49
rw 		IV50
rw 		IV51
rw 		IV52
rw 		IV53
rw 		IV54
rw 		IV55
rw 		IV56
rw 		IV57
rw 		IV58
rw 		IV59
rw 		IV60
rw 		IV61
rw 		IV62
rw 		IV63
rw
Toggle fields

IV63

Bit 0: IV63.

IV62

Bit 1: IV62.

IV61

Bit 2: IV61.

IV60

Bit 3: IV60.

IV59

Bit 4: IV59.

IV58

Bit 5: IV58.

IV57

Bit 6: IV57.

IV56

Bit 7: IV56.

IV55

Bit 8: IV55.

IV54

Bit 9: IV54.

IV53

Bit 10: IV53.

IV52

Bit 11: IV52.

IV51

Bit 12: IV51.

IV50

Bit 13: IV50.

IV49

Bit 14: IV49.

IV48

Bit 15: IV48.

IV47

Bit 16: IV47.

IV46

Bit 17: IV46.

IV45

Bit 18: IV45.

IV44

Bit 19: IV44.

IV43

Bit 20: IV43.

IV42

Bit 21: IV42.

IV41

Bit 22: IV41.

IV40

Bit 23: IV40.

IV39

Bit 24: IV39.

IV38

Bit 25: IV38.

IV37

Bit 26: IV37.

IV36

Bit 27: IV36.

IV35

Bit 28: IV35.

IV34

Bit 29: IV34.

IV33

Bit 30: IV33.

IV32

Bit 31: IV32.

IV1LR

Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV64
rw 		IV65
rw 		IV66
rw 		IV67
rw 		IV68
rw 		IV69
rw 		IV70
rw 		IV71
rw 		IV72
rw 		IV73
rw 		IV74
rw 		IV75
rw 		IV76
rw 		IV77
rw 		IV78
rw 		IV79
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV80
rw 		IV81
rw 		IV82
rw 		IV83
rw 		IV84
rw 		IV85
rw 		IV86
rw 		IV87
rw 		IV88
rw 		IV89
rw 		IV90
rw 		IV91
rw 		IV92
rw 		IV93
rw 		IV94
rw 		IV95
rw
Toggle fields

IV95

Bit 0: IV95.

IV94

Bit 1: IV94.

IV93

Bit 2: IV93.

IV92

Bit 3: IV92.

IV91

Bit 4: IV91.

IV90

Bit 5: IV90.

IV89

Bit 6: IV89.

IV88

Bit 7: IV88.

IV87

Bit 8: IV87.

IV86

Bit 9: IV86.

IV85

Bit 10: IV85.

IV84

Bit 11: IV84.

IV83

Bit 12: IV83.

IV82

Bit 13: IV82.

IV81

Bit 14: IV81.

IV80

Bit 15: IV80.

IV79

Bit 16: IV79.

IV78

Bit 17: IV78.

IV77

Bit 18: IV77.

IV76

Bit 19: IV76.

IV75

Bit 20: IV75.

IV74

Bit 21: IV74.

IV73

Bit 22: IV73.

IV72

Bit 23: IV72.

IV71

Bit 24: IV71.

IV70

Bit 25: IV70.

IV69

Bit 26: IV69.

IV68

Bit 27: IV68.

IV67

Bit 28: IV67.

IV66

Bit 29: IV66.

IV65

Bit 30: IV65.

IV64

Bit 31: IV64.

IV1RR

Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV96
rw 		IV97
rw 		IV98
rw 		IV99
rw 		IV100
rw 		IV101
rw 		IV102
rw 		IV103
rw 		IV104
rw 		IV105
rw 		IV106
rw 		IV107
rw 		IV108
rw 		IV109
rw 		IV110
rw 		IV111
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV112
rw 		IV113
rw 		IV114
rw 		IV115
rw 		IV116
rw 		IV117
rw 		IV118
rw 		IV119
rw 		IV120
rw 		IV121
rw 		IV122
rw 		IV123
rw 		IV124
rw 		IV125
rw 		IV126
rw 		IV127
rw
Toggle fields

IV127

Bit 0: IV127.

IV126

Bit 1: IV126.

IV125

Bit 2: IV125.

IV124

Bit 3: IV124.

IV123

Bit 4: IV123.

IV122

Bit 5: IV122.

IV121

Bit 6: IV121.

IV120

Bit 7: IV120.

IV119

Bit 8: IV119.

IV118

Bit 9: IV118.

IV117

Bit 10: IV117.

IV116

Bit 11: IV116.

IV115

Bit 12: IV115.

IV114

Bit 13: IV114.

IV113

Bit 14: IV113.

IV112

Bit 15: IV112.

IV111

Bit 16: IV111.

IV110

Bit 17: IV110.

IV109

Bit 18: IV109.

IV108

Bit 19: IV108.

IV107

Bit 20: IV107.

IV106

Bit 21: IV106.

IV105

Bit 22: IV105.

IV104

Bit 23: IV104.

IV103

Bit 24: IV103.

IV102

Bit 25: IV102.

IV101

Bit 26: IV101.

IV100

Bit 27: IV100.

IV99

Bit 28: IV99.

IV98

Bit 29: IV98.

IV97

Bit 30: IV97.

IV96

Bit 31: IV96.

CSGCMCCM0R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM0
rw
Toggle fields

CSGCMCCM0

Bits 0-31: CSGCMCCM0.

CSGCMCCM1R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM1
rw
Toggle fields

CSGCMCCM1

Bits 0-31: CSGCMCCM1.

CSGCMCCM2R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM2
rw
Toggle fields

CSGCMCCM2

Bits 0-31: CSGCMCCM2.

CSGCMCCM3R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM3
rw
Toggle fields

CSGCMCCM3

Bits 0-31: CSGCMCCM3.

CSGCMCCM4R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM4
rw
Toggle fields

CSGCMCCM4

Bits 0-31: CSGCMCCM4.

CSGCMCCM5R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM5
rw
Toggle fields

CSGCMCCM5

Bits 0-31: CSGCMCCM5.

CSGCMCCM6R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM6
rw
Toggle fields

CSGCMCCM6

Bits 0-31: CSGCMCCM6.

CSGCMCCM7R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM7
rw
Toggle fields

CSGCMCCM7

Bits 0-31: CSGCMCCM7.

CSGCM0R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM0
rw
Toggle fields

CSGCM0

Bits 0-31: CSGCM0.

CSGCM1R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM1
rw
Toggle fields

CSGCM1

Bits 0-31: CSGCM1.

CSGCM2R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM2
rw
Toggle fields

CSGCM2

Bits 0-31: CSGCM2.

CSGCM3R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM3
rw
Toggle fields

CSGCM3

Bits 0-31: CSGCM3.

CSGCM4R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM4
rw
Toggle fields

CSGCM4

Bits 0-31: CSGCM4.

CSGCM5R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM5
rw
Toggle fields

CSGCM5

Bits 0-31: CSGCM5.

CSGCM6R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM6
rw
Toggle fields

CSGCM6

Bits 0-31: CSGCM6.

CSGCM7R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM7
rw
Toggle fields

CSGCM7

Bits 0-31: CSGCM7.

HWCFGR

CRYP hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000131, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

VERR

CRYP HW Version Register

Offset: 0x3f4, size: 32, reset: 0x00000022, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VER
r
Toggle fields

VER

Bits 0-7: VER.

IPIDR

CRYP Identification

Offset: 0x3f8, size: 32, reset: 0x00170011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

MID

CRYP HW Magic ID

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MID
r
Toggle fields

MID

Bits 0-31: MID.

CRYP2

0x4c005000: CRYP1

17/183 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DIN
0xc DOUT
0x10 DMACR
0x14 IMSCR
0x18 RISR
0x1c MISR
0x20 K0LR
0x24 K0RR
0x28 K1LR
0x2c K1RR
0x30 K2LR
0x34 K2RR
0x38 K3LR
0x3c K3RR
0x40 IV0LR
0x44 IV0RR
0x48 IV1LR
0x4c IV1RR
0x50 CSGCMCCM0R
0x54 CSGCMCCM1R
0x58 CSGCMCCM2R
0x5c CSGCMCCM3R
0x60 CSGCMCCM4R
0x64 CSGCMCCM5R
0x68 CSGCMCCM6R
0x6c CSGCMCCM7R
0x70 CSGCM0R
0x74 CSGCM1R
0x78 CSGCM2R
0x7c CSGCM3R
0x80 CSGCM4R
0x84 CSGCM5R
0x88 CSGCM6R
0x8c CSGCM7R
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc MID
Toggle registers

CR

CRYP control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPBLB
rw 		ALGOMODE3
rw 		GCM_CCMPH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRYPEN
rw 		FFLUSH
w 		KEYSIZE
rw 		DATATYPE
rw 		ALGOMODE
rw 		ALGODIR
rw
Toggle fields

ALGODIR

Bit 2: ALGODIR.

ALGOMODE

Bits 3-5: ALGOMODE.

DATATYPE

Bits 6-7: DATATYPE.

KEYSIZE

Bits 8-9: KEYSIZE.

FFLUSH

Bit 14: FFLUSH.

CRYPEN

Bit 15: CRYPEN.

GCM_CCMPH

Bits 16-17: GCM_CCMPH.

ALGOMODE3

Bit 19: ALGOMODE3.

NPBLB

Bits 20-23: NPBLB.

SR

CRYP status register

Offset: 0x4, size: 32, reset: 0x00000003, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		OFFU
r 		OFNE
r 		IFNF
r 		IFEM
r
Toggle fields

IFEM

Bit 0: IFEM.

IFNF

Bit 1: IFNF.

OFNE

Bit 2: OFNE.

OFFU

Bit 3: OFFU.

BUSY

Bit 4: BUSY.

DIN

The CRYP_DIN register is the data input register. It is 32-bit wide. It is used to enter into the input FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DIN register is written to the data are pushed into the input FIFO. If CRYPEN = 1, when at least two 32-bit words in the DES/TDES mode have been pushed into the input FIFO (four words in the AES mode), and when at least two words are free in the output FIFO (four words in the AES mode), the CRYP engine starts an encrypting or decrypting process. When CRYP_DIN register is read: If CRYPEN = 0, the FIFO is popped, and then the data present in the Input FIFO are returned, from the oldest one (first reading) to the newest one (last reading). The IFEM flag must be checked before each read operation to make sure that the FIFO is not empty. if CRYPEN = 1, an undefined value is returned. After the CRYP_DIN register has been read once or several times, the FIFO must be flushed by setting the FFLUSH bit prior to processing new data.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: DATAIN.

DOUT

The CRYP_DOUT register is the data output register. It is read-only and 32-bit wide. It is used to retrieve from the output FIFO up to four 64-bit blocks (TDES) or two 128-bit blocks (AES) of plaintext (when encrypting) or ciphertext (when decrypting), one 32-bit word at a time. To fit different data sizes, the data can be swapped after processing by configuring the DATATYPE bits in the CRYP_CR register. Refer to Section39.3.16: CRYP data registers and data swapping for more details. When CRYP_DOUT register is read, the last data entered into the output FIFO (pointed to by the read pointer) is returned.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAOUT
r
Toggle fields

DATAOUT

Bits 0-31: DATAOUT.

DMACR

CRYP DMA control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOEN
rw 		DIEN
rw
Toggle fields

DIEN

Bit 0: DIEN.

DOEN

Bit 1: DOEN.

IMSCR

The CRYP_IMSCR register is the interrupt mask set or clear register. It is a read/write register. When a read operation is performed, this register gives the current value of the mask applied to the relevant interrupt. Writing 1 to the particular bit sets the mask, thus enabling the interrupt to be read. Writing 0 to this bit clears the corresponding mask. All the bits are cleared to 0 when the peripheral is reset.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTIM
rw 		INIM
rw
Toggle fields

INIM

Bit 0: INIM.

OUTIM

Bit 1: OUTIM.

RISR

The CRYP_RISR register is the raw interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current raw status of the corresponding interrupt, i.e. the interrupt information without taking CRYP_IMSCR mask into account. Write operations have no effect.

Offset: 0x18, size: 32, reset: 0x00000001, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTRIS
r 		INRIS
r
Toggle fields

INRIS

Bit 0: INRIS.

OUTRIS

Bit 1: OUTRIS.

MISR

The CRYP_MISR register is the masked interrupt status register. It is a read-only register. When a read operation is performed, this register gives the current masked status of the corresponding interrupt, i.e. the interrupt information taking CRYP_IMSCR mask into account. Write operations have no effect.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTMIS
r 		INMIS
r
Toggle fields

INMIS

Bit 0: INMIS.

OUTMIS

Bit 1: OUTMIS.

K0LR

CRYP key registers contain the cryptographic keys. In DES/TDES mode, the keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1) and named K1, K2 and K3 (K0 is not used). Each key consists of 56 information bits and 8 parity bits. In AES mode, the key is considered as a single 128, 192 or 256 bits long sequence K0K1K2...K127/191/255. The AES key is entered into the registers as follows: for AES-128: K0..K127 corresponds to b127..b0 (b255..b128 are not used), for AES-192: K0..K191 corresponds to b191..b0 (b255..b192 are not used), for AES-256: K0..K255 corresponds to b255..b0. In all cases key bit K0 is the leftmost bit in CRYP inner memory and register bit b0 is the rightmost bit in corresponding CRYP_KxLR key register. For more information refer to Section39.3.17: CRYP key registers. Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register)

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K0RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K1LR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K1RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K2LR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x30, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K2RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x34, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K3LR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x38, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

K3RR

Refer to Section39.6.9: CRYP key register 0L (CRYP_K0LR) for details.

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
K
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
K
w
Toggle fields

K

Bits 0-31: K.

IV0LR

The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES). For more information refer to Section39.3.18: CRYP initialization vector registers. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. Only CRYP_IV0(L/R) is used in DES/TDES. Write access to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register).

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV0
rw 		IV1
rw 		IV2
rw 		IV3
rw 		IV4
rw 		IV5
rw 		IV6
rw 		IV7
rw 		IV8
rw 		IV9
rw 		IV10
rw 		IV11
rw 		IV12
rw 		IV13
rw 		IV14
rw 		IV15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV16
rw 		IV17
rw 		IV18
rw 		IV19
rw 		IV20
rw 		IV21
rw 		IV22
rw 		IV23
rw 		IV24
rw 		IV25
rw 		IV26
rw 		IV27
rw 		IV28
rw 		IV29
rw 		IV30
rw 		IV31
rw
Toggle fields

IV31

Bit 0: IV31.

IV30

Bit 1: IV30.

IV29

Bit 2: IV29.

IV28

Bit 3: IV28.

IV27

Bit 4: IV27.

IV26

Bit 5: IV26.

IV25

Bit 6: IV25.

IV24

Bit 7: IV24.

IV23

Bit 8: IV23.

IV22

Bit 9: IV22.

IV21

Bit 10: IV21.

IV20

Bit 11: IV20.

IV19

Bit 12: IV19.

IV18

Bit 13: IV18.

IV17

Bit 14: IV17.

IV16

Bit 15: IV16.

IV15

Bit 16: IV15.

IV14

Bit 17: IV14.

IV13

Bit 18: IV13.

IV12

Bit 19: IV12.

IV11

Bit 20: IV11.

IV10

Bit 21: IV10.

IV9

Bit 22: IV9.

IV8

Bit 23: IV8.

IV7

Bit 24: IV7.

IV6

Bit 25: IV6.

IV5

Bit 26: IV5.

IV4

Bit 27: IV4.

IV3

Bit 28: IV3.

IV2

Bit 29: IV2.

IV1

Bit 30: IV1.

IV0

Bit 31: IV0.

IV0RR

Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV32
rw 		IV33
rw 		IV34
rw 		IV35
rw 		IV36
rw 		IV37
rw 		IV38
rw 		IV39
rw 		IV40
rw 		IV41
rw 		IV42
rw 		IV43
rw 		IV44
rw 		IV45
rw 		IV46
rw 		IV47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV48
rw 		IV49
rw 		IV50
rw 		IV51
rw 		IV52
rw 		IV53
rw 		IV54
rw 		IV55
rw 		IV56
rw 		IV57
rw 		IV58
rw 		IV59
rw 		IV60
rw 		IV61
rw 		IV62
rw 		IV63
rw
Toggle fields

IV63

Bit 0: IV63.

IV62

Bit 1: IV62.

IV61

Bit 2: IV61.

IV60

Bit 3: IV60.

IV59

Bit 4: IV59.

IV58

Bit 5: IV58.

IV57

Bit 6: IV57.

IV56

Bit 7: IV56.

IV55

Bit 8: IV55.

IV54

Bit 9: IV54.

IV53

Bit 10: IV53.

IV52

Bit 11: IV52.

IV51

Bit 12: IV51.

IV50

Bit 13: IV50.

IV49

Bit 14: IV49.

IV48

Bit 15: IV48.

IV47

Bit 16: IV47.

IV46

Bit 17: IV46.

IV45

Bit 18: IV45.

IV44

Bit 19: IV44.

IV43

Bit 20: IV43.

IV42

Bit 21: IV42.

IV41

Bit 22: IV41.

IV40

Bit 23: IV40.

IV39

Bit 24: IV39.

IV38

Bit 25: IV38.

IV37

Bit 26: IV37.

IV36

Bit 27: IV36.

IV35

Bit 28: IV35.

IV34

Bit 29: IV34.

IV33

Bit 30: IV33.

IV32

Bit 31: IV32.

IV1LR

Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV64
rw 		IV65
rw 		IV66
rw 		IV67
rw 		IV68
rw 		IV69
rw 		IV70
rw 		IV71
rw 		IV72
rw 		IV73
rw 		IV74
rw 		IV75
rw 		IV76
rw 		IV77
rw 		IV78
rw 		IV79
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV80
rw 		IV81
rw 		IV82
rw 		IV83
rw 		IV84
rw 		IV85
rw 		IV86
rw 		IV87
rw 		IV88
rw 		IV89
rw 		IV90
rw 		IV91
rw 		IV92
rw 		IV93
rw 		IV94
rw 		IV95
rw
Toggle fields

IV95

Bit 0: IV95.

IV94

Bit 1: IV94.

IV93

Bit 2: IV93.

IV92

Bit 3: IV92.

IV91

Bit 4: IV91.

IV90

Bit 5: IV90.

IV89

Bit 6: IV89.

IV88

Bit 7: IV88.

IV87

Bit 8: IV87.

IV86

Bit 9: IV86.

IV85

Bit 10: IV85.

IV84

Bit 11: IV84.

IV83

Bit 12: IV83.

IV82

Bit 13: IV82.

IV81

Bit 14: IV81.

IV80

Bit 15: IV80.

IV79

Bit 16: IV79.

IV78

Bit 17: IV78.

IV77

Bit 18: IV77.

IV76

Bit 19: IV76.

IV75

Bit 20: IV75.

IV74

Bit 21: IV74.

IV73

Bit 22: IV73.

IV72

Bit 23: IV72.

IV71

Bit 24: IV71.

IV70

Bit 25: IV70.

IV69

Bit 26: IV69.

IV68

Bit 27: IV68.

IV67

Bit 28: IV67.

IV66

Bit 29: IV66.

IV65

Bit 30: IV65.

IV64

Bit 31: IV64.

IV1RR

Refer to Section39.6.17: CRYP initialization vector register 0L (CRYP_IV0LR) for details.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IV96
rw 		IV97
rw 		IV98
rw 		IV99
rw 		IV100
rw 		IV101
rw 		IV102
rw 		IV103
rw 		IV104
rw 		IV105
rw 		IV106
rw 		IV107
rw 		IV108
rw 		IV109
rw 		IV110
rw 		IV111
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IV112
rw 		IV113
rw 		IV114
rw 		IV115
rw 		IV116
rw 		IV117
rw 		IV118
rw 		IV119
rw 		IV120
rw 		IV121
rw 		IV122
rw 		IV123
rw 		IV124
rw 		IV125
rw 		IV126
rw 		IV127
rw
Toggle fields

IV127

Bit 0: IV127.

IV126

Bit 1: IV126.

IV125

Bit 2: IV125.

IV124

Bit 3: IV124.

IV123

Bit 4: IV123.

IV122

Bit 5: IV122.

IV121

Bit 6: IV121.

IV120

Bit 7: IV120.

IV119

Bit 8: IV119.

IV118

Bit 9: IV118.

IV117

Bit 10: IV117.

IV116

Bit 11: IV116.

IV115

Bit 12: IV115.

IV114

Bit 13: IV114.

IV113

Bit 14: IV113.

IV112

Bit 15: IV112.

IV111

Bit 16: IV111.

IV110

Bit 17: IV110.

IV109

Bit 18: IV109.

IV108

Bit 19: IV108.

IV107

Bit 20: IV107.

IV106

Bit 21: IV106.

IV105

Bit 22: IV105.

IV104

Bit 23: IV104.

IV103

Bit 24: IV103.

IV102

Bit 25: IV102.

IV101

Bit 26: IV101.

IV100

Bit 27: IV100.

IV99

Bit 28: IV99.

IV98

Bit 29: IV98.

IV97

Bit 30: IV97.

IV96

Bit 31: IV96.

CSGCMCCM0R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM0
rw
Toggle fields

CSGCMCCM0

Bits 0-31: CSGCMCCM0.

CSGCMCCM1R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM1
rw
Toggle fields

CSGCMCCM1

Bits 0-31: CSGCMCCM1.

CSGCMCCM2R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM2
rw
Toggle fields

CSGCMCCM2

Bits 0-31: CSGCMCCM2.

CSGCMCCM3R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM3
rw
Toggle fields

CSGCMCCM3

Bits 0-31: CSGCMCCM3.

CSGCMCCM4R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM4
rw
Toggle fields

CSGCMCCM4

Bits 0-31: CSGCMCCM4.

CSGCMCCM5R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM5
rw
Toggle fields

CSGCMCCM5

Bits 0-31: CSGCMCCM5.

CSGCMCCM6R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM6
rw
Toggle fields

CSGCMCCM6

Bits 0-31: CSGCMCCM6.

CSGCMCCM7R

These registers contain the complete internal register states of the CRYP processor when the GCM/GMAC or CCM algorithm is selected. They are useful when a context swap has to be performed because a high-priority task needs the cryptographic processor while it is already in use by another task. When such an event occurs, the CRYP_CSGCMCCM0..7R and CRYP_CSGCM0..7R (in GCM/GMAC mode) or CRYP_CSGCMCCM0..7R (in CCM mode) registers have to be read and the values retrieved have to be saved in the system memory space. The cryptographic processor can then be used by the preemptive task. Then when the cryptographic computation is complete, the saved context can be read from memory and written back into the corresponding context swap registers.

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCMCCM7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCMCCM7
rw
Toggle fields

CSGCMCCM7

Bits 0-31: CSGCMCCM7.

CSGCM0R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM0
rw
Toggle fields

CSGCM0

Bits 0-31: CSGCM0.

CSGCM1R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM1
rw
Toggle fields

CSGCM1

Bits 0-31: CSGCM1.

CSGCM2R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM2
rw
Toggle fields

CSGCM2

Bits 0-31: CSGCM2.

CSGCM3R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM3
rw
Toggle fields

CSGCM3

Bits 0-31: CSGCM3.

CSGCM4R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM4
rw
Toggle fields

CSGCM4

Bits 0-31: CSGCM4.

CSGCM5R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM5
rw
Toggle fields

CSGCM5

Bits 0-31: CSGCM5.

CSGCM6R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM6
rw
Toggle fields

CSGCM6

Bits 0-31: CSGCM6.

CSGCM7R

Please refer to Section39.6.21: CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) for details.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSGCM7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSGCM7
rw
Toggle fields

CSGCM7

Bits 0-31: CSGCM7.

HWCFGR

CRYP hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000131, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

VERR

CRYP HW Version Register

Offset: 0x3f4, size: 32, reset: 0x00000022, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VER
r
Toggle fields

VER

Bits 0-7: VER.

IPIDR

CRYP Identification

Offset: 0x3f8, size: 32, reset: 0x00170011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

MID

CRYP HW Magic ID

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MID
r
Toggle fields

MID

Bits 0-31: MID.

DAC1

0x40017000: DAC1

15/64 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SWTRGR
0x8 DHR12R1
0xc DHR12L1
0x10 DHR8R1
0x14 DHR12R2
0x18 DHR12L2
0x1c DHR8R2
0x20 DHR12RD
0x24 DHR12LD
0x28 DHR8RD
0x2c DOR1
0x30 DOR2
0x34 SR
0x38 CCR
0x3c MCR
0x40 SHSR1
0x44 SHSR2
0x48 SHHR
0x4c SHRR
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

DAC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEN2
rw 		DMAUDRIE2
rw 		DMAEN2
rw 		MAMP2
rw 		WAVE2
rw 		TSEL23
rw 		TSEL22
rw 		TSEL21
rw 		TSEL20
rw 		TEN2
rw 		EN2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HFSEL
rw 		CEN1
rw 		DMAUDRIE1
rw 		DMAEN1
rw 		MAMP1
rw 		WAVE1
rw 		TSEL13
rw 		TSEL12
rw 		TSEL11
rw 		TSEL10
rw 		TEN1
rw 		EN1
rw
Toggle fields

EN1

Bit 0: EN1.

TEN1

Bit 1: TEN1.

TSEL10

Bit 2: TSEL10.

TSEL11

Bit 3: TSEL11.

TSEL12

Bit 4: TSEL12.

TSEL13

Bit 5: TSEL13.

WAVE1

Bits 6-7: WAVE1.

MAMP1

Bits 8-11: MAMP1.

DMAEN1

Bit 12: DMAEN1.

DMAUDRIE1

Bit 13: DMAUDRIE1.

CEN1

Bit 14: CEN1.

HFSEL

Bit 15: HFSEL.

EN2

Bit 16: EN2.

TEN2

Bit 17: TEN2.

TSEL20

Bit 18: TSEL20.

TSEL21

Bit 19: TSEL21.

TSEL22

Bit 20: TSEL22.

TSEL23

Bit 21: TSEL23.

WAVE2

Bits 22-23: WAVE2.

MAMP2

Bits 24-27: MAMP2.

DMAEN2

Bit 28: DMAEN2.

DMAUDRIE2

Bit 29: DMAUDRIE2.

CEN2

Bit 30: CEN2.

SWTRGR

DAC software trigger register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWTRIG2
w 		SWTRIG1
w
Toggle fields

SWTRIG1

Bit 0: SWTRIG1.

SWTRIG2

Bit 1: SWTRIG2.

DHR12R1

DAC channel1 12-bit right-aligned data holding register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DACC1DHR.

DHR12L1

DAC channel1 12-bit left aligned data holding register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DACC1DHR.

DHR8R1

DAC channel1 8-bit right aligned data holding register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DACC1DHR.

DHR12R2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-11: DACC2DHR.

DHR12L2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 4-15: DACC2DHR.

DHR8R2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw
Toggle fields

DACC2DHR

Bits 0-7: DACC2DHR.

DHR12RD

Dual DAC 12-bit right-aligned data holding register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-11: DACC1DHR.

DACC2DHR

Bits 16-27: DACC2DHR.

DHR12LD

Dual DAC 12-bit left aligned data holding register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 4-15: DACC1DHR.

DACC2DHR

Bits 20-31: DACC2DHR.

DHR8RD

Dual DAC 8-bit right aligned data holding register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR
rw 		DACC1DHR
rw
Toggle fields

DACC1DHR

Bits 0-7: DACC1DHR.

DACC2DHR

Bits 8-15: DACC2DHR.

DOR1

DAC channel1 data output register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DOR
r
Toggle fields

DACC1DOR

Bits 0-11: DACC1DOR.

DOR2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DOR
r
Toggle fields

DACC2DOR

Bits 0-11: DACC2DOR.

SR

DAC status register

Offset: 0x34, size: 32, reset: 0x00000000, access: Unspecified

4/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWST2
r 		CAL_FLAG2
r 		DMAUDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BWST1
r 		CAL_FLAG1
r 		DMAUDR1
rw
Toggle fields

DMAUDR1

Bit 13: DMAUDR1.

CAL_FLAG1

Bit 14: CAL_FLAG1.

BWST1

Bit 15: BWST1.

DMAUDR2

Bit 29: DMAUDR2.

CAL_FLAG2

Bit 30: CAL_FLAG2.

BWST2

Bit 31: BWST2.

CCR

DAC calibration control register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTRIM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTRIM1
rw
Toggle fields

OTRIM1

Bits 0-4: OTRIM1.

OTRIM2

Bits 16-20: OTRIM2.

MCR

DAC mode control register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODE1
rw
Toggle fields

MODE1

Bits 0-2: MODE1.

MODE2

Bits 16-18: MODE2.

SHSR1

DAC channel 1 sample and hold sample time register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE1
rw
Toggle fields

TSAMPLE1

Bits 0-9: TSAMPLE1.

SHSR2

This register is available only on dual-channel DACs. Refer to Section29.3: DAC implementation.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAMPLE2
rw
Toggle fields

TSAMPLE2

Bits 0-9: TSAMPLE2.

SHHR

DAC sample and hold time register

Offset: 0x48, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THOLD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THOLD1
rw
Toggle fields

THOLD1

Bits 0-9: THOLD1.

THOLD2

Bits 16-25: THOLD2.

SHRR

DAC sample and hold refresh time register

Offset: 0x4c, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TREFRESH2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFRESH1
rw
Toggle fields

TREFRESH1

Bits 0-7: TREFRESH1.

TREFRESH2

Bits 16-23: TREFRESH2.

HWCFGR0

DAC IP hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00001111, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAMPLE
r 		TRIANGLE
r 		LFSR
r 		DUAL
r
Toggle fields

DUAL

Bits 0-3: DUAL.

LFSR

Bits 4-7: LFSR.

TRIANGLE

Bits 8-11: TRIANGLE.

SAMPLE

Bits 12-15: SAMPLE.

OR_CFG

Bits 16-23: OR_CFG.

VERR

No

Offset: 0x3f4, size: 32, reset: 0x00000031, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

No

Offset: 0x3f8, size: 32, reset: 0x00110011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

No

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DCMI

0x4c006000: DCMI

17/54 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 RIS
0xc IER
0x10 MIS
0x14 ICR
0x18 ESCR
0x1c ESUR
0x20 CWSTRT
0x24 CWSIZE
0x28 DR
Toggle registers

CR

DCMI control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OELS
rw 		LSM
rw 		OEBS
rw 		BSM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLE
rw 		EDM
rw 		FCRC
rw 		VSPOL
rw 		HSPOL
rw 		PCKPOL
rw 		ESS
rw 		JPEG
rw 		CROP
rw 		CM
rw 		CAPTURE
rw
Toggle fields

CAPTURE

Bit 0: CAPTURE.

CM

Bit 1: CM.

CROP

Bit 2: CROP.

JPEG

Bit 3: JPEG.

ESS

Bit 4: ESS.

PCKPOL

Bit 5: PCKPOL.

HSPOL

Bit 6: HSPOL.

VSPOL

Bit 7: VSPOL.

FCRC

Bits 8-9: FCRC.

EDM

Bits 10-11: EDM.

ENABLE

Bit 14: ENABLE.

BSM

Bits 16-17: BSM.

OEBS

Bit 18: OEBS.

LSM

Bit 19: LSM.

OELS

Bit 20: OELS.

SR

DCMI status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNE
r 		VSYNC
r 		HSYNC
r
Toggle fields

HSYNC

Bit 0: HSYNC.

VSYNC

Bit 1: VSYNC.

FNE

Bit 2: FNE.

RIS

DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this register returns the status of the corresponding interrupt before masking with the DCMI_IER register value.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_RIS
r 		VSYNC_RIS
r 		ERR_RIS
r 		OVR_RIS
r 		FRAME_RIS
r
Toggle fields

FRAME_RIS

Bit 0: FRAME_RIS.

OVR_RIS

Bit 1: OVR_RIS.

ERR_RIS

Bit 2: ERR_RIS.

VSYNC_RIS

Bit 3: VSYNC_RIS.

LINE_RIS

Bit 4: LINE_RIS.

IER

The DCMI_IER register is used to enable interrupts. When one of the DCMI_IER bits is set, the corresponding interrupt is enabled. This register is accessible in both read and write.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_IE
rw 		VSYNC_IE
rw 		ERR_IE
rw 		OVR_IE
rw 		FRAME_IE
rw
Toggle fields

FRAME_IE

Bit 0: FRAME_IE.

OVR_IE

Bit 1: OVR_IE.

ERR_IE

Bit 2: ERR_IE.

VSYNC_IE

Bit 3: VSYNC_IE.

LINE_IE

Bit 4: LINE_IE.

MIS

This DCMI_MIS register is a read-only register. When read, it returns the current masked status value (depending on the value in DCMI_IER) of the corresponding interrupt. A bit in this register is set if the corresponding enable bit in DCMI_IER is set and the corresponding bit in DCMI_RIS is set.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_MIS
r 		VSYNC_MIS
r 		ERR_MIS
r 		OVR_MIS
r 		FRAME_MIS
r
Toggle fields

FRAME_MIS

Bit 0: FRAME_MIS.

OVR_MIS

Bit 1: OVR_MIS.

ERR_MIS

Bit 2: ERR_MIS.

VSYNC_MIS

Bit 3: VSYNC_MIS.

LINE_MIS

Bit 4: LINE_MIS.

ICR

The DCMI_ICR register is write-only.

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LINE_ISC
w 		VSYNC_ISC
w 		ERR_ISC
w 		OVR_ISC
w 		FRAME_ISC
w
Toggle fields

FRAME_ISC

Bit 0: FRAME_ISC.

OVR_ISC

Bit 1: OVR_ISC.

ERR_ISC

Bit 2: ERR_ISC.

VSYNC_ISC

Bit 3: VSYNC_ISC.

LINE_ISC

Bit 4: LINE_ISC.

ESCR

DCMI embedded synchronization code register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEC
rw 		LEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSC
rw 		FSC
rw
Toggle fields

FSC

Bits 0-7: FSC.

LSC

Bits 8-15: LSC.

LEC

Bits 16-23: LEC.

FEC

Bits 24-31: FEC.

ESUR

DCMI embedded synchronization unmask register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FEU
rw 		LEU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSU
rw 		FSU
rw
Toggle fields

FSU

Bits 0-7: FSU.

LSU

Bits 8-15: LSU.

LEU

Bits 16-23: LEU.

FEU

Bits 24-31: FEU.

CWSTRT

DCMI crop window start

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HOFFCNT
rw
Toggle fields

HOFFCNT

Bits 0-13: HOFFCNT.

VST

Bits 16-28: VST.

CWSIZE

DCMI crop window size

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLINE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAPCNT
rw
Toggle fields

CAPCNT

Bits 0-13: CAPCNT.

VLINE

Bits 16-29: VLINE.

DR

DCMI data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Byte3
r 		Byte2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Byte1
r 		Byte0
r
Toggle fields

Byte0

Bits 0-7: Byte0.

Byte1

Bits 8-15: Byte1.

Byte2

Bits 16-23: Byte2.

Byte3

Bits 24-31: Byte3.

DDRCTRL

0x5a003000: DDRCTRL

29/268 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MSTR
0x4 STAT
0x10 MRCTRL0
0x14 MRCTRL1
0x18 MRSTAT
0x20 DERATEEN
0x24 DERATEINT
0x30 PWRCTL
0x34 PWRTMG
0x38 HWLPCTL
0x50 RFSHCTL0
0x60 RFSHCTL3
0x64 RFSHTMG
0xc0 CRCPARCTL0
0xcc CRCPARSTAT
0xd0 INIT0
0xd4 INIT1
0xd8 INIT2
0xdc INIT3
0xe0 INIT4
0xe4 INIT5
0xf0 DIMMCTL
0x100 DRAMTMG0
0x104 DRAMTMG1
0x108 DRAMTMG2
0x10c DRAMTMG3
0x110 DRAMTMG4
0x114 DRAMTMG5
0x118 DRAMTMG6
0x11c DRAMTMG7
0x120 DRAMTMG8
0x138 DRAMTMG14
0x13c DRAMTMG15
0x180 ZQCTL0
0x184 ZQCTL1
0x188 ZQCTL2
0x18c ZQSTAT
0x190 DFITMG0
0x194 DFITMG1
0x198 DFILPCFG0
0x1a0 DFIUPD0
0x1a4 DFIUPD1
0x1a8 DFIUPD2
0x1b0 DFIMISC
0x1bc DFISTAT
0x1c4 DFIPHYMSTR
0x204 ADDRMAP1
0x208 ADDRMAP2
0x20c ADDRMAP3
0x210 ADDRMAP4
0x214 ADDRMAP5
0x218 ADDRMAP6
0x224 ADDRMAP9
0x228 ADDRMAP10
0x22c ADDRMAP11
0x240 ODTCFG
0x244 ODTMAP
0x250 SCHED
0x254 SCHED1
0x25c PERFHPR1
0x264 PERFLPR1
0x26c PERFWR1
0x300 DBG0
0x304 DBG1
0x308 DBGCAM
0x30c DBGCMD
0x310 DBGSTAT
0x320 SWCTL
0x324 SWSTAT
0x36c POISONCFG
0x370 POISONSTAT
0x3fc PSTAT
0x400 PCCFG
0x404 PCFGR_0
0x408 PCFGW_0
0x490 PCTRL_0
0x494 PCFGQOS0_0
0x498 PCFGQOS1_0
0x49c PCFGWQOS0_0
0x4a0 PCFGWQOS1_0
0x4b4 PCFGR_1
0x4b8 PCFGW_1
0x540 PCTRL_1
0x544 PCFGQOS0_1
0x548 PCFGQOS1_1
0x54c PCFGWQOS0_1
0x550 PCFGWQOS1_1
Toggle registers

MSTR

DDRCTRL master register 0

Offset: 0x0, size: 32, reset: 0x00040001, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BURST_RDWR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLL_OFF_MODE
rw 		DATA_BUS_WIDTH
rw 		EN_2T_TIMING_MODE
rw 		BURSTCHOP
rw 		LPDDR3
rw 		LPDDR2
rw 		DDR3
rw
Toggle fields

DDR3

Bit 0: DDR3.

LPDDR2

Bit 2: LPDDR2.

LPDDR3

Bit 3: LPDDR3.

BURSTCHOP

Bit 9: BURSTCHOP.

EN_2T_TIMING_MODE

Bit 10: EN_2T_TIMING_MODE.

DATA_BUS_WIDTH

Bits 12-13: DATA_BUS_WIDTH.

DLL_OFF_MODE

Bit 15: DLL_OFF_MODE.

BURST_RDWR

Bits 16-19: BURST_RDWR.

STAT

DDRCTRL operating mode status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SELFREF_CAM_NOT_EMPTY
r 		SELFREF_TYPE
r 		OPERATING_MODE
r
Toggle fields

OPERATING_MODE

Bits 0-2: OPERATING_MODE.

SELFREF_TYPE

Bits 4-5: SELFREF_TYPE.

SELFREF_CAM_NOT_EMPTY

Bit 12: SELFREF_CAM_NOT_EMPTY.

MRCTRL0

Mode Register Read/Write Control Register 0. Do not enable more than one of the following fields simultaneously: sw_init_int pda_en mpr_en

Offset: 0x10, size: 32, reset: 0x00000010, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR_WR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR_ADDR
rw 		MR_RANK
rw 		MR_TYPE
rw
Toggle fields

MR_TYPE

Bit 0: MR_TYPE.

MR_RANK

Bit 4: MR_RANK.

MR_ADDR

Bits 12-15: MR_ADDR.

MR_WR

Bit 31: MR_WR.

MRCTRL1

DDRCTRL mode register read/write control register 1

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR_DATA
rw
Toggle fields

MR_DATA

Bits 0-15: MR_DATA.

MRSTAT

DDRCTRL mode register read/write status register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR_WR_BUSY
r
Toggle fields

MR_WR_BUSY

Bit 0: MR_WR_BUSY.

DERATEEN

DDRCTRL temperature derate enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DERATE_BYTE
rw 		DERATE_VALUE
rw 		DERATE_ENABLE
rw
Toggle fields

DERATE_ENABLE

Bit 0: DERATE_ENABLE.

DERATE_VALUE

Bits 1-2: DERATE_VALUE.

DERATE_BYTE

Bits 4-7: DERATE_BYTE.

DERATEINT

DDRCTRL temperature derate interval register

Offset: 0x24, size: 32, reset: 0x00800000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR4_READ_INTERVAL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR4_READ_INTERVAL
rw
Toggle fields

MR4_READ_INTERVAL

Bits 0-31: MR4_READ_INTERVAL.

PWRCTL

DDRCTRL low power control register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS_CAM_DRAIN_SELFREF
rw 		SELFREF_SW
rw 		EN_DFI_DRAM_CLK_DISABLE
rw 		DEEPPOWERDOWN_EN
rw 		POWERDOWN_EN
rw 		SELFREF_EN
rw
Toggle fields

SELFREF_EN

Bit 0: SELFREF_EN.

POWERDOWN_EN

Bit 1: POWERDOWN_EN.

DEEPPOWERDOWN_EN

Bit 2: DEEPPOWERDOWN_EN.

EN_DFI_DRAM_CLK_DISABLE

Bit 3: EN_DFI_DRAM_CLK_DISABLE.

SELFREF_SW

Bit 5: SELFREF_SW.

DIS_CAM_DRAIN_SELFREF

Bit 7: DIS_CAM_DRAIN_SELFREF.

PWRTMG

DDRCTRL low power timing register

Offset: 0x34, size: 32, reset: 0x00402010, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELFREF_TO_X32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_DPD_X4096
rw 		POWERDOWN_TO_X32
rw
Toggle fields

POWERDOWN_TO_X32

Bits 0-4: POWERDOWN_TO_X32.

T_DPD_X4096

Bits 8-15: T_DPD_X4096.

SELFREF_TO_X32

Bits 16-23: SELFREF_TO_X32.

HWLPCTL

DDRCTRL hardware low power control register

Offset: 0x38, size: 32, reset: 0x00000003, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW_LP_IDLE_X32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HW_LP_EXIT_IDLE_EN
rw 		HW_LP_EN
rw
Toggle fields

HW_LP_EN

Bit 0: HW_LP_EN.

HW_LP_EXIT_IDLE_EN

Bit 1: HW_LP_EXIT_IDLE_EN.

HW_LP_IDLE_X32

Bits 16-27: HW_LP_IDLE_X32.

RFSHCTL0

DDRCTRL refresh control register 0

Offset: 0x50, size: 32, reset: 0x00210000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFRESH_MARGIN
rw 		REFRESH_TO_X32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH_TO_X32
rw 		REFRESH_BURST
rw 		PER_BANK_REFRESH
rw
Toggle fields

PER_BANK_REFRESH

Bit 2: PER_BANK_REFRESH.

REFRESH_BURST

Bits 4-8: REFRESH_BURST.

REFRESH_TO_X32

Bits 12-16: REFRESH_TO_X32.

REFRESH_MARGIN

Bits 20-23: REFRESH_MARGIN.

RFSHCTL3

DDRCTRL refresh control register 3

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFRESH_UPDATE_LEVEL
rw 		DIS_AUTO_REFRESH
rw
Toggle fields

DIS_AUTO_REFRESH

Bit 0: DIS_AUTO_REFRESH.

REFRESH_UPDATE_LEVEL

Bit 1: REFRESH_UPDATE_LEVEL.

RFSHTMG

DDRCTRL refresh timing register

Offset: 0x64, size: 32, reset: 0x0062008C, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_RFC_NOM_X1_SEL
rw 		T_RFC_NOM_X1_X32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPDDR3_TREFBW_EN
rw 		T_RFC_MIN
rw
Toggle fields

T_RFC_MIN

Bits 0-9: T_RFC_MIN.

LPDDR3_TREFBW_EN

Bit 15: LPDDR3_TREFBW_EN.

T_RFC_NOM_X1_X32

Bits 16-27: T_RFC_NOM_X1_X32.

T_RFC_NOM_X1_SEL

Bit 31: T_RFC_NOM_X1_SEL.

CRCPARCTL0

DDRCTRL CRC parity control register 0

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_ALERT_ERR_CNT_CLR
rw 		DFI_ALERT_ERR_INT_CLR
rw 		DFI_ALERT_ERR_INT_EN
rw
Toggle fields

DFI_ALERT_ERR_INT_EN

Bit 0: DFI_ALERT_ERR_INT_EN.

DFI_ALERT_ERR_INT_CLR

Bit 1: DFI_ALERT_ERR_INT_CLR.

DFI_ALERT_ERR_CNT_CLR

Bit 2: DFI_ALERT_ERR_CNT_CLR.

CRCPARSTAT

DDRCTRL CRC parity status register

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFI_ALERT_ERR_INT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_ALERT_ERR_CNT
r
Toggle fields

DFI_ALERT_ERR_CNT

Bits 0-15: DFI_ALERT_ERR_CNT.

DFI_ALERT_ERR_INT

Bit 16: DFI_ALERT_ERR_INT.

INIT0

DDRCTRL SDRAM initialization register 0

Offset: 0xd0, size: 32, reset: 0x0002004E, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SKIP_DRAM_INIT
rw 		POST_CKE_X1024
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRE_CKE_X1024
rw
Toggle fields

PRE_CKE_X1024

Bits 0-11: PRE_CKE_X1024.

POST_CKE_X1024

Bits 16-25: POST_CKE_X1024.

SKIP_DRAM_INIT

Bits 30-31: SKIP_DRAM_INIT.

INIT1

DDRCTRL SDRAM initialization register 1

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRAM_RSTN_X1024
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRE_OCD_X32
rw
Toggle fields

PRE_OCD_X32

Bits 0-3: PRE_OCD_X32.

DRAM_RSTN_X1024

Bits 16-24: DRAM_RSTN_X1024.

INIT2

DDRCTRL SDRAM initialization register 2

Offset: 0xd8, size: 32, reset: 0x00000D05, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDLE_AFTER_RESET_X32
rw 		MIN_STABLE_CLOCK_X1
rw
Toggle fields

MIN_STABLE_CLOCK_X1

Bits 0-3: MIN_STABLE_CLOCK_X1.

IDLE_AFTER_RESET_X32

Bits 8-15: IDLE_AFTER_RESET_X32.

INIT3

DDRCTRL SDRAM initialization register 3

Offset: 0xdc, size: 32, reset: 0x00000510, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EMR
rw
Toggle fields

EMR

Bits 0-15: EMR.

MR

Bits 16-31: MR.

INIT4

DDRCTRL SDRAM initialization register 4

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EMR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EMR3
rw
Toggle fields

EMR3

Bits 0-15: EMR3.

EMR2

Bits 16-31: EMR2.

INIT5

DDRCTRL SDRAM initialization register 5

Offset: 0xe4, size: 32, reset: 0x00100004, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEV_ZQINIT_X32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAX_AUTO_INIT_X1024
rw
Toggle fields

MAX_AUTO_INIT_X1024

Bits 0-9: MAX_AUTO_INIT_X1024.

DEV_ZQINIT_X32

Bits 16-23: DEV_ZQINIT_X32.

DIMMCTL

DDRCTRL DIMM control register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIMM_ADDR_MIRR_EN
rw 		DIMM_STAGGER_CS_EN
rw
Toggle fields

DIMM_STAGGER_CS_EN

Bit 0: DIMM_STAGGER_CS_EN.

DIMM_ADDR_MIRR_EN

Bit 1: DIMM_ADDR_MIRR_EN.

DRAMTMG0

DDRCTRL SDRAM timing register 0

Offset: 0x100, size: 32, reset: 0x0F101B0F, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR2PRE
rw 		T_FAW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_RAS_MAX
rw 		T_RAS_MIN
rw
Toggle fields

T_RAS_MIN

Bits 0-5: T_RAS_MIN.

T_RAS_MAX

Bits 8-14: T_RAS_MAX.

T_FAW

Bits 16-21: T_FAW.

WR2PRE

Bits 24-30: WR2PRE.

DRAMTMG1

DDRCTRL SDRAM timing register 1

Offset: 0x104, size: 32, reset: 0x00080414, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_XP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD2PRE
rw 		T_RC
rw
Toggle fields

T_RC

Bits 0-6: T_RC.

RD2PRE

Bits 8-13: RD2PRE.

T_XP

Bits 16-20: T_XP.

DRAMTMG2

DDRCTRL SDRAM timing register 2

Offset: 0x108, size: 32, reset: 0x0305060D, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRITE_LATENCY
rw 		READ_LATENCY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD2WR
rw 		WR2RD
rw
Toggle fields

WR2RD

Bits 0-5: WR2RD.

RD2WR

Bits 8-13: RD2WR.

READ_LATENCY

Bits 16-21: READ_LATENCY.

WRITE_LATENCY

Bits 24-29: WRITE_LATENCY.

DRAMTMG3

DDRCTRL SDRAM timing register 3

Offset: 0x10c, size: 32, reset: 0x0050400C, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_MRW
rw 		T_MRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_MRD
rw 		T_MOD
rw
Toggle fields

T_MOD

Bits 0-9: T_MOD.

T_MRD

Bits 12-17: T_MRD.

T_MRW

Bits 20-29: T_MRW.

DRAMTMG4

DDRCTRL SDRAM timing register 4

Offset: 0x110, size: 32, reset: 0x05040405, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_RCD
rw 		T_CCD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_RRD
rw 		T_RP
rw
Toggle fields

T_RP

Bits 0-4: T_RP.

T_RRD

Bits 8-11: T_RRD.

T_CCD

Bits 16-19: T_CCD.

T_RCD

Bits 24-28: T_RCD.

DRAMTMG5

DDRCTRL SDRAM timing register 5

Offset: 0x114, size: 32, reset: 0x05050403, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_CKSRX
rw 		T_CKSRE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_CKESR
rw 		T_CKE
rw
Toggle fields

T_CKE

Bits 0-4: T_CKE.

T_CKESR

Bits 8-13: T_CKESR.

T_CKSRE

Bits 16-19: T_CKSRE.

T_CKSRX

Bits 24-27: T_CKSRX.

DRAMTMG6

DDRCTRL SDRAM timing register 6

Offset: 0x118, size: 32, reset: 0x02020005, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_CKDPDE
rw 		T_CKDPDX
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_CKCSX
rw
Toggle fields

T_CKCSX

Bits 0-3: T_CKCSX.

T_CKDPDX

Bits 16-19: T_CKDPDX.

T_CKDPDE

Bits 24-27: T_CKDPDE.

DRAMTMG7

DDRCTRL SDRAM timing register 7

Offset: 0x11c, size: 32, reset: 0x00000202, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_CKPDE
rw 		T_CKPDX
rw
Toggle fields

T_CKPDX

Bits 0-3: T_CKPDX.

T_CKPDE

Bits 8-11: T_CKPDE.

DRAMTMG8

DDRCTRL SDRAM timing register 8

Offset: 0x120, size: 32, reset: 0x00004405, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_XS_DLL_X32
rw 		T_XS_X32
rw
Toggle fields

T_XS_X32

Bits 0-6: T_XS_X32.

T_XS_DLL_X32

Bits 8-14: T_XS_DLL_X32.

DRAMTMG14

DDRCTRL SDRAM timing register 14

Offset: 0x138, size: 32, reset: 0x000000A0, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_XSR
rw
Toggle fields

T_XSR

Bits 0-11: T_XSR.

DRAMTMG15

DDRCTRL SDRAM timing register 15

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN_DFI_LP_T_STAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_STAB_X32
rw
Toggle fields

T_STAB_X32

Bits 0-7: T_STAB_X32.

EN_DFI_LP_T_STAB

Bit 31: EN_DFI_LP_T_STAB.

ZQCTL0

DDRCTRL ZQ control register 0

Offset: 0x180, size: 32, reset: 0x02000040, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS_AUTO_ZQ
rw 		DIS_SRX_ZQCL
rw 		ZQ_RESISTOR_SHARED
rw 		T_ZQ_LONG_NOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_ZQ_SHORT_NOP
rw
Toggle fields

T_ZQ_SHORT_NOP

Bits 0-9: T_ZQ_SHORT_NOP.

T_ZQ_LONG_NOP

Bits 16-26: T_ZQ_LONG_NOP.

ZQ_RESISTOR_SHARED

Bit 29: ZQ_RESISTOR_SHARED.

DIS_SRX_ZQCL

Bit 30: DIS_SRX_ZQCL.

DIS_AUTO_ZQ

Bit 31: DIS_AUTO_ZQ.

ZQCTL1

DDRCTRL ZQ control register 1

Offset: 0x184, size: 32, reset: 0x02000100, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
T_ZQ_RESET_NOP
rw 		T_ZQ_SHORT_INTERVAL_X1024
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T_ZQ_SHORT_INTERVAL_X1024
rw
Toggle fields

T_ZQ_SHORT_INTERVAL_X1024

Bits 0-19: T_ZQ_SHORT_INTERVAL_X1024.

T_ZQ_RESET_NOP

Bits 20-29: T_ZQ_RESET_NOP.

ZQCTL2

DDRCTRL ZQ control register 2

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZQ_RESET
rw
Toggle fields

ZQ_RESET

Bit 0: ZQ_RESET.

ZQSTAT

DDRCTRL ZQ status register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZQ_RESET_BUSY
r
Toggle fields

ZQ_RESET_BUSY

Bit 0: ZQ_RESET_BUSY.

DFITMG0

DDRCTRL DFI timing register 0

Offset: 0x190, size: 32, reset: 0x07020002, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFI_T_CTRL_DELAY
rw 		DFI_T_RDDATA_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_TPHY_WRDATA
rw 		DFI_TPHY_WRLAT
rw
Toggle fields

DFI_TPHY_WRLAT

Bits 0-5: DFI_TPHY_WRLAT.

DFI_TPHY_WRDATA

Bits 8-13: DFI_TPHY_WRDATA.

DFI_T_RDDATA_EN

Bits 16-22: DFI_T_RDDATA_EN.

DFI_T_CTRL_DELAY

Bits 24-28: DFI_T_CTRL_DELAY.

DFITMG1

DDRCTRL DFI timing register 1

Offset: 0x194, size: 32, reset: 0x00000404, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFI_T_WRDATA_DELAY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_T_DRAM_CLK_DISABLE
rw 		DFI_T_DRAM_CLK_ENABLE
rw
Toggle fields

DFI_T_DRAM_CLK_ENABLE

Bits 0-4: DFI_T_DRAM_CLK_ENABLE.

DFI_T_DRAM_CLK_DISABLE

Bits 8-12: DFI_T_DRAM_CLK_DISABLE.

DFI_T_WRDATA_DELAY

Bits 16-20: DFI_T_WRDATA_DELAY.

DFILPCFG0

DDRCTRL low power configuration register 0

Offset: 0x198, size: 32, reset: 0x07000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFI_TLP_RESP
rw 		DFI_LP_WAKEUP_DPD
rw 		DFI_LP_EN_DPD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_LP_WAKEUP_SR
rw 		DFI_LP_EN_SR
rw 		DFI_LP_WAKEUP_PD
rw 		DFI_LP_EN_PD
rw
Toggle fields

DFI_LP_EN_PD

Bit 0: DFI_LP_EN_PD.

DFI_LP_WAKEUP_PD

Bits 4-7: DFI_LP_WAKEUP_PD.

DFI_LP_EN_SR

Bit 8: DFI_LP_EN_SR.

DFI_LP_WAKEUP_SR

Bits 12-15: DFI_LP_WAKEUP_SR.

DFI_LP_EN_DPD

Bit 16: DFI_LP_EN_DPD.

DFI_LP_WAKEUP_DPD

Bits 20-23: DFI_LP_WAKEUP_DPD.

DFI_TLP_RESP

Bits 24-28: DFI_TLP_RESP.

DFIUPD0

DDRCTRL DFI update register 0

Offset: 0x1a0, size: 32, reset: 0x00400003, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIS_AUTO_CTRLUPD
rw 		DIS_AUTO_CTRLUPD_SRX
rw 		CTRLUPD_PRE_SRX
rw 		DFI_T_CTRLUP_MAX
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_T_CTRLUP_MIN
rw
Toggle fields

DFI_T_CTRLUP_MIN

Bits 0-9: DFI_T_CTRLUP_MIN.

DFI_T_CTRLUP_MAX

Bits 16-25: DFI_T_CTRLUP_MAX.

CTRLUPD_PRE_SRX

Bit 29: CTRLUPD_PRE_SRX.

DIS_AUTO_CTRLUPD_SRX

Bit 30: DIS_AUTO_CTRLUPD_SRX.

DIS_AUTO_CTRLUPD

Bit 31: DIS_AUTO_CTRLUPD.

DFIUPD1

DDRCTRL DFI update register 1

Offset: 0x1a4, size: 32, reset: 0x00010001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFI_T_CTRLUPD_INTERVAL_MIN_X1024
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_T_CTRLUPD_INTERVAL_MAX_X1024
rw
Toggle fields

DFI_T_CTRLUPD_INTERVAL_MAX_X1024

Bits 0-7: DFI_T_CTRLUPD_INTERVAL_MAX_X1024.

DFI_T_CTRLUPD_INTERVAL_MIN_X1024

Bits 16-23: DFI_T_CTRLUPD_INTERVAL_MIN_X1024.

DFIUPD2

DDRCTRL DFI update register 2

Offset: 0x1a8, size: 32, reset: 0x80000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFI_PHYUPD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

DFI_PHYUPD_EN

Bit 31: DFI_PHYUPD_EN.

DFIMISC

DDRCTRL DFI miscellaneous control register

Offset: 0x1b0, size: 32, reset: 0x00000001, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_FREQUENCY
rw 		DFI_INIT_START
rw 		CTL_IDLE_EN
rw 		DFI_INIT_COMPLETE_EN
rw
Toggle fields

DFI_INIT_COMPLETE_EN

Bit 0: DFI_INIT_COMPLETE_EN.

CTL_IDLE_EN

Bit 4: CTL_IDLE_EN.

DFI_INIT_START

Bit 5: DFI_INIT_START.

DFI_FREQUENCY

Bits 8-12: DFI_FREQUENCY.

DFISTAT

DDRCTRL DFI status register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_LP_ACK
r 		DFI_INIT_COMPLETE
r
Toggle fields

DFI_INIT_COMPLETE

Bit 0: DFI_INIT_COMPLETE.

DFI_LP_ACK

Bit 1: DFI_LP_ACK.

DFIPHYMSTR

DDRCTRL DFI PHY master register

Offset: 0x1c4, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DFI_PHYMSTR_EN
rw
Toggle fields

DFI_PHYMSTR_EN

Bit 0: DFI_PHYMSTR_EN.

ADDRMAP1

DDRCTRL address map register 1

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRMAP_BANK_B2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_BANK_B1
rw 		ADDRMAP_BANK_B0
rw
Toggle fields

ADDRMAP_BANK_B0

Bits 0-5: ADDRMAP_BANK_B0.

ADDRMAP_BANK_B1

Bits 8-13: ADDRMAP_BANK_B1.

ADDRMAP_BANK_B2

Bits 16-21: ADDRMAP_BANK_B2.

ADDRMAP2

DDRCTRL address map register 2

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRMAP_COL_B5
rw 		ADDRMAP_COL_B4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_COL_B3
rw 		ADDRMAP_COL_B2
rw
Toggle fields

ADDRMAP_COL_B2

Bits 0-3: ADDRMAP_COL_B2.

ADDRMAP_COL_B3

Bits 8-11: ADDRMAP_COL_B3.

ADDRMAP_COL_B4

Bits 16-19: ADDRMAP_COL_B4.

ADDRMAP_COL_B5

Bits 24-27: ADDRMAP_COL_B5.

ADDRMAP3

DDRCTRL address map register 3

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRMAP_COL_B9
rw 		ADDRMAP_COL_B8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_COL_B7
rw 		ADDRMAP_COL_B6
rw
Toggle fields

ADDRMAP_COL_B6

Bits 0-3: ADDRMAP_COL_B6.

ADDRMAP_COL_B7

Bits 8-12: ADDRMAP_COL_B7.

ADDRMAP_COL_B8

Bits 16-20: ADDRMAP_COL_B8.

ADDRMAP_COL_B9

Bits 24-28: ADDRMAP_COL_B9.

ADDRMAP4

DDRCTRL address map register 4

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_COL_B11
rw 		ADDRMAP_COL_B10
rw
Toggle fields

ADDRMAP_COL_B10

Bits 0-4: ADDRMAP_COL_B10.

ADDRMAP_COL_B11

Bits 8-12: ADDRMAP_COL_B11.

ADDRMAP5

DDRCTRL address map register 5

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRMAP_ROW_B11
rw 		ADDRMAP_ROW_B2_10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_ROW_B1
rw 		ADDRMAP_ROW_B0
rw
Toggle fields

ADDRMAP_ROW_B0

Bits 0-3: ADDRMAP_ROW_B0.

ADDRMAP_ROW_B1

Bits 8-11: ADDRMAP_ROW_B1.

ADDRMAP_ROW_B2_10

Bits 16-19: ADDRMAP_ROW_B2_10.

ADDRMAP_ROW_B11

Bits 24-27: ADDRMAP_ROW_B11.

ADDRMAP6

DDRCTRL address register 6

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPDDR3_6GB_12GB
rw 		ADDRMAP_ROW_B15
rw 		ADDRMAP_ROW_B14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_ROW_B13
rw 		ADDRMAP_ROW_B12
rw
Toggle fields

ADDRMAP_ROW_B12

Bits 0-3: ADDRMAP_ROW_B12.

ADDRMAP_ROW_B13

Bits 8-11: ADDRMAP_ROW_B13.

ADDRMAP_ROW_B14

Bits 16-19: ADDRMAP_ROW_B14.

ADDRMAP_ROW_B15

Bits 24-27: ADDRMAP_ROW_B15.

LPDDR3_6GB_12GB

Bit 31: LPDDR3_6GB_12GB.

ADDRMAP9

DDRCTRL address map register 9

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRMAP_ROW_B5
rw 		ADDRMAP_ROW_B4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_ROW_B3
rw 		ADDRMAP_ROW_B2
rw
Toggle fields

ADDRMAP_ROW_B2

Bits 0-3: ADDRMAP_ROW_B2.

ADDRMAP_ROW_B3

Bits 8-11: ADDRMAP_ROW_B3.

ADDRMAP_ROW_B4

Bits 16-19: ADDRMAP_ROW_B4.

ADDRMAP_ROW_B5

Bits 24-27: ADDRMAP_ROW_B5.

ADDRMAP10

DDRCTRL address map register 10

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRMAP_ROW_B9
rw 		ADDRMAP_ROW_B8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_ROW_B7
rw 		ADDRMAP_ROW_B6
rw
Toggle fields

ADDRMAP_ROW_B6

Bits 0-3: ADDRMAP_ROW_B6.

ADDRMAP_ROW_B7

Bits 8-11: ADDRMAP_ROW_B7.

ADDRMAP_ROW_B8

Bits 16-19: ADDRMAP_ROW_B8.

ADDRMAP_ROW_B9

Bits 24-27: ADDRMAP_ROW_B9.

ADDRMAP11

DDRCTRL address map register 11

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRMAP_ROW_B10
rw
Toggle fields

ADDRMAP_ROW_B10

Bits 0-3: ADDRMAP_ROW_B10.

ODTCFG

DDRCTRL ODT configuration register

Offset: 0x240, size: 32, reset: 0x04000400, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_ODT_HOLD
rw 		WR_ODT_DELAY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_ODT_HOLD
rw 		RD_ODT_DELAY
rw
Toggle fields

RD_ODT_DELAY

Bits 2-6: RD_ODT_DELAY.

RD_ODT_HOLD

Bits 8-11: RD_ODT_HOLD.

WR_ODT_DELAY

Bits 16-20: WR_ODT_DELAY.

WR_ODT_HOLD

Bits 24-27: WR_ODT_HOLD.

ODTMAP

DDRCTRL ODT/Rank map register

Offset: 0x244, size: 32, reset: 0x00000011, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RANK0_RD_ODT
rw 		RANK0_WR_ODT
rw
Toggle fields

RANK0_WR_ODT

Bit 0: RANK0_WR_ODT.

RANK0_RD_ODT

Bit 4: RANK0_RD_ODT.

SCHED

DDRCTRL scheduler control register

Offset: 0x250, size: 32, reset: 0x00000805, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDWR_IDLE_GAP
rw 		GO2CRITICAL_HYSTERESIS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR_NUM_ENTRIES
rw 		PAGECLOSE
rw 		PREFER_WRITE
rw 		FORCE_LOW_PRI_N
rw
Toggle fields

FORCE_LOW_PRI_N

Bit 0: FORCE_LOW_PRI_N.

PREFER_WRITE

Bit 1: PREFER_WRITE.

PAGECLOSE

Bit 2: PAGECLOSE.

LPR_NUM_ENTRIES

Bits 8-11: LPR_NUM_ENTRIES.

GO2CRITICAL_HYSTERESIS

Bits 16-23: GO2CRITICAL_HYSTERESIS.

RDWR_IDLE_GAP

Bits 24-30: RDWR_IDLE_GAP.

SCHED1

DDRCTRL scheduler control register 1

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAGECLOSE_TIMER
rw
Toggle fields

PAGECLOSE_TIMER

Bits 0-7: PAGECLOSE_TIMER.

PERFHPR1

DDRCTRL high priority read CAM register 1

Offset: 0x25c, size: 32, reset: 0x0F000001, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPR_XACT_RUN_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPR_MAX_STARVE
rw
Toggle fields

HPR_MAX_STARVE

Bits 0-15: HPR_MAX_STARVE.

HPR_XACT_RUN_LENGTH

Bits 24-31: HPR_XACT_RUN_LENGTH.

PERFLPR1

DDRCTRL low priority read CAM register 1

Offset: 0x264, size: 32, reset: 0x0F00007F, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPR_XACT_RUN_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPR_MAX_STARVE
rw
Toggle fields

LPR_MAX_STARVE

Bits 0-15: LPR_MAX_STARVE.

LPR_XACT_RUN_LENGTH

Bits 24-31: LPR_XACT_RUN_LENGTH.

PERFWR1

DDRCTRL write CAM register 1

Offset: 0x26c, size: 32, reset: 0x0F00007F, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W_XACT_RUN_LENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W_MAX_STARVE
rw
Toggle fields

W_MAX_STARVE

Bits 0-15: W_MAX_STARVE.

W_XACT_RUN_LENGTH

Bits 24-31: W_XACT_RUN_LENGTH.

DBG0

DDRCTRL debug register 0

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS_COLLISION_PAGE_OPT
rw 		DIS_WC
rw
Toggle fields

DIS_WC

Bit 0: DIS_WC.

DIS_COLLISION_PAGE_OPT

Bit 4: DIS_COLLISION_PAGE_OPT.

DBG1

DDRCTRL debug register 1

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIS_HIF
rw 		DIS_DQ
rw
Toggle fields

DIS_DQ

Bit 0: DIS_DQ.

DIS_HIF

Bit 1: DIS_HIF.

DBGCAM

DDRCTRL CAM debug register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_DATA_PIPELINE_EMPTY
r 		RD_DATA_PIPELINE_EMPTY
r 		DBG_WR_Q_EMPTY
r 		DBG_RD_Q_EMPTY
r 		DBG_STALL
r 		DBG_W_Q_DEPTH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_LPR_Q_DEPTH
r 		DBG_HPR_Q_DEPTH
r
Toggle fields

DBG_HPR_Q_DEPTH

Bits 0-4: DBG_HPR_Q_DEPTH.

DBG_LPR_Q_DEPTH

Bits 8-12: DBG_LPR_Q_DEPTH.

DBG_W_Q_DEPTH

Bits 16-20: DBG_W_Q_DEPTH.

DBG_STALL

Bit 24: DBG_STALL.

DBG_RD_Q_EMPTY

Bit 25: DBG_RD_Q_EMPTY.

DBG_WR_Q_EMPTY

Bit 26: DBG_WR_Q_EMPTY.

RD_DATA_PIPELINE_EMPTY

Bit 28: RD_DATA_PIPELINE_EMPTY.

WR_DATA_PIPELINE_EMPTY

Bit 29: WR_DATA_PIPELINE_EMPTY.

DBGCMD

DDRCTRL command debug register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRLUPD
rw 		ZQ_CALIB_SHORT
rw 		RANK0_REFRESH
rw
Toggle fields

RANK0_REFRESH

Bit 0: RANK0_REFRESH.

ZQ_CALIB_SHORT

Bit 4: ZQ_CALIB_SHORT.

CTRLUPD

Bit 5: CTRLUPD.

DBGSTAT

DDRCTRL status debug register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRLUPD_BUSY
r 		ZQ_CALIB_SHORT_BUSY
r 		RANK0_REFRESH_BUSY
r
Toggle fields

RANK0_REFRESH_BUSY

Bit 0: RANK0_REFRESH_BUSY.

ZQ_CALIB_SHORT_BUSY

Bit 4: ZQ_CALIB_SHORT_BUSY.

CTRLUPD_BUSY

Bit 5: CTRLUPD_BUSY.

SWCTL

DDRCTRL software register programming control enable

Offset: 0x320, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW_DONE
rw
Toggle fields

SW_DONE

Bit 0: SW_DONE.

SWSTAT

DDRCTRL software register programming control status

Offset: 0x324, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW_DONE_ACK
r
Toggle fields

SW_DONE_ACK

Bit 0: SW_DONE_ACK.

POISONCFG

AXI Poison configuration register common for all AXI ports.

Offset: 0x36c, size: 32, reset: 0x00110011, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD_POISON_INTR_CLR
rw 		RD_POISON_INTR_EN
rw 		RD_POISON_SLVERR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_POISON_INTR_CLR
rw 		WR_POISON_INTR_EN
rw 		WR_POISON_SLVERR_EN
rw
Toggle fields

WR_POISON_SLVERR_EN

Bit 0: WR_POISON_SLVERR_EN.

WR_POISON_INTR_EN

Bit 4: WR_POISON_INTR_EN.

WR_POISON_INTR_CLR

Bit 8: WR_POISON_INTR_CLR.

RD_POISON_SLVERR_EN

Bit 16: RD_POISON_SLVERR_EN.

RD_POISON_INTR_EN

Bit 20: RD_POISON_INTR_EN.

RD_POISON_INTR_CLR

Bit 24: RD_POISON_INTR_CLR.

POISONSTAT

DDRCTRL AXI Poison status register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RD_POISON_INTR_1
r 		RD_POISON_INTR_0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_POISON_INTR_1
r 		WR_POISON_INTR_0
r
Toggle fields

WR_POISON_INTR_0

Bit 0: WR_POISON_INTR_0.

WR_POISON_INTR_1

Bit 1: WR_POISON_INTR_1.

RD_POISON_INTR_0

Bit 16: RD_POISON_INTR_0.

RD_POISON_INTR_1

Bit 17: RD_POISON_INTR_1.

PSTAT

DDRCTRL port status register

Offset: 0x3fc, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WR_PORT_BUSY_1
r 		WR_PORT_BUSY_0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_PORT_BUSY_1
r 		RD_PORT_BUSY_0
r
Toggle fields

RD_PORT_BUSY_0

Bit 0: RD_PORT_BUSY_0.

RD_PORT_BUSY_1

Bit 1: RD_PORT_BUSY_1.

WR_PORT_BUSY_0

Bit 16: WR_PORT_BUSY_0.

WR_PORT_BUSY_1

Bit 17: WR_PORT_BUSY_1.

PCCFG

DDRCTRL port common configuration register

Offset: 0x400, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BL_EXP_MODE
rw 		PAGEMATCH_LIMIT
rw 		GO2CRITICAL_EN
rw
Toggle fields

GO2CRITICAL_EN

Bit 0: GO2CRITICAL_EN.

PAGEMATCH_LIMIT

Bit 4: PAGEMATCH_LIMIT.

BL_EXP_MODE

Bit 8: BL_EXP_MODE.

PCFGR_0

DDRCTRL port 0 configuration read register

Offset: 0x404, size: 32, reset: 0x00004000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDWR_ORDERED_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_PORT_PAGEMATCH_EN
rw 		RD_PORT_URGENT_EN
rw 		RD_PORT_AGING_EN
rw 		RD_PORT_PRIORITY
rw
Toggle fields

RD_PORT_PRIORITY

Bits 0-9: RD_PORT_PRIORITY.

RD_PORT_AGING_EN

Bit 12: RD_PORT_AGING_EN.

RD_PORT_URGENT_EN

Bit 13: RD_PORT_URGENT_EN.

RD_PORT_PAGEMATCH_EN

Bit 14: RD_PORT_PAGEMATCH_EN.

RDWR_ORDERED_EN

Bit 16: RDWR_ORDERED_EN.

PCFGW_0

DDRCTRL port 0 configuration write register

Offset: 0x408, size: 32, reset: 0x00004000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_PORT_PAGEMATCH_EN
rw 		WR_PORT_URGENT_EN
rw 		WR_PORT_AGING_EN
rw 		WR_PORT_PRIORITY
rw
Toggle fields

WR_PORT_PRIORITY

Bits 0-9: WR_PORT_PRIORITY.

WR_PORT_AGING_EN

Bit 12: WR_PORT_AGING_EN.

WR_PORT_URGENT_EN

Bit 13: WR_PORT_URGENT_EN.

WR_PORT_PAGEMATCH_EN

Bit 14: WR_PORT_PAGEMATCH_EN.

PCTRL_0

DDRCTRL port 0 control register

Offset: 0x490, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_EN
rw
Toggle fields

PORT_EN

Bit 0: PORT_EN.

PCFGQOS0_0

DDRCTRL port 0 read Q0S configuration register 0

Offset: 0x494, size: 32, reset: 0x02000E00, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RQOS_MAP_REGION2
rw 		RQOS_MAP_REGION1
rw 		RQOS_MAP_REGION0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RQOS_MAP_LEVEL2
rw 		RQOS_MAP_LEVEL1
rw
Toggle fields

RQOS_MAP_LEVEL1

Bits 0-3: RQOS_MAP_LEVEL1.

RQOS_MAP_LEVEL2

Bits 8-11: RQOS_MAP_LEVEL2.

RQOS_MAP_REGION0

Bits 16-17: RQOS_MAP_REGION0.

RQOS_MAP_REGION1

Bits 20-21: RQOS_MAP_REGION1.

RQOS_MAP_REGION2

Bits 24-25: RQOS_MAP_REGION2.

PCFGQOS1_0

DDRCTRL port 0 read Q0S configuration register 1

Offset: 0x498, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RQOS_MAP_TIMEOUTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RQOS_MAP_TIMEOUTB
rw
Toggle fields

RQOS_MAP_TIMEOUTB

Bits 0-10: RQOS_MAP_TIMEOUTB.

RQOS_MAP_TIMEOUTR

Bits 16-26: RQOS_MAP_TIMEOUTR.

PCFGWQOS0_0

DDRCTRL port 0 write Q0S configuration register 0

Offset: 0x49c, size: 32, reset: 0x00000E00, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WQOS_MAP_REGION2
rw 		WQOS_MAP_REGION1
rw 		WQOS_MAP_REGION0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WQOS_MAP_LEVEL2
rw 		WQOS_MAP_LEVEL1
rw
Toggle fields

WQOS_MAP_LEVEL1

Bits 0-3: WQOS_MAP_LEVEL1.

WQOS_MAP_LEVEL2

Bits 8-11: WQOS_MAP_LEVEL2.

WQOS_MAP_REGION0

Bits 16-17: WQOS_MAP_REGION0.

WQOS_MAP_REGION1

Bits 20-21: WQOS_MAP_REGION1.

WQOS_MAP_REGION2

Bits 24-25: WQOS_MAP_REGION2.

PCFGWQOS1_0

DDRCTRL port 0 write Q0S configuration register 1

Offset: 0x4a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WQOS_MAP_TIMEOUT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WQOS_MAP_TIMEOUT1
rw
Toggle fields

WQOS_MAP_TIMEOUT1

Bits 0-10: WQOS_MAP_TIMEOUT1.

WQOS_MAP_TIMEOUT2

Bits 16-26: WQOS_MAP_TIMEOUT2.

PCFGR_1

DDRCTRL port 1 configuration read register

Offset: 0x4b4, size: 32, reset: 0x00004000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDWR_ORDERED_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD_PORT_PAGEMATCH_EN
rw 		RD_PORT_URGENT_EN
rw 		RD_PORT_AGING_EN
rw 		RD_PORT_PRIORITY
rw
Toggle fields

RD_PORT_PRIORITY

Bits 0-9: RD_PORT_PRIORITY.

RD_PORT_AGING_EN

Bit 12: RD_PORT_AGING_EN.

RD_PORT_URGENT_EN

Bit 13: RD_PORT_URGENT_EN.

RD_PORT_PAGEMATCH_EN

Bit 14: RD_PORT_PAGEMATCH_EN.

RDWR_ORDERED_EN

Bit 16: RDWR_ORDERED_EN.

PCFGW_1

DDRCTRL port 1 configuration write register

Offset: 0x4b8, size: 32, reset: 0x00004000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WR_PORT_PAGEMATCH_EN
rw 		WR_PORT_URGENT_EN
rw 		WR_PORT_AGING_EN
rw 		WR_PORT_PRIORITY
rw
Toggle fields

WR_PORT_PRIORITY

Bits 0-9: WR_PORT_PRIORITY.

WR_PORT_AGING_EN

Bit 12: WR_PORT_AGING_EN.

WR_PORT_URGENT_EN

Bit 13: WR_PORT_URGENT_EN.

WR_PORT_PAGEMATCH_EN

Bit 14: WR_PORT_PAGEMATCH_EN.

PCTRL_1

DDRCTRL port 1 control register

Offset: 0x540, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_EN
rw
Toggle fields

PORT_EN

Bit 0: PORT_EN.

PCFGQOS0_1

DDRCTRL port 1 read Q0S configuration register 0

Offset: 0x544, size: 32, reset: 0x02000E00, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RQOS_MAP_REGION2
rw 		RQOS_MAP_REGION1
rw 		RQOS_MAP_REGION0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RQOS_MAP_LEVEL2
rw 		RQOS_MAP_LEVEL1
rw
Toggle fields

RQOS_MAP_LEVEL1

Bits 0-3: RQOS_MAP_LEVEL1.

RQOS_MAP_LEVEL2

Bits 8-11: RQOS_MAP_LEVEL2.

RQOS_MAP_REGION0

Bits 16-17: RQOS_MAP_REGION0.

RQOS_MAP_REGION1

Bits 20-21: RQOS_MAP_REGION1.

RQOS_MAP_REGION2

Bits 24-25: RQOS_MAP_REGION2.

PCFGQOS1_1

DDRCTRL port 1 read Q0S configuration register 1

Offset: 0x548, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RQOS_MAP_TIMEOUTR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RQOS_MAP_TIMEOUTB
rw
Toggle fields

RQOS_MAP_TIMEOUTB

Bits 0-10: RQOS_MAP_TIMEOUTB.

RQOS_MAP_TIMEOUTR

Bits 16-26: RQOS_MAP_TIMEOUTR.

PCFGWQOS0_1

DDRCTRL port 1 write Q0S configuration register 0

Offset: 0x54c, size: 32, reset: 0x00000E00, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WQOS_MAP_REGION2
rw 		WQOS_MAP_REGION1
rw 		WQOS_MAP_REGION0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WQOS_MAP_LEVEL2
rw 		WQOS_MAP_LEVEL1
rw
Toggle fields

WQOS_MAP_LEVEL1

Bits 0-3: WQOS_MAP_LEVEL1.

WQOS_MAP_LEVEL2

Bits 8-11: WQOS_MAP_LEVEL2.

WQOS_MAP_REGION0

Bits 16-17: WQOS_MAP_REGION0.

WQOS_MAP_REGION1

Bits 20-21: WQOS_MAP_REGION1.

WQOS_MAP_REGION2

Bits 24-25: WQOS_MAP_REGION2.

PCFGWQOS1_1

DDRCTRL port 1 write Q0S configuration register 1

Offset: 0x550, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WQOS_MAP_TIMEOUT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WQOS_MAP_TIMEOUT1
rw
Toggle fields

WQOS_MAP_TIMEOUT1

Bits 0-10: WQOS_MAP_TIMEOUT1.

WQOS_MAP_TIMEOUT2

Bits 16-26: WQOS_MAP_TIMEOUT2.

DDRPERFM

0x5a007000: DDRPERFM

14/22 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTL
0x4 CFG
0x8 STATUS
0xc CCR
0x10 IER
0x14 ISR
0x18 ICR
0x20 TCNT
0x60 CNT0
0x68 CNT1
0x70 CNT2
0x78 CNT3
0x3f0 HWCFG
0x3f4 VER
0x3f8 ID
0x3fc SID
Toggle registers

CTL

Write-only register. A read request returns all zeros.

Offset: 0x0, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
w 		START
w
Toggle fields

START

Bit 0: START.

STOP

Bit 1: STOP.

CFG

DDRPERFM configurationl register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN
rw
Toggle fields

EN

Bits 0-3: EN.

SEL

Bits 16-17: SEL.

STATUS

DDRPERFM status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOVF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COVF
r
Toggle fields

COVF

Bits 0-3: COVF.

BUSY

Bit 16: BUSY.

TOVF

Bit 31: TOVF.

CCR

Write-only register. A read request returns all zeros

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCLR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCLR
w
Toggle fields

CCLR

Bits 0-3: CCLR.

TCLR

Bit 31: TCLR.

IER

DDRPERFM interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVFIE
rw
Toggle fields

OVFIE

Bit 0: OVFIE.

ISR

DDRPERFM interrupt status register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVFF
r
Toggle fields

OVFF

Bit 0: OVFF.

ICR

Write-only register. A read request returns all zeros

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVF
w
Toggle fields

OVF

Bit 0: OVF.

TCNT

DDRPERFM time counter register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-31: CNT.

CNT0

DDRPERFM event counter 0 register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-31: CNT.

CNT1

DDRPERFM event counter 1 register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-31: CNT.

CNT2

DDRPERFM event counter 2 register

Offset: 0x70, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-31: CNT.

CNT3

DDRPERFM event counter 3 register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-31: CNT.

HWCFG

DDRPERFM hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCNT
r
Toggle fields

NCNT

Bits 0-3: NCNT.

VER

DDRPERFM version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

ID

DDRPERFM ID register

Offset: 0x3f8, size: 32, reset: 0x00140061, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SID

DDRPERFM magic ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DDRPHYC

0x5a004000: DDRPHYC

61/386 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RIDR
0x4 PIR
0x8 PGCR
0xc PGSR
0x10 DLLGCR
0x14 ACDLLCR
0x18 PTR0
0x1c PTR1
0x20 PTR2
0x24 ACIOCR
0x28 DXCCR
0x2c DSGCR
0x30 DCR
0x34 DTPR0
0x38 DTPR1
0x3c DTPR2
0x40 (16-bit) DDR3_MR0
0x44 (16-bit) DDR3_MR1
0x48 (16-bit) DDR3_MR2
0x4c (8-bit) DDR3_MR3
0x50 ODTCR
0x54 DTAR
0x58 DTDR0
0x5c DTDR1
0x178 GPR0
0x17c GPR1
0x180 ZQ0CR0
0x184 (8-bit) ZQ0CR1
0x188 ZQ0SR0
0x18c (8-bit) ZQ0SR1
0x1c0 DX0GCR
0x1c4 (16-bit) DX0GSR0
0x1c8 DX0GSR1
0x1cc DX0DLLCR
0x1d0 DX0DQTR
0x1d4 DX0DQSTR
0x200 DX1GCR
0x204 (16-bit) DX1GSR0
0x208 DX1GSR1
0x20c DX1DLLCR
0x210 DX1DQTR
0x214 DX1DQSTR
0x240 DX2GCR
0x244 (16-bit) DX2GSR0
0x248 DX2GSR1
0x24c DX2DLLCR
0x250 DX2DQTR
0x254 DX2DQSTR
0x280 DX3GCR
0x284 (16-bit) DX3GSR0
0x288 DX3GSR1
0x28c DX3DLLCR
0x290 DX3DQTR
0x294 DX3DQSTR
Toggle registers

RIDR

DDRPHYC revision ID register

Offset: 0x0, size: 32, reset: 0x00410010, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRID
r 		PHYMJR
r 		PHYMDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYMNR
r 		PUBMJR
r 		PUBMDR
r 		PUBMNR
r
Toggle fields

PUBMNR

Bits 0-3: PUBMNR.

PUBMDR

Bits 4-7: PUBMDR.

PUBMJR

Bits 8-11: PUBMJR.

PHYMNR

Bits 12-15: PHYMNR.

PHYMDR

Bits 16-19: PHYMDR.

PHYMJR

Bits 20-23: PHYMJR.

UDRID

Bits 24-31: UDRID.

PIR

DDRPHYC PHY initialization register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INITBYP
w 		ZCALBYP
w 		LOCKBYP
w 		CLRSR
w 		CTLDINIT
w 		DLLBYP
w 		ICPC
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVTRN
w 		QSTRN
w 		DRAMINIT
w 		DRAMRST
w 		ITMSRST
w 		ZCAL
w 		DLLLOCK
w 		DLLSRST
w 		INIT
w
Toggle fields

INIT

Bit 0: INIT.

DLLSRST

Bit 1: DLLSRST.

DLLLOCK

Bit 2: DLLLOCK.

ZCAL

Bit 3: ZCAL.

ITMSRST

Bit 4: ITMSRST.

DRAMRST

Bit 5: DRAMRST.

DRAMINIT

Bit 6: DRAMINIT.

QSTRN

Bit 7: QSTRN.

RVTRN

Bit 8: RVTRN.

ICPC

Bit 16: ICPC.

DLLBYP

Bit 17: DLLBYP.

CTLDINIT

Bit 18: CTLDINIT.

CLRSR

Bit 28: CLRSR.

LOCKBYP

Bit 29: LOCKBYP.

ZCALBYP

Bit 30: ZCALBYP.

INITBYP

Bit 31: INITBYP.

PGCR

DDRPHYC PHY global control register

Offset: 0x8, size: 32, reset: 0x01BC2E04, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LBMODE
rw 		LBGDQS
rw 		LBDQSS
rw 		RFSHDT
rw 		PDDISDX
rw 		ZKSEL
rw 		RANKEN
rw 		IODDRM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOLB
rw 		CKINV
rw 		CKDV
rw 		CKEN
rw 		DTOSEL
rw 		DFTLMT
rw 		DFTCMP
rw 		DQSCFG
rw 		ITMDMD
rw
Toggle fields

ITMDMD

Bit 0: ITMDMD.

DQSCFG

Bit 1: DQSCFG.

DFTCMP

Bit 2: DFTCMP.

DFTLMT

Bits 3-4: DFTLMT.

DTOSEL

Bits 5-8: DTOSEL.

CKEN

Bits 9-11: CKEN.

CKDV

Bits 12-13: CKDV.

CKINV

Bit 14: CKINV.

IOLB

Bit 15: IOLB.

IODDRM

Bits 16-17: IODDRM.

RANKEN

Bits 18-21: RANKEN.

ZKSEL

Bits 22-23: ZKSEL.

PDDISDX

Bit 24: PDDISDX.

RFSHDT

Bits 25-28: RFSHDT.

LBDQSS

Bit 29: LBDQSS.

LBGDQS

Bit 30: LBGDQS.

LBMODE

Bit 31: LBMODE.

PGSR

DDRPHYC PHY global status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

11/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVEIRR
r 		RVERR
r 		DFTERR
r 		DTIERR
r 		DTERR
r 		DTDONE
r 		DIDONE
r 		ZCDDONE
r 		DLDONE
r 		IDONE
r
Toggle fields

IDONE

Bit 0: IDONE.

DLDONE

Bit 1: DLDONE.

ZCDDONE

Bit 2: ZCDDONE.

DIDONE

Bit 3: DIDONE.

DTDONE

Bit 4: DTDONE.

DTERR

Bit 5: DTERR.

DTIERR

Bit 6: DTIERR.

DFTERR

Bit 7: DFTERR.

RVERR

Bit 8: RVERR.

RVEIRR

Bit 9: RVEIRR.

TQ

Bit 31: TQ.

DLLGCR

DDRPHYC DDR global control register

Offset: 0x10, size: 32, reset: 0x03737000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLRSVD2
rw 		LOCKDET
rw 		FDTRMSL
rw 		SBIAS5_3
rw 		BPS200
rw 		SBIAS2_0
rw 		MBIAS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBIAS
rw 		TESTSW
rw 		ATC
rw 		DTC
rw 		TESTEN
rw 		IPUMP
rw 		DRES
rw
Toggle fields

DRES

Bits 0-1: DRES.

IPUMP

Bits 2-4: IPUMP.

TESTEN

Bit 5: TESTEN.

DTC

Bits 6-8: DTC.

ATC

Bits 9-10: ATC.

TESTSW

Bit 11: TESTSW.

MBIAS

Bits 12-19: MBIAS.

SBIAS2_0

Bits 20-22: SBIAS2_0.

BPS200

Bit 23: BPS200.

SBIAS5_3

Bits 24-26: SBIAS5_3.

FDTRMSL

Bits 27-28: FDTRMSL.

LOCKDET

Bit 29: LOCKDET.

DLLRSVD2

Bits 30-31: DLLRSVD2.

ACDLLCR

DDRPHYC AC DLL control register

Offset: 0x14, size: 32, reset: 0x40000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLDIS
rw 		DLLSRST
rw 		ATESTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFWDLY
rw 		MFBDLY
rw
Toggle fields

MFBDLY

Bits 6-8: MFBDLY.

MFWDLY

Bits 9-11: MFWDLY.

ATESTEN

Bit 18: ATESTEN.

DLLSRST

Bit 30: DLLSRST.

DLLDIS

Bit 31: DLLDIS.

PTR0

DDRPHYC PT register 0

Offset: 0x18, size: 32, reset: 0x0022AF9B, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TITMSRST
rw 		TDLLLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDLLLOCK
rw 		TDLLSRST
rw
Toggle fields

TDLLSRST

Bits 0-5: TDLLSRST.

TDLLLOCK

Bits 6-17: TDLLLOCK.

TITMSRST

Bits 18-21: TITMSRST.

PTR1

DDRPHYC PT register 1

Offset: 0x1c, size: 32, reset: 0x0604111D, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDINIT1
rw 		TDINIT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDINIT0
rw
Toggle fields

TDINIT0

Bits 0-18: TDINIT0.

TDINIT1

Bits 19-26: TDINIT1.

PTR2

DDRPHYC PT register 2

Offset: 0x20, size: 32, reset: 0x042DA072, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDINIT3
rw 		TDINIT2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDINIT2
rw
Toggle fields

TDINIT2

Bits 0-16: TDINIT2.

TDINIT3

Bits 17-26: TDINIT3.

ACIOCR

DDRPHYC ACIOC register

Offset: 0x24, size: 32, reset: 0x33C03812, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACSR
rw 		RSTIOM
rw 		RSTPDR
rw 		RSTPDD
rw 		RSTODT
rw 		RANKPDR
rw 		CSPDD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RANKODT
rw 		CKPDR
rw 		CKPDD
rw 		CKODT
rw 		ACPDR
rw 		ACPDD
rw 		ACODT
rw 		ACOE
rw 		ACIOM
rw
Toggle fields

ACIOM

Bit 0: ACIOM.

ACOE

Bit 1: ACOE.

ACODT

Bit 2: ACODT.

ACPDD

Bit 3: ACPDD.

ACPDR

Bit 4: ACPDR.

CKODT

Bits 5-7: CKODT.

CKPDD

Bits 8-10: CKPDD.

CKPDR

Bits 11-13: CKPDR.

RANKODT

Bit 14: RANKODT.

CSPDD

Bit 18: CSPDD.

RANKPDR

Bit 22: RANKPDR.

RSTODT

Bit 26: RSTODT.

RSTPDD

Bit 27: RSTPDD.

RSTPDR

Bit 28: RSTPDR.

RSTIOM

Bit 29: RSTIOM.

ACSR

Bits 30-31: ACSR.

DXCCR

DDRPHYC DXCC register

Offset: 0x28, size: 32, reset: 0x00000800, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVSEL
rw 		DQSNRST
rw 		DQSNRES
rw 		DQSRES
rw 		DXPDR
rw 		DXPDD
rw 		DXIOM
rw 		DXODT
rw
Toggle fields

DXODT

Bit 0: DXODT.

DXIOM

Bit 1: DXIOM.

DXPDD

Bit 2: DXPDD.

DXPDR

Bit 3: DXPDR.

DQSRES

Bits 4-7: DQSRES.

DQSNRES

Bits 8-11: DQSNRES.

DQSNRST

Bit 14: DQSNRST.

RVSEL

Bit 15: RVSEL.

AWDT

Bit 16: AWDT.

DSGCR

DDRPHYC DSGC register

Offset: 0x2c, size: 32, reset: 0xFA00001F, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKEOE
rw 		RSTOE
rw 		ODTOE
rw 		CKOE
rw 		TPDOE
rw 		TPDPD
rw 		NL2OE
rw 		NL2PD
rw 		ODTPDD
rw 		CKEPDD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FXDLAT
rw 		NOBUB
rw 		DQSGE
rw 		DQSGX
rw 		LPDLLPD
rw 		LPIOPD
rw 		ZUEN
rw 		BDISEN
rw 		PUREN
rw
Toggle fields

PUREN

Bit 0: PUREN.

BDISEN

Bit 1: BDISEN.

ZUEN

Bit 2: ZUEN.

LPIOPD

Bit 3: LPIOPD.

LPDLLPD

Bit 4: LPDLLPD.

DQSGX

Bits 5-7: DQSGX.

DQSGE

Bits 8-10: DQSGE.

NOBUB

Bit 11: NOBUB.

FXDLAT

Bit 12: FXDLAT.

CKEPDD

Bit 16: CKEPDD.

ODTPDD

Bit 20: ODTPDD.

NL2PD

Bit 24: NL2PD.

NL2OE

Bit 25: NL2OE.

TPDPD

Bit 26: TPDPD.

TPDOE

Bit 27: TPDOE.

CKOE

Bit 28: CKOE.

ODTOE

Bit 29: ODTOE.

RSTOE

Bit 30: RSTOE.

CKEOE

Bit 31: CKEOE.

DCR

DDRPHYC DC register

Offset: 0x30, size: 32, reset: 0x0000000B, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPD
rw 		RDIMM
rw 		UDIMM
rw 		DDR2T
rw 		NOSRA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRTYPE
rw 		MPRDQ
rw 		PDQ
rw 		DDR8BNK
rw 		DDRMD
rw
Toggle fields

DDRMD

Bits 0-2: DDRMD.

DDR8BNK

Bit 3: DDR8BNK.

PDQ

Bits 4-6: PDQ.

MPRDQ

Bit 7: MPRDQ.

DDRTYPE

Bits 8-9: DDRTYPE.

NOSRA

Bit 27: NOSRA.

DDR2T

Bit 28: DDR2T.

UDIMM

Bit 29: UDIMM.

RDIMM

Bit 30: RDIMM.

TPD

Bit 31: TPD.

DTPR0

DDRPHYC DTP register 0

Offset: 0x34, size: 32, reset: 0x3012666E, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCCD
rw 		TRC
rw 		TRRD
rw 		TRAS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRCD
rw 		TRP
rw 		TWTR
rw 		TRTP
rw 		TMRD
rw
Toggle fields

TMRD

Bits 0-1: TMRD.

TRTP

Bits 2-4: TRTP.

TWTR

Bits 5-7: TWTR.

TRP

Bits 8-11: TRP.

TRCD

Bits 12-15: TRCD.

TRAS

Bits 16-20: TRAS.

TRRD

Bits 21-24: TRRD.

TRC

Bits 25-30: TRC.

TCCD

Bit 31: TCCD.

DTPR1

DDRPHYC DTP register 1

Offset: 0x38, size: 32, reset: 0x0A030090, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDQSCKMAX
rw 		TDQSCKMIN
rw 		TRFC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRTODT
rw 		TMOD
rw 		TFAW
rw 		TRTW
rw 		TAOND
rw
Toggle fields

TAOND

Bits 0-1: TAOND.

TRTW

Bit 2: TRTW.

TFAW

Bits 3-8: TFAW.

TMOD

Bits 9-10: TMOD.

TRTODT

Bit 11: TRTODT.

TRFC

Bits 16-23: TRFC.

TDQSCKMIN

Bits 24-26: TDQSCKMIN.

TDQSCKMAX

Bits 27-29: TDQSCKMAX.

DTPR2

DDRPHYC DTP register 2

Offset: 0x3c, size: 32, reset: 0x20040D84, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDLLK
rw 		TCKE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCKE
rw 		TXP
rw 		TXS
rw
Toggle fields

TXS

Bits 0-9: TXS.

TXP

Bits 10-14: TXP.

TCKE

Bits 15-18: TCKE.

TDLLK

Bits 19-28: TDLLK.

DDR3_MR0

DDRPHYC MR0 register for DDR3

Offset: 0x40, size: 16, reset: 0x00000A52, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
rw 		PD
rw 		WR
rw 		DR
rw 		TM
rw 		CL
rw 		BT
rw 		CL0
rw 		BL
rw
Toggle fields

BL

Bits 0-1: BL.

CL0

Bit 2: CL0.

BT

Bit 3: BT.

CL

Bits 4-6: CL.

TM

Bit 7: TM.

DR

Bit 8: DR.

WR

Bits 9-11: WR.

PD

Bit 12: PD.

RSVD

Bits 13-15: RSVD.

DDR3_MR1

DDRPHYC MR1 register for DDR3

Offset: 0x44, size: 16, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QOFF
rw 		TDQS
rw 		RTT2
rw 		LEVEL
rw 		RTT1
rw 		DIC1
rw 		AL
rw 		RTT0
rw 		DIC0
rw 		DE
rw
Toggle fields

DE

Bit 0: DE.

DIC0

Bit 1: DIC0.

RTT0

Bit 2: RTT0.

AL

Bits 3-4: AL.

DIC1

Bit 5: DIC1.

RTT1

Bit 6: RTT1.

LEVEL

Bit 7: LEVEL.

RTT2

Bit 9: RTT2.

TDQS

Bit 11: TDQS.

QOFF

Bit 12: QOFF.

DDR3_MR2

DDRPHYC MR2 register for DDR3

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTTWR
rw 		SRT
rw 		ASR
rw 		CWL
rw 		PASR
rw
Toggle fields

PASR

Bits 0-2: PASR.

CWL

Bits 3-5: CWL.

ASR

Bit 6: ASR.

SRT

Bit 7: SRT.

RTTWR

Bits 9-10: RTTWR.

DDR3_MR3

DDRPHYC MR3 register for DDR3

Offset: 0x4c, size: 8, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPR
rw 		MPRLOC
rw
Toggle fields

MPRLOC

Bits 0-1: MPRLOC.

MPR

Bit 2: MPR.

ODTCR

DDRPHYC ODTC register

Offset: 0x50, size: 32, reset: 0x84210000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRODT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDODT
rw
Toggle fields

RDODT

Bit 0: RDODT.

WRODT

Bit 16: WRODT.

DTAR

DDRPHYC DTA register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTMPR
rw 		DTBANK
rw 		DTROW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTROW
rw 		DTCOL
rw
Toggle fields

DTCOL

Bits 0-11: DTCOL.

DTROW

Bits 12-27: DTROW.

DTBANK

Bits 28-30: DTBANK.

DTMPR

Bit 31: DTMPR.

DTDR0

DDRPHYC DTD register 0

Offset: 0x58, size: 32, reset: 0xDD22EE11, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTBYTE3
rw 		DTBYTE2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTBYTE1
rw 		DTBYTE0
rw
Toggle fields

DTBYTE0

Bits 0-7: DTBYTE0.

DTBYTE1

Bits 8-15: DTBYTE1.

DTBYTE2

Bits 16-23: DTBYTE2.

DTBYTE3

Bits 24-31: DTBYTE3.

DTDR1

DDRPHYC DTD register 1

Offset: 0x5c, size: 32, reset: 0x7788BB44, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTBYTE7
rw 		DTBYTE6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTBYTE5
rw 		DTBYTE4
rw
Toggle fields

DTBYTE4

Bits 0-7: DTBYTE4.

DTBYTE5

Bits 8-15: DTBYTE5.

DTBYTE6

Bits 16-23: DTBYTE6.

DTBYTE7

Bits 24-31: DTBYTE7.

GPR0

DDRPHYC general purpose register 0

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR0
rw
Toggle fields

GPR0

Bits 0-31: GPR0.

GPR1

DDRPHYC general purpose register 1

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR1
rw
Toggle fields

GPR1

Bits 0-31: GPR1.

ZQ0CR0

DDRPHYC ZQ0C register 0

Offset: 0x180, size: 32, reset: 0x0000014A, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ZQPD
rw 		ZCAL
rw 		ZCALBYP
rw 		ZDEN
rw 		ZDATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZDATA
rw
Toggle fields

ZDATA

Bits 0-19: ZDATA.

ZDEN

Bit 28: ZDEN.

ZCALBYP

Bit 29: ZCALBYP.

ZCAL

Bit 30: ZCAL.

ZQPD

Bit 31: ZQPD.

ZQ0CR1

DDRPHYC ZQ0CR1 register

Offset: 0x184, size: 8, reset: 0x0000007B, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZPROG
rw
Toggle fields

ZPROG

Bits 0-7: ZPROG.

ZQ0SR0

DDRPHYC ZQ0S register 0

Offset: 0x188, size: 32, reset: 0x0000014A, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ZDONE
r 		ZERR
r 		ZCTRL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ZCTRL
r
Toggle fields

ZCTRL

Bits 0-19: ZCTRL.

ZERR

Bit 30: ZERR.

ZDONE

Bit 31: ZDONE.

ZQ0SR1

DDRPHYC ZQ0S register 1

Offset: 0x18c, size: 8, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPU
r 		OPD
r 		ZPU
r 		ZPD
r
Toggle fields

ZPD

Bits 0-1: ZPD.

ZPU

Bits 2-3: ZPU.

OPD

Bits 4-5: OPD.

OPU

Bits 6-7: OPU.

DX0GCR

DDRPHYC byte lane 0 GC register

Offset: 0x1c0, size: 32, reset: 0x0000EE81, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0RVSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0RVSL
rw 		RTTOAL
rw 		RTTOH
rw 		DQRTT
rw 		DQSRTT
rw 		DSEN
rw 		DQSRPD
rw 		DXPDR
rw 		DXPDD
rw 		DXIOM
rw 		DQODT
rw 		DQSODT
rw 		DXEN
rw
Toggle fields

DXEN

Bit 0: DXEN.

DQSODT

Bit 1: DQSODT.

DQODT

Bit 2: DQODT.

DXIOM

Bit 3: DXIOM.

DXPDD

Bit 4: DXPDD.

DXPDR

Bit 5: DXPDR.

DQSRPD

Bit 6: DQSRPD.

DSEN

Bits 7-8: DSEN.

DQSRTT

Bit 9: DQSRTT.

DQRTT

Bit 10: DQRTT.

RTTOH

Bits 11-12: RTTOH.

RTTOAL

Bit 13: RTTOAL.

R0RVSL

Bits 14-16: R0RVSL.

DX0GSR0

DDRPHYC byte lane 0 GS register 0

Offset: 0x1c4, size: 16, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTPASS
r 		DTIERR
r 		DTERR
r 		DTDONE
r
Toggle fields

DTDONE

Bit 0: DTDONE.

DTERR

Bit 4: DTERR.

DTIERR

Bit 8: DTIERR.

DTPASS

Bits 13-15: DTPASS.

DX0GSR1

DDRPHYC byte lane 0 GS register 1

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RVPASS
r 		RVIERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVERR
r 		DQSDFT
r 		DFTERR
r
Toggle fields

DFTERR

Bit 0: DFTERR.

DQSDFT

Bits 4-5: DQSDFT.

RVERR

Bit 12: RVERR.

RVIERR

Bit 16: RVIERR.

RVPASS

Bits 20-22: RVPASS.

DX0DLLCR

DDRPHYC byte lane 0 DLLC register

Offset: 0x1cc, size: 32, reset: 0x40000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLDIS
rw 		DLLSRST
rw 		SDLBMODE
rw 		ATESTEN
rw 		SDPHASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDPHASE
rw 		SSTART
rw 		MFWDLY
rw 		MFBDLY
rw 		SFWDLY
rw 		SFBDLY
rw
Toggle fields

SFBDLY

Bits 0-2: SFBDLY.

SFWDLY

Bits 3-5: SFWDLY.

MFBDLY

Bits 6-8: MFBDLY.

MFWDLY

Bits 9-11: MFWDLY.

SSTART

Bits 12-13: SSTART.

SDPHASE

Bits 14-17: SDPHASE.

ATESTEN

Bit 18: ATESTEN.

SDLBMODE

Bit 19: SDLBMODE.

DLLSRST

Bit 30: DLLSRST.

DLLDIS

Bit 31: DLLDIS.

DX0DQTR

DDRPHYC byte lane 0 DQT register

Offset: 0x1d0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQDLY7
rw 		DQDLY6
rw 		DQDLY5
rw 		DQDLY4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DQDLY3
rw 		DQDLY2
rw 		DQDLY1
rw 		DQDLY0
rw
Toggle fields

DQDLY0

Bits 0-3: DQDLY0.

DQDLY1

Bits 4-7: DQDLY1.

DQDLY2

Bits 8-11: DQDLY2.

DQDLY3

Bits 12-15: DQDLY3.

DQDLY4

Bits 16-19: DQDLY4.

DQDLY5

Bits 20-23: DQDLY5.

DQDLY6

Bits 24-27: DQDLY6.

DQDLY7

Bits 28-31: DQDLY7.

DX0DQSTR

DDRPHYC byte lane 0 DQST register

Offset: 0x1d4, size: 32, reset: 0x3DB02000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMDLY
rw 		DQSNDLY
rw 		DQSDLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0DGPS
rw 		R0DGSL
rw
Toggle fields

R0DGSL

Bits 0-2: R0DGSL.

R0DGPS

Bits 12-13: R0DGPS.

DQSDLY

Bits 20-22: DQSDLY.

DQSNDLY

Bits 23-25: DQSNDLY.

DMDLY

Bits 26-29: DMDLY.

DX1GCR

DDRPHYC byte lane 1 GC register

Offset: 0x200, size: 32, reset: 0x0000EE81, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0RVSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0RVSL
rw 		RTTOAL
rw 		RTTOH
rw 		DQRTT
rw 		DQSRTT
rw 		DSEN
rw 		DQSRPD
rw 		DXPDR
rw 		DXPDD
rw 		DXIOM
rw 		DQODT
rw 		DQSODT
rw 		DXEN
rw
Toggle fields

DXEN

Bit 0: DXEN.

DQSODT

Bit 1: DQSODT.

DQODT

Bit 2: DQODT.

DXIOM

Bit 3: DXIOM.

DXPDD

Bit 4: DXPDD.

DXPDR

Bit 5: DXPDR.

DQSRPD

Bit 6: DQSRPD.

DSEN

Bits 7-8: DSEN.

DQSRTT

Bit 9: DQSRTT.

DQRTT

Bit 10: DQRTT.

RTTOH

Bits 11-12: RTTOH.

RTTOAL

Bit 13: RTTOAL.

R0RVSL

Bits 14-16: R0RVSL.

DX1GSR0

DDRPHYC byte lane 1 GS register 0

Offset: 0x204, size: 16, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTPASS
r 		DTIERR
r 		DTERR
r 		DTDONE
r
Toggle fields

DTDONE

Bit 0: DTDONE.

DTERR

Bit 4: DTERR.

DTIERR

Bit 8: DTIERR.

DTPASS

Bits 13-15: DTPASS.

DX1GSR1

DDRPHYC byte lane 1 GS register 1

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RVPASS
r 		RVIERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVERR
r 		DQSDFT
r 		DFTERR
r
Toggle fields

DFTERR

Bit 0: DFTERR.

DQSDFT

Bits 4-5: DQSDFT.

RVERR

Bit 12: RVERR.

RVIERR

Bit 16: RVIERR.

RVPASS

Bits 20-22: RVPASS.

DX1DLLCR

DDRPHYC byte lane 1 DLLC register

Offset: 0x20c, size: 32, reset: 0x40000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLDIS
rw 		DLLSRST
rw 		SDLBMODE
rw 		ATESTEN
rw 		SDPHASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDPHASE
rw 		SSTART
rw 		MFWDLY
rw 		MFBDLY
rw 		SFWDLY
rw 		SFBDLY
rw
Toggle fields

SFBDLY

Bits 0-2: SFBDLY.

SFWDLY

Bits 3-5: SFWDLY.

MFBDLY

Bits 6-8: MFBDLY.

MFWDLY

Bits 9-11: MFWDLY.

SSTART

Bits 12-13: SSTART.

SDPHASE

Bits 14-17: SDPHASE.

ATESTEN

Bit 18: ATESTEN.

SDLBMODE

Bit 19: SDLBMODE.

DLLSRST

Bit 30: DLLSRST.

DLLDIS

Bit 31: DLLDIS.

DX1DQTR

DDRPHYC byte lane 1 DQT register

Offset: 0x210, size: 32, reset: 0xFFFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQDLY7
rw 		DQDLY6
rw 		DQDLY5
rw 		DQDLY4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DQDLY3
rw 		DQDLY2
rw 		DQDLY1
rw 		DQDLY0
rw
Toggle fields

DQDLY0

Bits 0-3: DQDLY0.

DQDLY1

Bits 4-7: DQDLY1.

DQDLY2

Bits 8-11: DQDLY2.

DQDLY3

Bits 12-15: DQDLY3.

DQDLY4

Bits 16-19: DQDLY4.

DQDLY5

Bits 20-23: DQDLY5.

DQDLY6

Bits 24-27: DQDLY6.

DQDLY7

Bits 28-31: DQDLY7.

DX1DQSTR

DDRPHYC byte lane 1 DQST register

Offset: 0x214, size: 32, reset: 0x3DB02000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMDLY
rw 		DQSNDLY
rw 		DQSDLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0DGPS
rw 		R0DGSL
rw
Toggle fields

R0DGSL

Bits 0-2: R0DGSL.

R0DGPS

Bits 12-13: R0DGPS.

DQSDLY

Bits 20-22: DQSDLY.

DQSNDLY

Bits 23-25: DQSNDLY.

DMDLY

Bits 26-29: DMDLY.

DX2GCR

DDRPHYC byte lane 2 GC register

Offset: 0x240, size: 32, reset: 0x0000EE81, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0RVSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0RVSL
rw 		RTTOAL
rw 		RTTOH
rw 		DQRTT
rw 		DQSRTT
rw 		DSEN
rw 		DQSRPD
rw 		DXPDR
rw 		DXPDD
rw 		DXIOM
rw 		DQODT
rw 		DQSODT
rw 		DXEN
rw
Toggle fields

DXEN

Bit 0: DXEN.

DQSODT

Bit 1: DQSODT.

DQODT

Bit 2: DQODT.

DXIOM

Bit 3: DXIOM.

DXPDD

Bit 4: DXPDD.

DXPDR

Bit 5: DXPDR.

DQSRPD

Bit 6: DQSRPD.

DSEN

Bits 7-8: DSEN.

DQSRTT

Bit 9: DQSRTT.

DQRTT

Bit 10: DQRTT.

RTTOH

Bits 11-12: RTTOH.

RTTOAL

Bit 13: RTTOAL.

R0RVSL

Bits 14-16: R0RVSL.

DX2GSR0

DDRPHYC byte lane 2 GS register 0

Offset: 0x244, size: 16, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTPASS
r 		DTIERR
r 		DTERR
r 		DTDONE
r
Toggle fields

DTDONE

Bit 0: DTDONE.

DTERR

Bit 4: DTERR.

DTIERR

Bit 8: DTIERR.

DTPASS

Bits 13-15: DTPASS.

DX2GSR1

DDRPHYC byte lane 2 GS register 1

Offset: 0x248, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RVPASS
r 		RVIERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVERR
r 		DQSDFT
r 		DFTERR
r
Toggle fields

DFTERR

Bit 0: DFTERR.

DQSDFT

Bits 4-5: DQSDFT.

RVERR

Bit 12: RVERR.

RVIERR

Bit 16: RVIERR.

RVPASS

Bits 20-22: RVPASS.

DX2DLLCR

DDRPHYC byte lane 2 DLLC register

Offset: 0x24c, size: 32, reset: 0x40000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLDIS
rw 		DLLSRST
rw 		SDLBMODE
rw 		ATESTEN
rw 		SDPHASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDPHASE
rw 		SSTART
rw 		MFWDLY
rw 		MFBDLY
rw 		SFWDLY
rw 		SFBDLY
rw
Toggle fields

SFBDLY

Bits 0-2: SFBDLY.

SFWDLY

Bits 3-5: SFWDLY.

MFBDLY

Bits 6-8: MFBDLY.

MFWDLY

Bits 9-11: MFWDLY.

SSTART

Bits 12-13: SSTART.

SDPHASE

Bits 14-17: SDPHASE.

ATESTEN

Bit 18: ATESTEN.

SDLBMODE

Bit 19: SDLBMODE.

DLLSRST

Bit 30: DLLSRST.

DLLDIS

Bit 31: DLLDIS.

DX2DQTR

DDRPHYC byte lane 2 DQT register

Offset: 0x250, size: 32, reset: 0xFFFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQDLY7
rw 		DQDLY6
rw 		DQDLY5
rw 		DQDLY4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DQDLY3
rw 		DQDLY2
rw 		DQDLY1
rw 		DQDLY0
rw
Toggle fields

DQDLY0

Bits 0-3: DQDLY0.

DQDLY1

Bits 4-7: DQDLY1.

DQDLY2

Bits 8-11: DQDLY2.

DQDLY3

Bits 12-15: DQDLY3.

DQDLY4

Bits 16-19: DQDLY4.

DQDLY5

Bits 20-23: DQDLY5.

DQDLY6

Bits 24-27: DQDLY6.

DQDLY7

Bits 28-31: DQDLY7.

DX2DQSTR

DDRPHYC byte lane 2 DQST register

Offset: 0x254, size: 32, reset: 0x3DB02000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMDLY
rw 		DQSNDLY
rw 		DQSDLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0DGPS
rw 		R0DGSL
rw
Toggle fields

R0DGSL

Bits 0-2: R0DGSL.

R0DGPS

Bits 12-13: R0DGPS.

DQSDLY

Bits 20-22: DQSDLY.

DQSNDLY

Bits 23-25: DQSNDLY.

DMDLY

Bits 26-29: DMDLY.

DX3GCR

DDRPHYC byte lane 3 GC register

Offset: 0x280, size: 32, reset: 0x0000EE81, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R0RVSL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0RVSL
rw 		RTTOAL
rw 		RTTOH
rw 		DQRTT
rw 		DQSRTT
rw 		DSEN
rw 		DQSRPD
rw 		DXPDR
rw 		DXPDD
rw 		DXIOM
rw 		DQODT
rw 		DQSODT
rw 		DXEN
rw
Toggle fields

DXEN

Bit 0: DXEN.

DQSODT

Bit 1: DQSODT.

DQODT

Bit 2: DQODT.

DXIOM

Bit 3: DXIOM.

DXPDD

Bit 4: DXPDD.

DXPDR

Bit 5: DXPDR.

DQSRPD

Bit 6: DQSRPD.

DSEN

Bits 7-8: DSEN.

DQSRTT

Bit 9: DQSRTT.

DQRTT

Bit 10: DQRTT.

RTTOH

Bits 11-12: RTTOH.

RTTOAL

Bit 13: RTTOAL.

R0RVSL

Bits 14-16: R0RVSL.

DX3GSR0

DDRPHYC byte lane 3 GS register 0

Offset: 0x284, size: 16, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTPASS
r 		DTIERR
r 		DTERR
r 		DTDONE
r
Toggle fields

DTDONE

Bit 0: DTDONE.

DTERR

Bit 4: DTERR.

DTIERR

Bit 8: DTIERR.

DTPASS

Bits 13-15: DTPASS.

DX3GSR1

DDRPHYC byte lane 3 GS register 1

Offset: 0x288, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RVPASS
r 		RVIERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RVERR
r 		DQSDFT
r 		DFTERR
r
Toggle fields

DFTERR

Bit 0: DFTERR.

DQSDFT

Bits 4-5: DQSDFT.

RVERR

Bit 12: RVERR.

RVIERR

Bit 16: RVIERR.

RVPASS

Bits 20-22: RVPASS.

DX3DLLCR

DDRPHYC byte lane 3 DLLC register

Offset: 0x28c, size: 32, reset: 0x40000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLLDIS
rw 		DLLSRST
rw 		SDLBMODE
rw 		ATESTEN
rw 		SDPHASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDPHASE
rw 		SSTART
rw 		MFWDLY
rw 		MFBDLY
rw 		SFWDLY
rw 		SFBDLY
rw
Toggle fields

SFBDLY

Bits 0-2: SFBDLY.

SFWDLY

Bits 3-5: SFWDLY.

MFBDLY

Bits 6-8: MFBDLY.

MFWDLY

Bits 9-11: MFWDLY.

SSTART

Bits 12-13: SSTART.

SDPHASE

Bits 14-17: SDPHASE.

ATESTEN

Bit 18: ATESTEN.

SDLBMODE

Bit 19: SDLBMODE.

DLLSRST

Bit 30: DLLSRST.

DLLDIS

Bit 31: DLLDIS.

DX3DQTR

DDRPHYC byte lane 3 DQT register

Offset: 0x290, size: 32, reset: 0xFFFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DQDLY7
rw 		DQDLY6
rw 		DQDLY5
rw 		DQDLY4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DQDLY3
rw 		DQDLY2
rw 		DQDLY1
rw 		DQDLY0
rw
Toggle fields

DQDLY0

Bits 0-3: DQDLY0.

DQDLY1

Bits 4-7: DQDLY1.

DQDLY2

Bits 8-11: DQDLY2.

DQDLY3

Bits 12-15: DQDLY3.

DQDLY4

Bits 16-19: DQDLY4.

DQDLY5

Bits 20-23: DQDLY5.

DQDLY6

Bits 24-27: DQDLY6.

DQDLY7

Bits 28-31: DQDLY7.

DX3DQSTR

DDRPHYC byte lane 3 DQST register

Offset: 0x294, size: 32, reset: 0x3DB02000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMDLY
rw 		DQSNDLY
rw 		DQSDLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0DGPS
rw 		R0DGSL
rw
Toggle fields

R0DGSL

Bits 0-2: R0DGSL.

R0DGPS

Bits 12-13: R0DGPS.

DQSDLY

Bits 20-22: DQSDLY.

DQSNDLY

Bits 23-25: DQSNDLY.

DMDLY

Bits 26-29: DMDLY.

DFSDM1

0x4400d000: DFSDM1

134/522 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CH0CFGR1
0x4 CH0CFGR2
0x8 CH0AWSCDR
0xc CH0WDATR
0x10 CH0DATINR
0x14 CH0DLYR
0x20 CH1CFGR1
0x24 CH1CFGR2
0x28 CH1AWSCDR
0x2c CH1WDATR
0x30 CH1DATINR
0x34 CH1DLYR
0x40 CH2CFGR1
0x44 CH2CFGR2
0x48 CH2AWSCDR
0x4c CH2WDATR
0x50 CH2DATINR
0x54 CH2DLYR
0x60 CH3CFGR1
0x64 CH3CFGR2
0x68 CH3AWSCDR
0x6c CH3WDATR
0x70 CH3DATINR
0x74 CH3DLYR
0x80 CH4CFGR1
0x84 CH4CFGR2
0x88 CH4AWSCDR
0x8c CH4WDATR
0x90 CH4DATINR
0x94 CH4DLYR
0xa0 CH5CFGR1
0xa4 CH5CFGR2
0xa8 CH5AWSCDR
0xac CH5WDATR
0xb0 CH5DATINR
0xb4 CH5DLYR
0xc0 CH6CFGR1
0xc4 CH6CFGR2
0xc8 CH6AWSCDR
0xcc CH6WDATR
0xd0 CH6DATINR
0xd4 CH6DLYR
0xe0 CH7CFGR1
0xe4 CH7CFGR2
0xe8 CH7AWSCDR
0xec CH7WDATR
0xf0 CH7DATINR
0xf4 CH7DLYR
0x100 FLT0CR1
0x104 FLT0CR2
0x108 FLT0ISR
0x10c FLT0ICR
0x110 FLT0JCHGR
0x114 FLT0FCR
0x118 FLT0JDATAR
0x11c FLT0RDATAR
0x120 FLT0AWHTR
0x124 FLT0AWLTR
0x128 FLT0AWSR
0x12c FLT0AWCFR
0x130 FLT0EXMAX
0x134 FLT0EXMIN
0x138 FLT0CNVTIMR
0x180 FLT1CR1
0x184 FLT1CR2
0x188 FLT1ISR
0x18c FLT1ICR
0x190 FLT1JCHGR
0x194 FLT1FCR
0x198 FLT1JDATAR
0x19c FLT1RDATAR
0x1a0 FLT1AWHTR
0x1a4 FLT1AWLTR
0x1a8 FLT1AWSR
0x1ac FLT1AWCFR
0x1b0 FLT1EXMAX
0x1b4 FLT1EXMIN
0x1b8 FLT1CNVTIMR
0x200 FLT2CR1
0x204 FLT2CR2
0x208 FLT2ISR
0x20c FLT2ICR
0x210 FLT2JCHGR
0x214 FLT2FCR
0x218 FLT2JDATAR
0x21c FLT2RDATAR
0x220 FLT2AWHTR
0x224 FLT2AWLTR
0x228 FLT2AWSR
0x22c FLT2AWCFR
0x230 FLT2EXMAX
0x234 FLT2EXMIN
0x238 FLT2CNVTIMR
0x280 FLT3CR1
0x284 FLT3CR2
0x288 FLT3ISR
0x28c FLT3ICR
0x290 FLT3JCHGR
0x294 FLT3FCR
0x298 FLT3JDATAR
0x29c FLT3RDATAR
0x2a0 FLT3AWHTR
0x2a4 FLT3AWLTR
0x2a8 FLT3AWSR
0x2ac FLT3AWCFR
0x2b0 FLT3EXMAX
0x2b4 FLT3EXMIN
0x2b8 FLT3CNVTIMR
0x300 FLT4CR1
0x304 FLT4CR2
0x308 FLT4ISR
0x30c FLT4ICR
0x310 FLT4JCHGR
0x314 FLT4FCR
0x318 FLT4JDATAR
0x31c FLT4RDATAR
0x320 FLT4AWHTR
0x324 FLT4AWLTR
0x328 FLT4AWSR
0x32c FLT4AWCFR
0x330 FLT4EXMAX
0x334 FLT4EXMIN
0x338 FLT4CNVTIMR
0x380 FLT5CR1
0x384 FLT5CR2
0x388 FLT5ISR
0x38c FLT5ICR
0x390 FLT5JCHGR
0x394 FLT5FCR
0x398 FLT5JDATAR
0x39c FLT5RDATAR
0x3a0 FLT5AWHTR
0x3a4 FLT5AWLTR
0x3a8 FLT5AWSR
0x3ac FLT5AWCFR
0x3b0 FLT5EXMAX
0x3b4 FLT5EXMIN
0x3b8 FLT5CNVTIMR
0x7f0 HWCFGR
0x7f4 VERR
0x7f8 IPIDR
0x7fc SIDR
Toggle registers

CH0CFGR1

This register specifies the parameters used by channel y.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH0CFGR2

This register specifies the parameters used by channel y.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH0AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH0WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH0DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH0DLYR

DFSDM channel 0 delay register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH1CFGR1

This register specifies the parameters used by channel y.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH1CFGR2

This register specifies the parameters used by channel y.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH1AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH1WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH1DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH1DLYR

DFSDM channel 1 delay register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH2CFGR1

This register specifies the parameters used by channel y.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH2CFGR2

This register specifies the parameters used by channel y.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH2AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH2WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH2DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH2DLYR

DFSDM channel 2 delay register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH3CFGR1

This register specifies the parameters used by channel y.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH3CFGR2

This register specifies the parameters used by channel y.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH3AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH3WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH3DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH3DLYR

DFSDM channel 3 delay register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH4CFGR1

This register specifies the parameters used by channel y.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH4CFGR2

This register specifies the parameters used by channel y.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH4AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH4WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH4DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH4DLYR

DFSDM channel 4 delay register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH5CFGR1

This register specifies the parameters used by channel y.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH5CFGR2

This register specifies the parameters used by channel y.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH5AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH5WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH5DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH5DLYR

DFSDM channel 5 delay register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH6CFGR1

This register specifies the parameters used by channel y.

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH6CFGR2

This register specifies the parameters used by channel y.

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH6AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH6WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH6DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH6DLYR

DFSDM channel 6 delay register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

CH7CFGR1

This register specifies the parameters used by channel y.

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDMEN
rw 		CKOUTSRC
rw 		CKOUTDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATPACK
rw 		DATMPX
rw 		CHINSEL
rw 		CHEN
rw 		CKABEN
rw 		SCDEN
rw 		SPICKSEL
rw 		SITP
rw
Toggle fields

SITP

Bits 0-1: SITP.

SPICKSEL

Bits 2-3: SPICKSEL.

SCDEN

Bit 5: SCDEN.

CKABEN

Bit 6: CKABEN.

CHEN

Bit 7: CHEN.

CHINSEL

Bit 8: CHINSEL.

DATMPX

Bits 12-13: DATMPX.

DATPACK

Bits 14-15: DATPACK.

CKOUTDIV

Bits 16-23: CKOUTDIV.

CKOUTSRC

Bit 30: CKOUTSRC.

DFSDMEN

Bit 31: DFSDMEN.

CH7CFGR2

This register specifies the parameters used by channel y.

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET
rw 		DTRBS
rw
Toggle fields

DTRBS

Bits 3-7: DTRBS.

OFFSET

Bits 8-31: OFFSET.

CH7AWSCDR

Short-circuit detector and analog watchdog settings for channel y.

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFORD
rw 		AWFOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKSCD
rw 		SCDT
rw
Toggle fields

SCDT

Bits 0-7: SCDT.

BKSCD

Bits 12-15: BKSCD.

AWFOSR

Bits 16-20: AWFOSR.

AWFORD

Bits 22-23: AWFORD.

CH7WDATR

This register contains the data resulting from the analog watchdog filter associated to the input channel y.

Offset: 0xec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA
r
Toggle fields

WDATA

Bits 0-15: WDATA.

CH7DATINR

This register contains 16-bit input data to be processed by DFSDM filter module.

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INDAT1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INDAT0
rw
Toggle fields

INDAT0

Bits 0-15: INDAT0.

INDAT1

Bits 16-31: INDAT1.

CH7DLYR

DFSDM channel 7 delay register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLSSKP
rw
Toggle fields

PLSSKP

Bits 0-5: PLSSKP.

FLT0CR1

DFSDM filter 0 control register 1

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFEN.

JSWSTART

Bit 1: JSWSTART.

JSYNC

Bit 3: JSYNC.

JSCAN

Bit 4: JSCAN.

JDMAEN

Bit 5: JDMAEN.

JEXTSEL

Bits 8-12: JEXTSEL.

JEXTEN

Bits 13-14: JEXTEN.

RSWSTART

Bit 17: RSWSTART.

RCONT

Bit 18: RCONT.

RSYNC

Bit 19: RSYNC.

RDMAEN

Bit 21: RDMAEN.

RCH

Bits 24-26: RCH.

FAST

Bit 29: FAST.

AWFSEL

Bit 30: AWFSEL.

FLT0CR2

DFSDM filter 0 control register 2

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: JEOCIE.

REOCIE

Bit 1: REOCIE.

JOVRIE

Bit 2: JOVRIE.

ROVRIE

Bit 3: ROVRIE.

AWDIE

Bit 4: AWDIE.

SCDIE

Bit 5: SCDIE.

CKABIE

Bit 6: CKABIE.

EXCH

Bits 8-15: EXCH.

AWDCH

Bits 16-23: AWDCH.

FLT0ISR

DFSDM filter 0 interrupt and status register

Offset: 0x108, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: JEOCF.

REOCF

Bit 1: REOCF.

JOVRF

Bit 2: JOVRF.

ROVRF

Bit 3: ROVRF.

AWDF

Bit 4: AWDF.

JCIP

Bit 13: JCIP.

RCIP

Bit 14: RCIP.

CKABF

Bits 16-23: CKABF.

SCDF

Bits 24-31: SCDF.

FLT0ICR

DFSDM filter 0 interrupt flag clear register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: CLRJOVRF.

CLRROVRF

Bit 3: CLRROVRF.

CLRCKABF

Bits 16-23: CLRCKABF.

CLRSCDF

Bits 24-31: CLRSCDF.

FLT0JCHGR

DFSDM filter 0 injected channel group selection register

Offset: 0x110, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: JCHG.

FLT0FCR

DFSDM filter 0 control register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: IOSR.

FOSR

Bits 16-25: FOSR.

FORD

Bits 29-31: FORD.

FLT0JDATAR

DFSDM filter 0 data register for injected group

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: JDATACH.

JDATA

Bits 8-31: JDATA.

FLT0RDATAR

DFSDM filter 0 data register for the regular channel

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: RDATACH.

RPEND

Bit 4: RPEND.

RDATA

Bits 8-31: RDATA.

FLT0AWHTR

DFSDM filter 0 analog watchdog high threshold register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: BKAWH.

AWHT

Bits 8-31: AWHT.

FLT0AWLTR

DFSDM filter 0 analog watchdog low threshold register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: BKAWL.

AWLT

Bits 8-31: AWLT.

FLT0AWSR

DFSDM filter 0 analog watchdog status register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: AWLTF.

AWHTF

Bits 8-15: AWHTF.

FLT0AWCFR

DFSDM filter 0 analog watchdog clear flag register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: CLRAWLTF.

CLRAWHTF

Bits 8-15: CLRAWHTF.

FLT0EXMAX

DFSDM filter 0 extremes detector maximum register

Offset: 0x130, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: EXMAXCH.

EXMAX

Bits 8-31: EXMAX.

FLT0EXMIN

DFSDM filter 0 extremes detector minimum register

Offset: 0x134, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rw 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: EXMINCH.

EXMIN

Bits 8-31: EXMIN.

FLT0CNVTIMR

DFSDM filter 0 conversion timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: CNVCNT.

FLT1CR1

DFSDM filter 1 control register 1

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFEN.

JSWSTART

Bit 1: JSWSTART.

JSYNC

Bit 3: JSYNC.

JSCAN

Bit 4: JSCAN.

JDMAEN

Bit 5: JDMAEN.

JEXTSEL

Bits 8-12: JEXTSEL.

JEXTEN

Bits 13-14: JEXTEN.

RSWSTART

Bit 17: RSWSTART.

RCONT

Bit 18: RCONT.

RSYNC

Bit 19: RSYNC.

RDMAEN

Bit 21: RDMAEN.

RCH

Bits 24-26: RCH.

FAST

Bit 29: FAST.

AWFSEL

Bit 30: AWFSEL.

FLT1CR2

DFSDM filter 1 control register 2

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: JEOCIE.

REOCIE

Bit 1: REOCIE.

JOVRIE

Bit 2: JOVRIE.

ROVRIE

Bit 3: ROVRIE.

AWDIE

Bit 4: AWDIE.

SCDIE

Bit 5: SCDIE.

CKABIE

Bit 6: CKABIE.

EXCH

Bits 8-15: EXCH.

AWDCH

Bits 16-23: AWDCH.

FLT1ISR

DFSDM filter 1 interrupt and status register

Offset: 0x188, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: JEOCF.

REOCF

Bit 1: REOCF.

JOVRF

Bit 2: JOVRF.

ROVRF

Bit 3: ROVRF.

AWDF

Bit 4: AWDF.

JCIP

Bit 13: JCIP.

RCIP

Bit 14: RCIP.

CKABF

Bits 16-23: CKABF.

SCDF

Bits 24-31: SCDF.

FLT1ICR

DFSDM filter 1 interrupt flag clear register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: CLRJOVRF.

CLRROVRF

Bit 3: CLRROVRF.

CLRCKABF

Bits 16-23: CLRCKABF.

CLRSCDF

Bits 24-31: CLRSCDF.

FLT1JCHGR

DFSDM filter 1 injected channel group selection register

Offset: 0x190, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: JCHG.

FLT1FCR

DFSDM filter 1 control register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: IOSR.

FOSR

Bits 16-25: FOSR.

FORD

Bits 29-31: FORD.

FLT1JDATAR

DFSDM filter 1 data register for injected group

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: JDATACH.

JDATA

Bits 8-31: JDATA.

FLT1RDATAR

DFSDM filter 1 data register for the regular channel

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: RDATACH.

RPEND

Bit 4: RPEND.

RDATA

Bits 8-31: RDATA.

FLT1AWHTR

DFSDM filter 1 analog watchdog high threshold register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: BKAWH.

AWHT

Bits 8-31: AWHT.

FLT1AWLTR

DFSDM filter 1 analog watchdog low threshold register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: BKAWL.

AWLT

Bits 8-31: AWLT.

FLT1AWSR

DFSDM filter 1 analog watchdog status register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: AWLTF.

AWHTF

Bits 8-15: AWHTF.

FLT1AWCFR

DFSDM filter 1 analog watchdog clear flag register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: CLRAWLTF.

CLRAWHTF

Bits 8-15: CLRAWHTF.

FLT1EXMAX

DFSDM filter 1 extremes detector maximum register

Offset: 0x1b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: EXMAXCH.

EXMAX

Bits 8-31: EXMAX.

FLT1EXMIN

DFSDM filter 1 extremes detector minimum register

Offset: 0x1b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rw 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: EXMINCH.

EXMIN

Bits 8-31: EXMIN.

FLT1CNVTIMR

DFSDM filter 1 conversion timer register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: CNVCNT.

FLT2CR1

DFSDM filter 2 control register 1

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFEN.

JSWSTART

Bit 1: JSWSTART.

JSYNC

Bit 3: JSYNC.

JSCAN

Bit 4: JSCAN.

JDMAEN

Bit 5: JDMAEN.

JEXTSEL

Bits 8-12: JEXTSEL.

JEXTEN

Bits 13-14: JEXTEN.

RSWSTART

Bit 17: RSWSTART.

RCONT

Bit 18: RCONT.

RSYNC

Bit 19: RSYNC.

RDMAEN

Bit 21: RDMAEN.

RCH

Bits 24-26: RCH.

FAST

Bit 29: FAST.

AWFSEL

Bit 30: AWFSEL.

FLT2CR2

DFSDM filter 2 control register 2

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: JEOCIE.

REOCIE

Bit 1: REOCIE.

JOVRIE

Bit 2: JOVRIE.

ROVRIE

Bit 3: ROVRIE.

AWDIE

Bit 4: AWDIE.

SCDIE

Bit 5: SCDIE.

CKABIE

Bit 6: CKABIE.

EXCH

Bits 8-15: EXCH.

AWDCH

Bits 16-23: AWDCH.

FLT2ISR

DFSDM filter 2 interrupt and status register

Offset: 0x208, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: JEOCF.

REOCF

Bit 1: REOCF.

JOVRF

Bit 2: JOVRF.

ROVRF

Bit 3: ROVRF.

AWDF

Bit 4: AWDF.

JCIP

Bit 13: JCIP.

RCIP

Bit 14: RCIP.

CKABF

Bits 16-23: CKABF.

SCDF

Bits 24-31: SCDF.

FLT2ICR

DFSDM filter 2 interrupt flag clear register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: CLRJOVRF.

CLRROVRF

Bit 3: CLRROVRF.

CLRCKABF

Bits 16-23: CLRCKABF.

CLRSCDF

Bits 24-31: CLRSCDF.

FLT2JCHGR

DFSDM filter 2 injected channel group selection register

Offset: 0x210, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: JCHG.

FLT2FCR

DFSDM filter 2 control register

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: IOSR.

FOSR

Bits 16-25: FOSR.

FORD

Bits 29-31: FORD.

FLT2JDATAR

DFSDM filter 2 data register for injected group

Offset: 0x218, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: JDATACH.

JDATA

Bits 8-31: JDATA.

FLT2RDATAR

DFSDM filter 2 data register for the regular channel

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: RDATACH.

RPEND

Bit 4: RPEND.

RDATA

Bits 8-31: RDATA.

FLT2AWHTR

DFSDM filter 2 analog watchdog high threshold register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: BKAWH.

AWHT

Bits 8-31: AWHT.

FLT2AWLTR

DFSDM filter 2 analog watchdog low threshold register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: BKAWL.

AWLT

Bits 8-31: AWLT.

FLT2AWSR

DFSDM filter 2 analog watchdog status register

Offset: 0x228, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: AWLTF.

AWHTF

Bits 8-15: AWHTF.

FLT2AWCFR

DFSDM filter 2 analog watchdog clear flag register

Offset: 0x22c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: CLRAWLTF.

CLRAWHTF

Bits 8-15: CLRAWHTF.

FLT2EXMAX

DFSDM filter 2 extremes detector maximum register

Offset: 0x230, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: EXMAXCH.

EXMAX

Bits 8-31: EXMAX.

FLT2EXMIN

DFSDM filter 2 extremes detector minimum register

Offset: 0x234, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rw 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: EXMINCH.

EXMIN

Bits 8-31: EXMIN.

FLT2CNVTIMR

DFSDM filter 2 conversion timer register

Offset: 0x238, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: CNVCNT.

FLT3CR1

DFSDM filter 3 control register 1

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFEN.

JSWSTART

Bit 1: JSWSTART.

JSYNC

Bit 3: JSYNC.

JSCAN

Bit 4: JSCAN.

JDMAEN

Bit 5: JDMAEN.

JEXTSEL

Bits 8-12: JEXTSEL.

JEXTEN

Bits 13-14: JEXTEN.

RSWSTART

Bit 17: RSWSTART.

RCONT

Bit 18: RCONT.

RSYNC

Bit 19: RSYNC.

RDMAEN

Bit 21: RDMAEN.

RCH

Bits 24-26: RCH.

FAST

Bit 29: FAST.

AWFSEL

Bit 30: AWFSEL.

FLT3CR2

DFSDM filter 3 control register 2

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: JEOCIE.

REOCIE

Bit 1: REOCIE.

JOVRIE

Bit 2: JOVRIE.

ROVRIE

Bit 3: ROVRIE.

AWDIE

Bit 4: AWDIE.

SCDIE

Bit 5: SCDIE.

CKABIE

Bit 6: CKABIE.

EXCH

Bits 8-15: EXCH.

AWDCH

Bits 16-23: AWDCH.

FLT3ISR

DFSDM filter 3 interrupt and status register

Offset: 0x288, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: JEOCF.

REOCF

Bit 1: REOCF.

JOVRF

Bit 2: JOVRF.

ROVRF

Bit 3: ROVRF.

AWDF

Bit 4: AWDF.

JCIP

Bit 13: JCIP.

RCIP

Bit 14: RCIP.

CKABF

Bits 16-23: CKABF.

SCDF

Bits 24-31: SCDF.

FLT3ICR

DFSDM filter 3 interrupt flag clear register

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: CLRJOVRF.

CLRROVRF

Bit 3: CLRROVRF.

CLRCKABF

Bits 16-23: CLRCKABF.

CLRSCDF

Bits 24-31: CLRSCDF.

FLT3JCHGR

DFSDM filter 3 injected channel group selection register

Offset: 0x290, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: JCHG.

FLT3FCR

DFSDM filter 3 control register

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: IOSR.

FOSR

Bits 16-25: FOSR.

FORD

Bits 29-31: FORD.

FLT3JDATAR

DFSDM filter 3 data register for injected group

Offset: 0x298, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: JDATACH.

JDATA

Bits 8-31: JDATA.

FLT3RDATAR

DFSDM filter 3 data register for the regular channel

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: RDATACH.

RPEND

Bit 4: RPEND.

RDATA

Bits 8-31: RDATA.

FLT3AWHTR

DFSDM filter 3 analog watchdog high threshold register

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: BKAWH.

AWHT

Bits 8-31: AWHT.

FLT3AWLTR

DFSDM filter 3 analog watchdog low threshold register

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: BKAWL.

AWLT

Bits 8-31: AWLT.

FLT3AWSR

DFSDM filter 3 analog watchdog status register

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: AWLTF.

AWHTF

Bits 8-15: AWHTF.

FLT3AWCFR

DFSDM filter 3 analog watchdog clear flag register

Offset: 0x2ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: CLRAWLTF.

CLRAWHTF

Bits 8-15: CLRAWHTF.

FLT3EXMAX

DFSDM filter 3 extremes detector maximum register

Offset: 0x2b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: EXMAXCH.

EXMAX

Bits 8-31: EXMAX.

FLT3EXMIN

DFSDM filter 3 extremes detector minimum register

Offset: 0x2b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rw 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: EXMINCH.

EXMIN

Bits 8-31: EXMIN.

FLT3CNVTIMR

DFSDM filter 3 conversion timer register

Offset: 0x2b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: CNVCNT.

FLT4CR1

DFSDM filter 4 control register 1

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFEN.

JSWSTART

Bit 1: JSWSTART.

JSYNC

Bit 3: JSYNC.

JSCAN

Bit 4: JSCAN.

JDMAEN

Bit 5: JDMAEN.

JEXTSEL

Bits 8-12: JEXTSEL.

JEXTEN

Bits 13-14: JEXTEN.

RSWSTART

Bit 17: RSWSTART.

RCONT

Bit 18: RCONT.

RSYNC

Bit 19: RSYNC.

RDMAEN

Bit 21: RDMAEN.

RCH

Bits 24-26: RCH.

FAST

Bit 29: FAST.

AWFSEL

Bit 30: AWFSEL.

FLT4CR2

DFSDM filter 4 control register 2

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: JEOCIE.

REOCIE

Bit 1: REOCIE.

JOVRIE

Bit 2: JOVRIE.

ROVRIE

Bit 3: ROVRIE.

AWDIE

Bit 4: AWDIE.

SCDIE

Bit 5: SCDIE.

CKABIE

Bit 6: CKABIE.

EXCH

Bits 8-15: EXCH.

AWDCH

Bits 16-23: AWDCH.

FLT4ISR

DFSDM filter 4 interrupt and status register

Offset: 0x308, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: JEOCF.

REOCF

Bit 1: REOCF.

JOVRF

Bit 2: JOVRF.

ROVRF

Bit 3: ROVRF.

AWDF

Bit 4: AWDF.

JCIP

Bit 13: JCIP.

RCIP

Bit 14: RCIP.

CKABF

Bits 16-23: CKABF.

SCDF

Bits 24-31: SCDF.

FLT4ICR

DFSDM filter 4 interrupt flag clear register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: CLRJOVRF.

CLRROVRF

Bit 3: CLRROVRF.

CLRCKABF

Bits 16-23: CLRCKABF.

CLRSCDF

Bits 24-31: CLRSCDF.

FLT4JCHGR

DFSDM filter 4 injected channel group selection register

Offset: 0x310, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: JCHG.

FLT4FCR

DFSDM filter 4 control register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: IOSR.

FOSR

Bits 16-25: FOSR.

FORD

Bits 29-31: FORD.

FLT4JDATAR

DFSDM filter 4 data register for injected group

Offset: 0x318, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: JDATACH.

JDATA

Bits 8-31: JDATA.

FLT4RDATAR

DFSDM filter 4 data register for the regular channel

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: RDATACH.

RPEND

Bit 4: RPEND.

RDATA

Bits 8-31: RDATA.

FLT4AWHTR

DFSDM filter 4 analog watchdog high threshold register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: BKAWH.

AWHT

Bits 8-31: AWHT.

FLT4AWLTR

DFSDM filter 4 analog watchdog low threshold register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: BKAWL.

AWLT

Bits 8-31: AWLT.

FLT4AWSR

DFSDM filter 4 analog watchdog status register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: AWLTF.

AWHTF

Bits 8-15: AWHTF.

FLT4AWCFR

DFSDM filter 4 analog watchdog clear flag register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: CLRAWLTF.

CLRAWHTF

Bits 8-15: CLRAWHTF.

FLT4EXMAX

DFSDM filter 4 extremes detector maximum register

Offset: 0x330, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: EXMAXCH.

EXMAX

Bits 8-31: EXMAX.

FLT4EXMIN

DFSDM filter 4 extremes detector minimum register

Offset: 0x334, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rw 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: EXMINCH.

EXMIN

Bits 8-31: EXMIN.

FLT4CNVTIMR

DFSDM filter 4 conversion timer register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: CNVCNT.

FLT5CR1

DFSDM filter 5 control register 1

Offset: 0x380, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWFSEL
rw 		FAST
rw 		RCH
rw 		RDMAEN
rw 		RSYNC
rw 		RCONT
rw 		RSWSTART
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JEXTEN
rw 		JEXTSEL
rw 		JDMAEN
rw 		JSCAN
rw 		JSYNC
rw 		JSWSTART
rw 		DFEN
rw
Toggle fields

DFEN

Bit 0: DFEN.

JSWSTART

Bit 1: JSWSTART.

JSYNC

Bit 3: JSYNC.

JSCAN

Bit 4: JSCAN.

JDMAEN

Bit 5: JDMAEN.

JEXTSEL

Bits 8-12: JEXTSEL.

JEXTEN

Bits 13-14: JEXTEN.

RSWSTART

Bit 17: RSWSTART.

RCONT

Bit 18: RCONT.

RSYNC

Bit 19: RSYNC.

RDMAEN

Bit 21: RDMAEN.

RCH

Bits 24-26: RCH.

FAST

Bit 29: FAST.

AWFSEL

Bit 30: AWFSEL.

FLT5CR2

DFSDM filter 5 control register 2

Offset: 0x384, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWDCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXCH
rw 		CKABIE
rw 		SCDIE
rw 		AWDIE
rw 		ROVRIE
rw 		JOVRIE
rw 		REOCIE
rw 		JEOCIE
rw
Toggle fields

JEOCIE

Bit 0: JEOCIE.

REOCIE

Bit 1: REOCIE.

JOVRIE

Bit 2: JOVRIE.

ROVRIE

Bit 3: ROVRIE.

AWDIE

Bit 4: AWDIE.

SCDIE

Bit 5: SCDIE.

CKABIE

Bit 6: CKABIE.

EXCH

Bits 8-15: EXCH.

AWDCH

Bits 16-23: AWDCH.

FLT5ISR

DFSDM filter 5 interrupt and status register

Offset: 0x388, size: 32, reset: 0x00FF0000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCDF
r 		CKABF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCIP
r 		JCIP
r 		AWDF
r 		ROVRF
r 		JOVRF
r 		REOCF
r 		JEOCF
r
Toggle fields

JEOCF

Bit 0: JEOCF.

REOCF

Bit 1: REOCF.

JOVRF

Bit 2: JOVRF.

ROVRF

Bit 3: ROVRF.

AWDF

Bit 4: AWDF.

JCIP

Bit 13: JCIP.

RCIP

Bit 14: RCIP.

CKABF

Bits 16-23: CKABF.

SCDF

Bits 24-31: SCDF.

FLT5ICR

DFSDM filter 5 interrupt flag clear register

Offset: 0x38c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRSCDF
rw 		CLRCKABF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRROVRF
rw 		CLRJOVRF
rw
Toggle fields

CLRJOVRF

Bit 2: CLRJOVRF.

CLRROVRF

Bit 3: CLRROVRF.

CLRCKABF

Bits 16-23: CLRCKABF.

CLRSCDF

Bits 24-31: CLRSCDF.

FLT5JCHGR

DFSDM filter 5 injected channel group selection register

Offset: 0x390, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JCHG
rw
Toggle fields

JCHG

Bits 0-7: JCHG.

FLT5FCR

DFSDM filter 5 control register

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD
rw 		FOSR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSR
rw
Toggle fields

IOSR

Bits 0-7: IOSR.

FOSR

Bits 16-25: FOSR.

FORD

Bits 29-31: FORD.

FLT5JDATAR

DFSDM filter 5 data register for injected group

Offset: 0x398, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA
r 		JDATACH
r
Toggle fields

JDATACH

Bits 0-2: JDATACH.

JDATA

Bits 8-31: JDATA.

FLT5RDATAR

DFSDM filter 5 data register for the regular channel

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
r 		RPEND
r 		RDATACH
r
Toggle fields

RDATACH

Bits 0-2: RDATACH.

RPEND

Bit 4: RPEND.

RDATA

Bits 8-31: RDATA.

FLT5AWHTR

DFSDM filter 5 analog watchdog high threshold register

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWHT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHT
rw 		BKAWH
rw
Toggle fields

BKAWH

Bits 0-3: BKAWH.

AWHT

Bits 8-31: AWHT.

FLT5AWLTR

DFSDM filter 5 analog watchdog low threshold register

Offset: 0x3a4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWLT
rw 		BKAWL
rw
Toggle fields

BKAWL

Bits 0-3: BKAWL.

AWLT

Bits 8-31: AWLT.

FLT5AWSR

DFSDM filter 5 analog watchdog status register

Offset: 0x3a8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AWHTF
r 		AWLTF
r
Toggle fields

AWLTF

Bits 0-7: AWLTF.

AWHTF

Bits 8-15: AWHTF.

FLT5AWCFR

DFSDM filter 5 analog watchdog clear flag register

Offset: 0x3ac, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRAWHTF
rw 		CLRAWLTF
rw
Toggle fields

CLRAWLTF

Bits 0-7: CLRAWLTF.

CLRAWHTF

Bits 8-15: CLRAWHTF.

FLT5EXMAX

DFSDM filter 5 extremes detector maximum register

Offset: 0x3b0, size: 32, reset: 0x80000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMAX
r 		EXMAXCH
r
Toggle fields

EXMAXCH

Bits 0-2: EXMAXCH.

EXMAX

Bits 8-31: EXMAX.

FLT5EXMIN

DFSDM filter 5 extremes detector minimum register

Offset: 0x3b4, size: 32, reset: 0x7FFFFF00, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXMIN
rw 		EXMINCH
r
Toggle fields

EXMINCH

Bits 0-2: EXMINCH.

EXMIN

Bits 8-31: EXMIN.

FLT5CNVTIMR

DFSDM filter 5 conversion timer register

Offset: 0x3b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNVCNT
r
Toggle fields

CNVCNT

Bits 4-31: CNVCNT.

HWCFGR

This register specifies the hardware configuration of DFSDM peripheral.

Offset: 0x7f0, size: 32, reset: 0x00000608, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBF
r 		NBT
r
Toggle fields

NBT

Bits 0-7: NBT.

NBF

Bits 8-15: NBF.

VERR

This register specifies the version of DFSDM peripheral.

Offset: 0x7f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

This register specifies the identification of DFSDM peripheral.

Offset: 0x7f8, size: 32, reset: 0x00110031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

This register specifies the size allocated to DFSDM registers.

Offset: 0x7fc, size: 32, reset: 0xA3C5DD02, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DLYBQS

0x58004000: DLYBQS

6/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw 		DEN
rw
Toggle fields

DEN

Bit 0: DEN.

SEN

Bit 1: SEN.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
r 		LNG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw 		SEL
rw
Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

VERR

DLYB IP version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

DLYB IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140051, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DLYB size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DLYBSD1

0x58006000: DLYBSD1

6/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw 		DEN
rw
Toggle fields

DEN

Bit 0: DEN.

SEN

Bit 1: SEN.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
r 		LNG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw 		SEL
rw
Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

VERR

DLYB IP version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

DLYB IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140051, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DLYB size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DLYBSD2

0x58008000: DLYBSD1

6/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw 		DEN
rw
Toggle fields

DEN

Bit 0: DEN.

SEN

Bit 1: SEN.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
r 		LNG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw 		SEL
rw
Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

VERR

DLYB IP version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

DLYB IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140051, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DLYB size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DLYBSD3

0x48005000: DLYBSD1

6/10 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

DLYB control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEN
rw 		DEN
rw
Toggle fields

DEN

Bit 0: DEN.

SEN

Bit 1: SEN.

CFGR

DLYB configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

2/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LNGF
r 		LNG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UNIT
rw 		SEL
rw
Toggle fields

SEL

Bits 0-3: SEL.

UNIT

Bits 8-14: UNIT.

LNG

Bits 16-27: LNG.

LNGF

Bit 31: LNGF.

VERR

DLYB IP version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

DLYB IP identification register

Offset: 0x3f8, size: 32, reset: 0x00140051, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DLYB size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DMA1

0x48000000: DMA1

63/303 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 LISR
0x4 HISR
0x8 LIFCR
0xc HIFCR
0x10 S0CR
0x14 S0NDTR
0x18 S0PAR
0x1c S0M0AR
0x20 S0M1AR
0x24 S0FCR
0x28 S1CR
0x2c S1NDTR
0x30 S1PAR
0x34 S1M0AR
0x38 S1M1AR
0x3c S1FCR
0x40 S2CR
0x44 S2NDTR
0x48 S2PAR
0x4c S2M0AR
0x50 S2M1AR
0x54 S2FCR
0x58 S3CR
0x5c S3NDTR
0x60 S3PAR
0x64 S3M0AR
0x68 S3M1AR
0x6c S3FCR
0x70 S4CR
0x74 S4NDTR
0x78 S4PAR
0x7c S4M0AR
0x80 S4M1AR
0x84 S4FCR
0x88 S5CR
0x8c S5NDTR
0x90 S5PAR
0x94 S5M0AR
0x98 S5M1AR
0x9c S5FCR
0xa0 S6CR
0xa4 S6NDTR
0xa8 S6PAR
0xac S6M0AR
0xb0 S6M1AR
0xb4 S6FCR
0xb8 S7CR
0xbc S7NDTR
0xc0 S7PAR
0xc4 S7M0AR
0xc8 S7M1AR
0xcc S7FCR
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPDR
0x3fc SIDR
Toggle registers

LISR

DMA low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r 		HTIF3
r 		TEIF3
r 		DMEIF3
r 		FEIF3
r 		TCIF2
r 		HTIF2
r 		TEIF2
r 		DMEIF2
r 		FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r 		HTIF1
r 		TEIF1
r 		DMEIF1
r 		FEIF1
r 		TCIF0
r 		HTIF0
r 		TEIF0
r 		DMEIF0
r 		FEIF0
r
Toggle fields

FEIF0

Bit 0: FEIF0.

DMEIF0

Bit 2: DMEIF0.

TEIF0

Bit 3: TEIF0.

HTIF0

Bit 4: HTIF0.

TCIF0

Bit 5: TCIF0.

FEIF1

Bit 6: FEIF1.

DMEIF1

Bit 8: DMEIF1.

TEIF1

Bit 9: TEIF1.

HTIF1

Bit 10: HTIF1.

TCIF1

Bit 11: TCIF1.

FEIF2

Bit 16: FEIF2.

DMEIF2

Bit 18: DMEIF2.

TEIF2

Bit 19: TEIF2.

HTIF2

Bit 20: HTIF2.

TCIF2

Bit 21: TCIF2.

FEIF3

Bit 22: FEIF3.

DMEIF3

Bit 24: DMEIF3.

TEIF3

Bit 25: TEIF3.

HTIF3

Bit 26: HTIF3.

TCIF3

Bit 27: TCIF3.

HISR

DMA high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r 		HTIF7
r 		TEIF7
r 		DMEIF7
r 		FEIF7
r 		TCIF6
r 		HTIF6
r 		TEIF6
r 		DMEIF6
r 		FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r 		HTIF5
r 		TEIF5
r 		DMEIF5
r 		FEIF5
r 		TCIF4
r 		HTIF4
r 		TEIF4
r 		DMEIF4
r 		FEIF4
r
Toggle fields

FEIF4

Bit 0: FEIF4.

DMEIF4

Bit 2: DMEIF4.

TEIF4

Bit 3: TEIF4.

HTIF4

Bit 4: HTIF4.

TCIF4

Bit 5: TCIF4.

FEIF5

Bit 6: FEIF5.

DMEIF5

Bit 8: DMEIF5.

TEIF5

Bit 9: TEIF5.

HTIF5

Bit 10: HTIF5.

TCIF5

Bit 11: TCIF5.

FEIF6

Bit 16: FEIF6.

DMEIF6

Bit 18: DMEIF6.

TEIF6

Bit 19: TEIF6.

HTIF6

Bit 20: HTIF6.

TCIF6

Bit 21: TCIF6.

FEIF7

Bit 22: FEIF7.

DMEIF7

Bit 24: DMEIF7.

TEIF7

Bit 25: TEIF7.

HTIF7

Bit 26: HTIF7.

TCIF7

Bit 27: TCIF7.

LIFCR

DMA low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF3
w 		CHTIF3
w 		CTEIF3
w 		CDMEIF3
w 		CFEIF3
w 		CTCIF2
w 		CHTIF2
w 		CTEIF2
w 		CDMEIF2
w 		CFEIF2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF1
w 		CHTIF1
w 		CTEIF1
w 		CDMEIF1
w 		CFEIF1
w 		CTCIF0
w 		CHTIF0
w 		CTEIF0
w 		CDMEIF0
w 		CFEIF0
w
Toggle fields

CFEIF0

Bit 0: CFEIF0.

CDMEIF0

Bit 2: CDMEIF0.

CTEIF0

Bit 3: CTEIF0.

CHTIF0

Bit 4: CHTIF0.

CTCIF0

Bit 5: CTCIF0.

CFEIF1

Bit 6: CFEIF1.

CDMEIF1

Bit 8: CDMEIF1.

CTEIF1

Bit 9: CTEIF1.

CHTIF1

Bit 10: CHTIF1.

CTCIF1

Bit 11: CTCIF1.

CFEIF2

Bit 16: CFEIF2.

CDMEIF2

Bit 18: CDMEIF2.

CTEIF2

Bit 19: CTEIF2.

CHTIF2

Bit 20: CHTIF2.

CTCIF2

Bit 21: CTCIF2.

CFEIF3

Bit 22: CFEIF3.

CDMEIF3

Bit 24: CDMEIF3.

CTEIF3

Bit 25: CTEIF3.

CHTIF3

Bit 26: CHTIF3.

CTCIF3

Bit 27: CTCIF3.

HIFCR

DMA high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7
w 		CHTIF7
w 		CTEIF7
w 		CDMEIF7
w 		CFEIF7
w 		CTCIF6
w 		CHTIF6
w 		CTEIF6
w 		CDMEIF6
w 		CFEIF6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF5
w 		CHTIF5
w 		CTEIF5
w 		CDMEIF5
w 		CFEIF5
w 		CTCIF4
w 		CHTIF4
w 		CTEIF4
w 		CDMEIF4
w 		CFEIF4
w
Toggle fields

CFEIF4

Bit 0: CFEIF4.

CDMEIF4

Bit 2: CDMEIF4.

CTEIF4

Bit 3: CTEIF4.

CHTIF4

Bit 4: CHTIF4.

CTCIF4

Bit 5: CTCIF4.

CFEIF5

Bit 6: CFEIF5.

CDMEIF5

Bit 8: CDMEIF5.

CTEIF5

Bit 9: CTEIF5.

CHTIF5

Bit 10: CHTIF5.

CTCIF5

Bit 11: CTCIF5.

CFEIF6

Bit 16: CFEIF6.

CDMEIF6

Bit 18: CDMEIF6.

CTEIF6

Bit 19: CTEIF6.

CHTIF6

Bit 20: CHTIF6.

CTCIF6

Bit 21: CTCIF6.

CFEIF7

Bit 22: CFEIF7.

CDMEIF7

Bit 24: CDMEIF7.

CTEIF7

Bit 25: CTEIF7.

CHTIF7

Bit 26: CHTIF7.

CTCIF7

Bit 27: CTCIF7.

S0CR

This register is used to configure the concerned stream.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S0NDTR

DMA stream 0 number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S0PAR

DMA stream 0 peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S0M0AR

DMA stream 0 memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S0M1AR

DMA stream 0 memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S0FCR

DMA stream 0 FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S1CR

This register is used to configure the concerned stream.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S1NDTR

DMA stream 1 number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S1PAR

DMA stream 1 peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S1M0AR

DMA stream 1 memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S1M1AR

DMA stream 1 memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S1FCR

DMA stream 1 FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S2CR

This register is used to configure the concerned stream.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S2NDTR

DMA stream 2 number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S2PAR

DMA stream 2 peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S2M0AR

DMA stream 2 memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S2M1AR

DMA stream 2 memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S2FCR

DMA stream 2 FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S3CR

This register is used to configure the concerned stream.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S3NDTR

DMA stream 3 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S3PAR

DMA stream 3 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S3M0AR

DMA stream 3 memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S3M1AR

DMA stream 3 memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S3FCR

DMA stream 3 FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S4CR

This register is used to configure the concerned stream.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S4NDTR

DMA stream 4 number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S4PAR

DMA stream 4 peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S4M0AR

DMA stream 4 memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S4M1AR

DMA stream 4 memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S4FCR

DMA stream 4 FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S5CR

This register is used to configure the concerned stream.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S5NDTR

DMA stream 5 number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S5PAR

DMA stream 5 peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S5M0AR

DMA stream 5 memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S5M1AR

DMA stream 5 memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S5FCR

DMA stream 5 FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S6CR

This register is used to configure the concerned stream.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S6NDTR

DMA stream 6 number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S6PAR

DMA stream 6 peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S6M0AR

DMA stream 6 memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S6M1AR

DMA stream 6 memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S6FCR

DMA stream 6 FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S7CR

This register is used to configure the concerned stream.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S7NDTR

DMA stream 7 number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S7PAR

DMA stream 7 peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S7M0AR

DMA stream 7 memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S7M1AR

DMA stream 7 memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S7FCR

DMA stream 7 FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

HWCFGR2

DMA hardware configuration 2register

Offset: 0x3ec, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHSEL_WIDTH
r 		WRITE_BUFFERABLE
r 		FIFO_SIZE
r
Toggle fields

FIFO_SIZE

Bits 0-1: FIFO_SIZE.

WRITE_BUFFERABLE

Bit 4: WRITE_BUFFERABLE.

CHSEL_WIDTH

Bits 8-10: CHSEL_WIDTH.

HWCFGR1

DMA hardware configuration 1 register

Offset: 0x3f0, size: 32, reset: 0x22222222, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_DEF7
r 		DMA_DEF6
r 		DMA_DEF5
r 		DMA_DEF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA_DEF3
r 		DMA_DEF2
r 		DMA_DEF1
r 		DMA_DEF0
r
Toggle fields

DMA_DEF0

Bits 0-1: DMA_DEF0.

DMA_DEF1

Bits 4-5: DMA_DEF1.

DMA_DEF2

Bits 8-9: DMA_DEF2.

DMA_DEF3

Bits 12-13: DMA_DEF3.

DMA_DEF4

Bits 16-17: DMA_DEF4.

DMA_DEF5

Bits 20-21: DMA_DEF5.

DMA_DEF6

Bits 24-25: DMA_DEF6.

DMA_DEF7

Bits 28-29: DMA_DEF7.

VERR

This register identifies the version of the IP.

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPDR

DMA IP identification register

Offset: 0x3f8, size: 32, reset: 0x00100002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DMA size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DMA2

0x48001000: DMA1

63/303 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 LISR
0x4 HISR
0x8 LIFCR
0xc HIFCR
0x10 S0CR
0x14 S0NDTR
0x18 S0PAR
0x1c S0M0AR
0x20 S0M1AR
0x24 S0FCR
0x28 S1CR
0x2c S1NDTR
0x30 S1PAR
0x34 S1M0AR
0x38 S1M1AR
0x3c S1FCR
0x40 S2CR
0x44 S2NDTR
0x48 S2PAR
0x4c S2M0AR
0x50 S2M1AR
0x54 S2FCR
0x58 S3CR
0x5c S3NDTR
0x60 S3PAR
0x64 S3M0AR
0x68 S3M1AR
0x6c S3FCR
0x70 S4CR
0x74 S4NDTR
0x78 S4PAR
0x7c S4M0AR
0x80 S4M1AR
0x84 S4FCR
0x88 S5CR
0x8c S5NDTR
0x90 S5PAR
0x94 S5M0AR
0x98 S5M1AR
0x9c S5FCR
0xa0 S6CR
0xa4 S6NDTR
0xa8 S6PAR
0xac S6M0AR
0xb0 S6M1AR
0xb4 S6FCR
0xb8 S7CR
0xbc S7NDTR
0xc0 S7PAR
0xc4 S7M0AR
0xc8 S7M1AR
0xcc S7FCR
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPDR
0x3fc SIDR
Toggle registers

LISR

DMA low interrupt status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF3
r 		HTIF3
r 		TEIF3
r 		DMEIF3
r 		FEIF3
r 		TCIF2
r 		HTIF2
r 		TEIF2
r 		DMEIF2
r 		FEIF2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF1
r 		HTIF1
r 		TEIF1
r 		DMEIF1
r 		FEIF1
r 		TCIF0
r 		HTIF0
r 		TEIF0
r 		DMEIF0
r 		FEIF0
r
Toggle fields

FEIF0

Bit 0: FEIF0.

DMEIF0

Bit 2: DMEIF0.

TEIF0

Bit 3: TEIF0.

HTIF0

Bit 4: HTIF0.

TCIF0

Bit 5: TCIF0.

FEIF1

Bit 6: FEIF1.

DMEIF1

Bit 8: DMEIF1.

TEIF1

Bit 9: TEIF1.

HTIF1

Bit 10: HTIF1.

TCIF1

Bit 11: TCIF1.

FEIF2

Bit 16: FEIF2.

DMEIF2

Bit 18: DMEIF2.

TEIF2

Bit 19: TEIF2.

HTIF2

Bit 20: HTIF2.

TCIF2

Bit 21: TCIF2.

FEIF3

Bit 22: FEIF3.

DMEIF3

Bit 24: DMEIF3.

TEIF3

Bit 25: TEIF3.

HTIF3

Bit 26: HTIF3.

TCIF3

Bit 27: TCIF3.

HISR

DMA high interrupt status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

20/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCIF7
r 		HTIF7
r 		TEIF7
r 		DMEIF7
r 		FEIF7
r 		TCIF6
r 		HTIF6
r 		TEIF6
r 		DMEIF6
r 		FEIF6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF5
r 		HTIF5
r 		TEIF5
r 		DMEIF5
r 		FEIF5
r 		TCIF4
r 		HTIF4
r 		TEIF4
r 		DMEIF4
r 		FEIF4
r
Toggle fields

FEIF4

Bit 0: FEIF4.

DMEIF4

Bit 2: DMEIF4.

TEIF4

Bit 3: TEIF4.

HTIF4

Bit 4: HTIF4.

TCIF4

Bit 5: TCIF4.

FEIF5

Bit 6: FEIF5.

DMEIF5

Bit 8: DMEIF5.

TEIF5

Bit 9: TEIF5.

HTIF5

Bit 10: HTIF5.

TCIF5

Bit 11: TCIF5.

FEIF6

Bit 16: FEIF6.

DMEIF6

Bit 18: DMEIF6.

TEIF6

Bit 19: TEIF6.

HTIF6

Bit 20: HTIF6.

TCIF6

Bit 21: TCIF6.

FEIF7

Bit 22: FEIF7.

DMEIF7

Bit 24: DMEIF7.

TEIF7

Bit 25: TEIF7.

HTIF7

Bit 26: HTIF7.

TCIF7

Bit 27: TCIF7.

LIFCR

DMA low interrupt flag clear register

Offset: 0x8, size: 32, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF3
w 		CHTIF3
w 		CTEIF3
w 		CDMEIF3
w 		CFEIF3
w 		CTCIF2
w 		CHTIF2
w 		CTEIF2
w 		CDMEIF2
w 		CFEIF2
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF1
w 		CHTIF1
w 		CTEIF1
w 		CDMEIF1
w 		CFEIF1
w 		CTCIF0
w 		CHTIF0
w 		CTEIF0
w 		CDMEIF0
w 		CFEIF0
w
Toggle fields

CFEIF0

Bit 0: CFEIF0.

CDMEIF0

Bit 2: CDMEIF0.

CTEIF0

Bit 3: CTEIF0.

CHTIF0

Bit 4: CHTIF0.

CTCIF0

Bit 5: CTCIF0.

CFEIF1

Bit 6: CFEIF1.

CDMEIF1

Bit 8: CDMEIF1.

CTEIF1

Bit 9: CTEIF1.

CHTIF1

Bit 10: CHTIF1.

CTCIF1

Bit 11: CTCIF1.

CFEIF2

Bit 16: CFEIF2.

CDMEIF2

Bit 18: CDMEIF2.

CTEIF2

Bit 19: CTEIF2.

CHTIF2

Bit 20: CHTIF2.

CTCIF2

Bit 21: CTCIF2.

CFEIF3

Bit 22: CFEIF3.

CDMEIF3

Bit 24: CDMEIF3.

CTEIF3

Bit 25: CTEIF3.

CHTIF3

Bit 26: CHTIF3.

CTCIF3

Bit 27: CTCIF3.

HIFCR

DMA high interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTCIF7
w 		CHTIF7
w 		CTEIF7
w 		CDMEIF7
w 		CFEIF7
w 		CTCIF6
w 		CHTIF6
w 		CTEIF6
w 		CDMEIF6
w 		CFEIF6
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTCIF5
w 		CHTIF5
w 		CTEIF5
w 		CDMEIF5
w 		CFEIF5
w 		CTCIF4
w 		CHTIF4
w 		CTEIF4
w 		CDMEIF4
w 		CFEIF4
w
Toggle fields

CFEIF4

Bit 0: CFEIF4.

CDMEIF4

Bit 2: CDMEIF4.

CTEIF4

Bit 3: CTEIF4.

CHTIF4

Bit 4: CHTIF4.

CTCIF4

Bit 5: CTCIF4.

CFEIF5

Bit 6: CFEIF5.

CDMEIF5

Bit 8: CDMEIF5.

CTEIF5

Bit 9: CTEIF5.

CHTIF5

Bit 10: CHTIF5.

CTCIF5

Bit 11: CTCIF5.

CFEIF6

Bit 16: CFEIF6.

CDMEIF6

Bit 18: CDMEIF6.

CTEIF6

Bit 19: CTEIF6.

CHTIF6

Bit 20: CHTIF6.

CTCIF6

Bit 21: CTCIF6.

CFEIF7

Bit 22: CFEIF7.

CDMEIF7

Bit 24: CDMEIF7.

CTEIF7

Bit 25: CTEIF7.

CHTIF7

Bit 26: CHTIF7.

CTCIF7

Bit 27: CTCIF7.

S0CR

This register is used to configure the concerned stream.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S0NDTR

DMA stream 0 number of data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S0PAR

DMA stream 0 peripheral address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S0M0AR

DMA stream 0 memory 0 address register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S0M1AR

DMA stream 0 memory 1 address register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S0FCR

DMA stream 0 FIFO control register

Offset: 0x24, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S1CR

This register is used to configure the concerned stream.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S1NDTR

DMA stream 1 number of data register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S1PAR

DMA stream 1 peripheral address register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S1M0AR

DMA stream 1 memory 0 address register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S1M1AR

DMA stream 1 memory 1 address register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S1FCR

DMA stream 1 FIFO control register

Offset: 0x3c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S2CR

This register is used to configure the concerned stream.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S2NDTR

DMA stream 2 number of data register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S2PAR

DMA stream 2 peripheral address register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S2M0AR

DMA stream 2 memory 0 address register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S2M1AR

DMA stream 2 memory 1 address register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S2FCR

DMA stream 2 FIFO control register

Offset: 0x54, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S3CR

This register is used to configure the concerned stream.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S3NDTR

DMA stream 3 number of data register

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S3PAR

DMA stream 3 peripheral address register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S3M0AR

DMA stream 3 memory 0 address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S3M1AR

DMA stream 3 memory 1 address register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S3FCR

DMA stream 3 FIFO control register

Offset: 0x6c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S4CR

This register is used to configure the concerned stream.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S4NDTR

DMA stream 4 number of data register

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S4PAR

DMA stream 4 peripheral address register

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S4M0AR

DMA stream 4 memory 0 address register

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S4M1AR

DMA stream 4 memory 1 address register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S4FCR

DMA stream 4 FIFO control register

Offset: 0x84, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S5CR

This register is used to configure the concerned stream.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S5NDTR

DMA stream 5 number of data register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S5PAR

DMA stream 5 peripheral address register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S5M0AR

DMA stream 5 memory 0 address register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S5M1AR

DMA stream 5 memory 1 address register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S5FCR

DMA stream 5 FIFO control register

Offset: 0x9c, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S6CR

This register is used to configure the concerned stream.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S6NDTR

DMA stream 6 number of data register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S6PAR

DMA stream 6 peripheral address register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S6M0AR

DMA stream 6 memory 0 address register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S6M1AR

DMA stream 6 memory 1 address register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S6FCR

DMA stream 6 FIFO control register

Offset: 0xb4, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

S7CR

This register is used to configure the concerned stream.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBURST
rw 		PBURST
rw 		CT
rw 		DBM
rw 		PL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINCOS
rw 		MSIZE
rw 		PSIZE
rw 		MINC
rw 		PINC
rw 		CIRC
rw 		DIR
rw 		PFCTRL
rw 		TCIE
rw 		HTIE
rw 		TEIE
rw 		DMEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

DMEIE

Bit 1: DMEIE.

TEIE

Bit 2: TEIE.

HTIE

Bit 3: HTIE.

TCIE

Bit 4: TCIE.

PFCTRL

Bit 5: PFCTRL.

DIR

Bits 6-7: DIR.

CIRC

Bit 8: CIRC.

PINC

Bit 9: PINC.

MINC

Bit 10: MINC.

PSIZE

Bits 11-12: PSIZE.

MSIZE

Bits 13-14: MSIZE.

PINCOS

Bit 15: PINCOS.

PL

Bits 16-17: PL.

DBM

Bit 18: DBM.

CT

Bit 19: CT.

PBURST

Bits 21-22: PBURST.

MBURST

Bits 23-24: MBURST.

S7NDTR

DMA stream 7 number of data register

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT
rw
Toggle fields

NDT

Bits 0-15: NDT.

S7PAR

DMA stream 7 peripheral address register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PAR
rw
Toggle fields

PAR

Bits 0-31: PAR.

S7M0AR

DMA stream 7 memory 0 address register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M0A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M0A
rw
Toggle fields

M0A

Bits 0-31: M0A.

S7M1AR

DMA stream 7 memory 1 address register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M1A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M1A
rw
Toggle fields

M1A

Bits 0-31: M1A.

S7FCR

DMA stream 7 FIFO control register

Offset: 0xcc, size: 32, reset: 0x00000021, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FEIE
rw 		FS
r 		DMDIS
rw 		FTH
rw
Toggle fields

FTH

Bits 0-1: FTH.

DMDIS

Bit 2: DMDIS.

FS

Bits 3-5: FS.

FEIE

Bit 7: FEIE.

HWCFGR2

DMA hardware configuration 2register

Offset: 0x3ec, size: 32, reset: 0x00000001, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHSEL_WIDTH
r 		WRITE_BUFFERABLE
r 		FIFO_SIZE
r
Toggle fields

FIFO_SIZE

Bits 0-1: FIFO_SIZE.

WRITE_BUFFERABLE

Bit 4: WRITE_BUFFERABLE.

CHSEL_WIDTH

Bits 8-10: CHSEL_WIDTH.

HWCFGR1

DMA hardware configuration 1 register

Offset: 0x3f0, size: 32, reset: 0x22222222, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMA_DEF7
r 		DMA_DEF6
r 		DMA_DEF5
r 		DMA_DEF4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA_DEF3
r 		DMA_DEF2
r 		DMA_DEF1
r 		DMA_DEF0
r
Toggle fields

DMA_DEF0

Bits 0-1: DMA_DEF0.

DMA_DEF1

Bits 4-5: DMA_DEF1.

DMA_DEF2

Bits 8-9: DMA_DEF2.

DMA_DEF3

Bits 12-13: DMA_DEF3.

DMA_DEF4

Bits 16-17: DMA_DEF4.

DMA_DEF5

Bits 20-21: DMA_DEF5.

DMA_DEF6

Bits 24-25: DMA_DEF6.

DMA_DEF7

Bits 28-29: DMA_DEF7.

VERR

This register identifies the version of the IP.

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPDR

DMA IP identification register

Offset: 0x3f8, size: 32, reset: 0x00100002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DMA size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DMAMUX1

0x48002000: DMAMUX1

33/209 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 C0CR
0x4 C1CR
0x8 C2CR
0xc C3CR
0x10 C4CR
0x14 C5CR
0x18 C6CR
0x1c C7CR
0x20 C8CR
0x24 C9CR
0x28 C10CR
0x2c C11CR
0x30 C12CR
0x34 C13CR
0x38 C14CR
0x3c C15CR
0x80 CSR
0x84 CFR
0x100 RG0CR
0x104 RG1CR
0x108 RG2CR
0x10c RG3CR
0x110 RG4CR
0x114 RG5CR
0x118 RG6CR
0x11c RG7CR
0x140 RGSR
0x144 RGCFR
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

C0CR

DMAMUX request line multiplexer channel 0 configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C1CR

DMAMUX request line multiplexer channel 1 configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C2CR

DMAMUX request line multiplexer channel 2 configuration register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C3CR

DMAMUX request line multiplexer channel 3 configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C4CR

DMAMUX request line multiplexer channel 4 configuration register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C5CR

DMAMUX request line multiplexer channel 5 configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C6CR

DMAMUX request line multiplexer channel 6 configuration register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C7CR

DMAMUX request line multiplexer channel 7 configuration register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C8CR

DMAMUX request line multiplexer channel 8 configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C9CR

DMAMUX request line multiplexer channel 9 configuration register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C10CR

DMAMUX request line multiplexer channel 10 configuration register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C11CR

DMAMUX request line multiplexer channel 11 configuration register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C12CR

DMAMUX request line multiplexer channel 12 configuration register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C13CR

DMAMUX request line multiplexer channel 13 configuration register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C14CR

DMAMUX request line multiplexer channel 14 configuration register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

C15CR

DMAMUX request line multiplexer channel 15 configuration register

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC_ID
rw 		NBREQ
rw 		SPOL
rw 		SE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EGE
rw 		SOIE
rw 		DMAREQ_ID
rw
Toggle fields

DMAREQ_ID

Bits 0-6: DMAREQ_ID.

SOIE

Bit 8: SOIE.

EGE

Bit 9: EGE.

SE

Bit 16: SE.

SPOL

Bits 17-18: SPOL.

NBREQ

Bits 19-23: NBREQ.

SYNC_ID

Bits 24-26: SYNC_ID.

CSR

DMAMUX request line multiplexer interrupt channel status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF15
r 		SOF14
r 		SOF13
r 		SOF12
r 		SOF11
r 		SOF10
r 		SOF9
r 		SOF8
r 		SOF7
r 		SOF6
r 		SOF5
r 		SOF4
r 		SOF3
r 		SOF2
r 		SOF1
r 		SOF0
r
Toggle fields

SOF0

Bit 0: SOF0.

SOF1

Bit 1: SOF1.

SOF2

Bit 2: SOF2.

SOF3

Bit 3: SOF3.

SOF4

Bit 4: SOF4.

SOF5

Bit 5: SOF5.

SOF6

Bit 6: SOF6.

SOF7

Bit 7: SOF7.

SOF8

Bit 8: SOF8.

SOF9

Bit 9: SOF9.

SOF10

Bit 10: SOF10.

SOF11

Bit 11: SOF11.

SOF12

Bit 12: SOF12.

SOF13

Bit 13: SOF13.

SOF14

Bit 14: SOF14.

SOF15

Bit 15: SOF15.

CFR

DMAMUX request line multiplexer interrupt clear flag register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF15
w 		CSOF14
w 		CSOF13
w 		CSOF12
w 		CSOF11
w 		CSOF10
w 		CSOF9
w 		CSOF8
w 		CSOF7
w 		CSOF6
w 		CSOF5
w 		CSOF4
w 		CSOF3
w 		CSOF2
w 		CSOF1
w 		CSOF0
w
Toggle fields

CSOF0

Bit 0: CSOF0.

CSOF1

Bit 1: CSOF1.

CSOF2

Bit 2: CSOF2.

CSOF3

Bit 3: CSOF3.

CSOF4

Bit 4: CSOF4.

CSOF5

Bit 5: CSOF5.

CSOF6

Bit 6: CSOF6.

CSOF7

Bit 7: CSOF7.

CSOF8

Bit 8: CSOF8.

CSOF9

Bit 9: CSOF9.

CSOF10

Bit 10: CSOF10.

CSOF11

Bit 11: CSOF11.

CSOF12

Bit 12: CSOF12.

CSOF13

Bit 13: CSOF13.

CSOF14

Bit 14: CSOF14.

CSOF15

Bit 15: CSOF15.

RG0CR

DMAMUX request generator channel 0 configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG1CR

DMAMUX request generator channel 1 configuration register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG2CR

DMAMUX request generator channel 2 configuration register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG3CR

DMAMUX request generator channel 3 configuration register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG4CR

DMAMUX request generator channel 4 configuration register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG5CR

DMAMUX request generator channel 5 configuration register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG6CR

DMAMUX request generator channel 6 configuration register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RG7CR

DMAMUX request generator channel 7 configuration register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GNBREQ
rw 		GPOL
rw 		GE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIE
rw 		SIG_ID
rw
Toggle fields

SIG_ID

Bits 0-2: SIG_ID.

OIE

Bit 8: OIE.

GE

Bit 16: GE.

GPOL

Bits 17-18: GPOL.

GNBREQ

Bits 19-23: GNBREQ.

RGSR

DMAMUX request generator interrupt status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF7
r 		OF6
r 		OF5
r 		OF4
r 		OF3
r 		OF2
r 		OF1
r 		OF0
r
Toggle fields

OF0

Bit 0: OF0.

OF1

Bit 1: OF1.

OF2

Bit 2: OF2.

OF3

Bit 3: OF3.

OF4

Bit 4: OF4.

OF5

Bit 5: OF5.

OF6

Bit 6: OF6.

OF7

Bit 7: OF7.

RGCFR

DMAMUX request generator interrupt clear flag register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COF7
w 		COF6
w 		COF5
w 		COF4
w 		COF3
w 		COF2
w 		COF1
w 		COF0
w
Toggle fields

COF0

Bit 0: COF0.

COF1

Bit 1: COF1.

COF2

Bit 2: COF2.

COF3

Bit 3: COF3.

COF4

Bit 4: COF4.

COF5

Bit 5: COF5.

COF6

Bit 6: COF6.

COF7

Bit 7: COF7.

HWCFGR2

DMAMUX hardware configuration 2 register

Offset: 0x3ec, size: 32, reset: 0x00000008, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NUM_DMA_EXT_REQ
r
Toggle fields

NUM_DMA_EXT_REQ

Bits 0-7: NUM_DMA_EXT_REQ.

HWCFGR1

DMAMUX hardware configuration 1 register

Offset: 0x3f0, size: 32, reset: 0x08086C10, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NUM_DMA_REQGEN
r 		NUM_DMA_TRIG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NUM_DMA_PERIPH_REQ
r 		NUM_DMA_STREAMS
r
Toggle fields

NUM_DMA_STREAMS

Bits 0-7: NUM_DMA_STREAMS.

NUM_DMA_PERIPH_REQ

Bits 8-15: NUM_DMA_PERIPH_REQ.

NUM_DMA_TRIG

Bits 16-23: NUM_DMA_TRIG.

NUM_DMA_REQGEN

Bits 24-31: NUM_DMA_REQGEN.

VERR

This register identifies the IP version.

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

This register identifies the IP.

Offset: 0x3f8, size: 32, reset: 0x00100011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

DMAMUX size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

DTS

0x50028000: DTS register block

10/64 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CFGR1
0x8 T0VALR1
0x10 RAMPVALR
0x14 ITR1
0x1c DR
0x20 SR
0x24 ITENR
0x28 ICIFR
0x2c OR
Toggle registers

CFGR1

DTS_CFGR1 is the configuration register for temperature sensor 1.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSREF_CLK_DIV
rw 		Q_MEAS_opt
rw 		REFCLK_SEL
rw 		TS1_SMP_TIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_INTRIG_SEL
rw 		TS1_START
rw 		TS1_EN
rw
Toggle fields

TS1_EN

Bit 0: TS1_EN.

TS1_START

Bit 4: TS1_START.

TS1_INTRIG_SEL

Bits 8-11: TS1_INTRIG_SEL.

TS1_SMP_TIME

Bits 16-19: TS1_SMP_TIME.

REFCLK_SEL

Bit 20: REFCLK_SEL.

Q_MEAS_opt

Bit 21: Q_MEAS_opt.

HSREF_CLK_DIV

Bits 24-30: HSREF_CLK_DIV.

T0VALR1

DTS_T0VALR1 contains the value of the factory calibration temperature (T0) for temperature sensor 1. The system reset value is factory trimmed.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS1_T0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_FMT0
r
Toggle fields

TS1_FMT0

Bits 0-15: TS1_FMT0.

TS1_T0

Bits 16-17: TS1_T0.

RAMPVALR

The DTS_RAMPVALR is the ramp coefficient for the temperature sensor. The system reset value is factory trimmed.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_RAMP_COEFF
r
Toggle fields

TS1_RAMP_COEFF

Bits 0-15: TS1_RAMP_COEFF.

ITR1

DTS_ITR1 contains the threshold values for sensor 1.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS1_HITTHD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_LITTHD
rw
Toggle fields

TS1_LITTHD

Bits 0-15: TS1_LITTHD.

TS1_HITTHD

Bits 16-31: TS1_HITTHD.

DR

The DTS_DR contains the number of REF_CLK cycles used to compute the FM(T) frequency.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_MFREQ
rw
Toggle fields

TS1_MFREQ

Bits 0-15: TS1_MFREQ.

SR

Temperature sensor status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_RDY
r 		TS1_AITHF
r 		TS1_AITLF
r 		TS1_AITEF
r 		TS1_ITHF
r 		TS1_ITLF
r 		TS1_ITEF
r
Toggle fields

TS1_ITEF

Bit 0: TS1_ITEF.

TS1_ITLF

Bit 1: TS1_ITLF.

TS1_ITHF

Bit 2: TS1_ITHF.

TS1_AITEF

Bit 4: TS1_AITEF.

TS1_AITLF

Bit 5: TS1_AITLF.

TS1_AITHF

Bit 6: TS1_AITHF.

TS1_RDY

Bit 15: TS1_RDY.

ITENR

Temperature sensor interrupt enable register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_AITHEN
rw 		TS1_AITLEN
rw 		TS1_AITEEN
rw 		TS1_ITHEN
rw 		TS1_ITLEN
rw 		TS1_ITEEN
rw
Toggle fields

TS1_ITEEN

Bit 0: TS1_ITEEN.

TS1_ITLEN

Bit 1: TS1_ITLEN.

TS1_ITHEN

Bit 2: TS1_ITHEN.

TS1_AITEEN

Bit 4: TS1_AITEEN.

TS1_AITLEN

Bit 5: TS1_AITLEN.

TS1_AITHEN

Bit 6: TS1_AITHEN.

ICIFR

DTS_ICIFR is the control register for the interrupt flags.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS1_CAITHF
rw 		TS1_CAITLF
rw 		TS1_CAITEF
rw 		TS1_CITHF
rw 		TS1_CITLF
rw 		TS1_CITEF
rw
Toggle fields

TS1_CITEF

Bit 0: TS1_CITEF.

TS1_CITLF

Bit 1: TS1_CITLF.

TS1_CITHF

Bit 2: TS1_CITHF.

TS1_CAITEF

Bit 4: TS1_CAITEF.

TS1_CAITLF

Bit 5: TS1_CAITLF.

TS1_CAITHF

Bit 6: TS1_CAITHF.

OR

The DTS_OR contains general-purpose option bits.

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_Op31
rw 		TS_Op30
rw 		TS_Op29
rw 		TS_Op28
rw 		TS_Op27
rw 		TS_Op26
rw 		TS_Op25
rw 		TS_Op24
rw 		TS_Op23
rw 		TS_Op22
rw 		TS_Op21
rw 		TS_Op20
rw 		TS_Op19
rw 		TS_Op18
rw 		TS_Op17
rw 		TS_Op16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_Op15
rw 		TS_Op14
rw 		TS_Op13
rw 		TS_Op12
rw 		TS_Op11
rw 		TS_Op10
rw 		TS_Op9
rw 		TS_Op8
rw 		TS_Op7
rw 		TS_Op6
rw 		TS_Op5
rw 		TS_Op4
rw 		TS_Op3
rw 		TS_Op2
rw 		TS_Op1
rw 		TS_Op0
rw
Toggle fields

TS_Op0

Bit 0: TS_Op0.

TS_Op1

Bit 1: TS_Op1.

TS_Op2

Bit 2: TS_Op2.

TS_Op3

Bit 3: TS_Op3.

TS_Op4

Bit 4: TS_Op4.

TS_Op5

Bit 5: TS_Op5.

TS_Op6

Bit 6: TS_Op6.

TS_Op7

Bit 7: TS_Op7.

TS_Op8

Bit 8: TS_Op8.

TS_Op9

Bit 9: TS_Op9.

TS_Op10

Bit 10: TS_Op10.

TS_Op11

Bit 11: TS_Op11.

TS_Op12

Bit 12: TS_Op12.

TS_Op13

Bit 13: TS_Op13.

TS_Op14

Bit 14: TS_Op14.

TS_Op15

Bit 15: TS_Op15.

TS_Op16

Bit 16: TS_Op16.

TS_Op17

Bit 17: TS_Op17.

TS_Op18

Bit 18: TS_Op18.

TS_Op19

Bit 19: TS_Op19.

TS_Op20

Bit 20: TS_Op20.

TS_Op21

Bit 21: TS_Op21.

TS_Op22

Bit 22: TS_Op22.

TS_Op23

Bit 23: TS_Op23.

TS_Op24

Bit 24: TS_Op24.

TS_Op25

Bit 25: TS_Op25.

TS_Op26

Bit 26: TS_Op26.

TS_Op27

Bit 27: TS_Op27.

TS_Op28

Bit 28: TS_Op28.

TS_Op29

Bit 29: TS_Op29.

TS_Op30

Bit 30: TS_Op30.

TS_Op31

Bit 31: TS_Op31.

ETH_DMA

0x5800b000: ETH_DMA

20/146 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 DMAMR
0x4 DMASBMR
0x8 DMAISR
0xc DMADSR
0x20 DMAA4TxACR
0x24 DMAA4RxACR
0x28 DMAA4DACR
0x100 DMAC0CR
0x104 DMAC0TxCR
0x108 DMAC0RxCR
0x114 DMAC0TxDLAR
0x11c DMAC0RxDLAR
0x120 DMAC0TxDTPR
0x128 DMAC0RxDTPR
0x12c DMAC0TxRLR
0x130 DMAC0RxRLR
0x134 DMAC0IER
0x138 DMAC0RxIWTR
0x13c DMAC0SFCSR
0x144 DMAC0CATxDR
0x14c DMAC0CARxDR
0x154 DMAC0CATxBR
0x15c DMAC0CARxBR
0x160 DMAC0SR
0x16c DMAC0MFCR
0x180 DMAC1CR
0x184 DMAC1TxCR
0x194 DMAC1TxDLAR
0x1a0 DMAC1TxDTPR
0x1ac DMAC1TxRLR
0x1b4 DMAC1IER
0x1bc DMAC1SFCSR
0x1c4 DMAC1CATxDR
0x1d4 DMAC1CATxBR
0x1e0 DMAC1SR
0x1ec DMAC1MFCR
Toggle registers

DMAMR

DMA mode register

Offset: 0x0, size: 32, reset: 0x00008000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw 		TXPR
rw 		TAA
rw 		SWR
rw
Toggle fields

SWR

Bit 0: Software Reset.

TAA

Bits 2-4: TAA.

TXPR

Bit 11: Transmit priority.

PR

Bits 12-14: Priority ratio.

INTM

Bits 16-17: Interrupt Mode.

DMASBMR

System bus mode register

Offset: 0x4, size: 32, reset: 0x00008000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN_LPI
rw 		LPI_XIT_PKT
rw 		WR_OSR_LMT
rw 		RD_OSR_LMT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONEKBBE
rw 		AAL
rw 		BLEN256
rw 		BLEN128
rw 		BLEN64
rw 		BLEN32
rw 		BLEN16
rw 		BLEN8
rw 		BLEN4
rw 		FB
rw
Toggle fields

FB

Bit 0: Fixed Burst Length.

BLEN4

Bit 1: BLEN4.

BLEN8

Bit 2: BLEN8.

BLEN16

Bit 3: BLEN16.

BLEN32

Bit 4: BLEN32.

BLEN64

Bit 5: BLEN64.

BLEN128

Bit 6: BLEN128.

BLEN256

Bit 7: BLEN256.

AAL

Bit 12: Address-Aligned Beats.

ONEKBBE

Bit 13: ONEKBBE.

RD_OSR_LMT

Bits 16-17: RD_OSR_LMT.

WR_OSR_LMT

Bits 24-25: WR_OSR_LMT.

LPI_XIT_PKT

Bit 30: LPI_XIT_PKT.

EN_LPI

Bit 31: EN_LPI.

DMAISR

Interrupt status register

Offset: 0x8, size: 32, reset: 0x00008000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MACIS
r 		MTLIS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DC1IS
r 		DC0IS
r
Toggle fields

DC0IS

Bit 0: DMA Channel Interrupt Status.

DC1IS

Bit 1: DC1IS.

MTLIS

Bit 16: MTL Interrupt Status.

MACIS

Bit 17: MAC Interrupt Status.

DMADSR

Debug status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TPS1
r 		RPS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPS0
r 		RPS0
r 		AXRHSTS
r 		AXWHSTS
r
Toggle fields

AXWHSTS

Bit 0: AHB Master Write Channel.

AXRHSTS

Bit 1: AXRHSTS.

RPS0

Bits 8-11: RPS0.

TPS0

Bits 12-15: TPS0.

RPS1

Bits 16-19: RPS1.

TPS1

Bits 20-23: TPS1.

DMAA4TxACR

AXI4 transmit channel ACE control register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
THC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEC
rw 		TDRC
rw
Toggle fields

TDRC

Bits 0-3: TDRC.

TEC

Bits 8-11: TEC.

THC

Bits 16-19: THC.

DMAA4RxACR

AXI4 receive channel ACE control register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDC
rw 		RHC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPC
rw 		RDWC
rw
Toggle fields

RDWC

Bits 0-3: RDWC.

RPC

Bits 8-11: RPC.

RHC

Bits 16-19: RHC.

RDC

Bits 24-25: RDC.

DMAA4DACR

AXI4 descriptor ACE control register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRP
rw 		RDP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDRC
rw 		TDWD
rw 		TDWC
rw
Toggle fields

TDWC

Bits 0-3: TDWC.

TDWD

Bits 4-5: TDWD.

RDRC

Bits 8-11: RDRC.

RDP

Bits 16-18: RDP.

WRP

Bits 20-22: WRP.

DMAC0CR

Channel 0 control register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSL
rw 		PBLX8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSS
rw
Toggle fields

MSS

Bits 0-13: MSS.

PBLX8

Bit 16: PBLX8.

DSL

Bits 18-20: DSL.

DMAC0TxCR

Channel 0 transmit control register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TQOS
rw 		TXPBL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSE
rw 		OSF
rw 		TCW
rw 		ST
rw
Toggle fields

ST

Bit 0: ST.

TCW

Bits 1-3: TCW.

OSF

Bit 4: OSF.

TSE

Bit 12: TSE.

TXPBL

Bits 16-21: TXPBL.

TQOS

Bits 24-27: TQOS.

DMAC0RxCR

Channel receive control register

Offset: 0x108, size: 32, reset: 0x00008000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPF
rw 		RQOS
rw 		RXPBL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBSZ
rw 		SR
rw
Toggle fields

SR

Bit 0: Start or Stop Receive Command.

RBSZ

Bits 1-14: Receive Buffer size.

RXPBL

Bits 16-21: RXPBL.

RQOS

Bits 24-27: RQOS.

RPF

Bit 31: DMA Rx Channel Packet Flush.

DMAC0TxDLAR

Channel i Tx descriptor list address register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDESLA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDESLA
rw
Toggle fields

TDESLA

Bits 3-31: Start of Transmit List.

DMAC0RxDLAR

Channel Rx descriptor list address register

Offset: 0x11c, size: 32, reset: 0x00008000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDESLA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDESLA
rw
Toggle fields

RDESLA

Bits 3-31: Start of Receive List.

DMAC0TxDTPR

Channel Tx descriptor tail pointer register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDT
rw
Toggle fields

TDT

Bits 3-31: Transmit Descriptor Tail Pointer.

DMAC0RxDTPR

Channel Rx descriptor tail pointer register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDT
rw
Toggle fields

RDT

Bits 3-31: Receive Descriptor Tail Pointer.

DMAC0TxRLR

Channel Tx descriptor ring length register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDRL
rw
Toggle fields

TDRL

Bits 0-9: Transmit Descriptor Ring Length.

DMAC0RxRLR

Channel Rx descriptor ring length register

Offset: 0x130, size: 32, reset: 0x00008000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDRL
rw
Toggle fields

RDRL

Bits 0-9: Receive Descriptor Ring Length.

DMAC0IER

Channel interrupt enable register

Offset: 0x134, size: 32, reset: 0x00008000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIE
rw 		AIE
rw 		CDEE
rw 		FBEE
rw 		ERIE
rw 		ETIE
rw 		RWTE
rw 		RSE
rw 		RBUE
rw 		RIE
rw 		TBUE
rw 		TXSE
rw 		TIE
rw
Toggle fields

TIE

Bit 0: Transmit Interrupt Enable.

TXSE

Bit 1: Transmit Stopped Enable.

TBUE

Bit 2: Transmit Buffer Unavailable Enable.

RIE

Bit 6: Receive Interrupt Enable.

RBUE

Bit 7: Receive Buffer Unavailable Enable.

RSE

Bit 8: Receive Stopped Enable.

RWTE

Bit 9: Receive Watchdog Timeout Enable.

ETIE

Bit 10: Early Transmit Interrupt Enable.

ERIE

Bit 11: Early Receive Interrupt Enable.

FBEE

Bit 12: Fatal Bus Error Enable.

CDEE

Bit 13: Context Descriptor Error Enable.

AIE

Bit 14: Abnormal Interrupt Summary Enable.

NIE

Bit 15: Normal Interrupt Summary Enable.

DMAC0RxIWTR

Channel Rx interrupt watchdog timer register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RWT
rw
Toggle fields

RWT

Bits 0-7: Receive Interrupt Watchdog Timer Count.

DMAC0SFCSR

Channel i slot function control status register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC
rw 		ESC
rw
Toggle fields

ESC

Bit 0: ESC.

ASC

Bit 1: ASC.

RSN

Bits 16-19: RSN.

DMAC0CATxDR

Channel current application transmit descriptor register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURTDESAPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURTDESAPTR
r
Toggle fields

CURTDESAPTR

Bits 0-31: Application Transmit Descriptor Address Pointer.

DMAC0CARxDR

Channel 0 current application receive descriptor register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRDESAPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRDESAPTR
r
Toggle fields

CURRDESAPTR

Bits 0-31: Application Transmit Descriptor Address Pointer.

DMAC0CATxBR

Channel 0 current application transmit buffer register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURTBUFAPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURTBUFAPTR
r
Toggle fields

CURTBUFAPTR

Bits 0-31: Application Transmit Buffer Address Pointer.

DMAC0CARxBR

Channel current application receive buffer register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURRBUFAPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURRBUFAPTR
r
Toggle fields

CURRBUFAPTR

Bits 0-31: Application Receive Buffer Address Pointer.

DMAC0SR

Channel status register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REB
rw 		TEB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIS
rw 		AIS
rw 		CDE
rw 		FBE
rw 		ERI
rw 		ETI
rw 		RWT
rw 		RPS
rw 		RBU
rw 		RI
rw 		TBU
rw 		TPS
rw 		TI
rw
Toggle fields

TI

Bit 0: Transmit Interrupt.

TPS

Bit 1: Transmit Process Stopped.

TBU

Bit 2: Transmit Buffer Unavailable.

RI

Bit 6: Receive Interrupt.

RBU

Bit 7: Receive Buffer Unavailable.

RPS

Bit 8: Receive Process Stopped.

RWT

Bit 9: Receive Watchdog Timeout.

ETI

Bit 10: Early Transmit Interrupt.

ERI

Bit 11: Early Receive Interrupt.

FBE

Bit 12: Fatal Bus Error.

CDE

Bit 13: Context Descriptor Error.

AIS

Bit 14: Abnormal Interrupt Summary.

NIS

Bit 15: Normal Interrupt Summary.

TEB

Bits 16-18: Tx DMA Error Bits.

REB

Bits 19-21: Rx DMA Error Bits.

DMAC0MFCR

Channel missed frame count register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFCO
r 		MFC
r
Toggle fields

MFC

Bits 0-10: Dropped Packet Counters.

MFCO

Bit 15: Overflow status of the MFC Counter.

DMAC1CR

Channel 1 control register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSL
rw 		PBLX8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSS
rw
Toggle fields

MSS

Bits 0-13: MSS.

PBLX8

Bit 16: PBLX8.

DSL

Bits 18-20: DSL.

DMAC1TxCR

Channel 1 transmit control register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TQOS
rw 		TXPBL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSE
rw 		OSF
rw 		TCW
rw 		ST
rw
Toggle fields

ST

Bit 0: ST.

TCW

Bits 1-3: TCW.

OSF

Bit 4: OSF.

TSE

Bit 12: TSE.

TXPBL

Bits 16-21: TXPBL.

TQOS

Bits 24-27: TQOS.

DMAC1TxDLAR

Channel i Tx descriptor list address register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDESLA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDESLA
rw
Toggle fields

TDESLA

Bits 3-31: Start of Transmit List.

DMAC1TxDTPR

Channel Tx descriptor tail pointer register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDT
rw
Toggle fields

TDT

Bits 3-31: Transmit Descriptor Tail Pointer.

DMAC1TxRLR

Channel Tx descriptor ring length register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDRL
rw
Toggle fields

TDRL

Bits 0-9: Transmit Descriptor Ring Length.

DMAC1IER

Channel interrupt enable register

Offset: 0x1b4, size: 32, reset: 0x00008000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIE
rw 		AIE
rw 		CDEE
rw 		FBEE
rw 		ERIE
rw 		ETIE
rw 		RWTE
rw 		RSE
rw 		RBUE
rw 		RIE
rw 		TBUE
rw 		TXSE
rw 		TIE
rw
Toggle fields

TIE

Bit 0: Transmit Interrupt Enable.

TXSE

Bit 1: Transmit Stopped Enable.

TBUE

Bit 2: Transmit Buffer Unavailable Enable.

RIE

Bit 6: Receive Interrupt Enable.

RBUE

Bit 7: Receive Buffer Unavailable Enable.

RSE

Bit 8: Receive Stopped Enable.

RWTE

Bit 9: Receive Watchdog Timeout Enable.

ETIE

Bit 10: Early Transmit Interrupt Enable.

ERIE

Bit 11: Early Receive Interrupt Enable.

FBEE

Bit 12: Fatal Bus Error Enable.

CDEE

Bit 13: Context Descriptor Error Enable.

AIE

Bit 14: Abnormal Interrupt Summary Enable.

NIE

Bit 15: Normal Interrupt Summary Enable.

DMAC1SFCSR

Channel i slot function control status register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASC
rw 		ESC
rw
Toggle fields

ESC

Bit 0: ESC.

ASC

Bit 1: ASC.

RSN

Bits 16-19: RSN.

DMAC1CATxDR

Channel current application transmit descriptor register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURTDESAPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURTDESAPTR
r
Toggle fields

CURTDESAPTR

Bits 0-31: Application Transmit Descriptor Address Pointer.

DMAC1CATxBR

Channel 0 current application transmit buffer register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURTBUFAPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURTBUFAPTR
r
Toggle fields

CURTBUFAPTR

Bits 0-31: Application Transmit Buffer Address Pointer.

DMAC1SR

Channel status register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REB
rw 		TEB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIS
rw 		AIS
rw 		CDE
rw 		FBE
rw 		ERI
rw 		ETI
rw 		RWT
rw 		RPS
rw 		RBU
rw 		RI
rw 		TBU
rw 		TPS
rw 		TI
rw
Toggle fields

TI

Bit 0: Transmit Interrupt.

TPS

Bit 1: Transmit Process Stopped.

TBU

Bit 2: Transmit Buffer Unavailable.

RI

Bit 6: Receive Interrupt.

RBU

Bit 7: Receive Buffer Unavailable.

RPS

Bit 8: Receive Process Stopped.

RWT

Bit 9: Receive Watchdog Timeout.

ETI

Bit 10: Early Transmit Interrupt.

ERI

Bit 11: Early Receive Interrupt.

FBE

Bit 12: Fatal Bus Error.

CDE

Bit 13: Context Descriptor Error.

AIS

Bit 14: Abnormal Interrupt Summary.

NIS

Bit 15: Normal Interrupt Summary.

TEB

Bits 16-18: Tx DMA Error Bits.

REB

Bits 19-21: Rx DMA Error Bits.

DMAC1MFCR

Channel missed frame count register

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFCO
r 		MFC
r
Toggle fields

MFC

Bits 0-10: Dropped Packet Counters.

MFCO

Bit 15: Overflow status of the MFC Counter.

ETH_MAC_MMC

0x5800a000: ETH_MAC_MMC

103/356 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MACCR
0x4 MACECR
0x8 MACPFR
0xc MACWTR
0x10 MACHT0R
0x14 MACHT1R
0x50 MACVTR
0x58 MACVHTR
0x60 MACVIR
0x64 MACIVIR
0x70 MACQ0TxFCR
0x90 MACRxFCR
0x98 MACTxQPMR
0xa0 MACRxQC0R
0xa4 MACRxQC1R
0xa8 MACRxQC2R
0xb0 MACISR
0xb4 MACIER
0xb8 MACRxTxSR
0xc0 MACPCSR
0xc4 MACRWKPFR
0xd0 MACLCSR
0xd4 MACLTCR
0xd8 MACLETR
0xdc MAC1USTCR
0xf8 MACPHYCSR
0x110 MACVR
0x114 MACDR
0x120 MACHWF1R
0x124 MACHWF2R
0x200 MACMDIOAR
0x204 MACMDIODR
0x300 MACA0HR
0x304 MACA0LR
0x308 MACA1HR
0x30c MACA1LR
0x310 MACA2HR
0x314 MACA2LR
0x318 MACA3HR
0x31c MACA3LR
0x700 MMC_CONTROL
0x704 MMC_RX_INTERRUPT
0x708 MMC_TX_INTERRUPT
0x70c MMC_RX_INTERRUPT_MASK
0x710 MMC_TX_INTERRUPT_MASK
0x74c TX_SINGLE_COLLISION_GOOD_PACKETS
0x750 TX_MULTIPLE_COLLISION_GOOD_PACKETS
0x768 TX_PACKET_COUNT_GOOD
0x794 RX_CRC_ERROR_PACKETS
0x798 RX_ALIGNMENT_ERROR_PACKETS
0x7c4 RX_UNICAST_PACKETS_GOOD
0x7ec TX_LPI_USEC_CNTR
0x7f0 TX_LPI_TRAN_CNTR
0x7f4 RX_LPI_USEC_CNTR
0x7f8 RX_LPI_TRAN_CNTR
0x900 MACL3L4C0R
0x904 MACL4A0R
0x910 MACL3A00R
0x914 MACL3A10R
0x918 MACL3A20
0x91c MACL3A30
0x930 MACL3L4C1R
0x934 MACL4A1R
0x940 MACL3A01R
0x944 MACL3A11R
0x948 MACL3A21R
0x94c MACL3A31R
0xae0 MACARPAR
0xb00 MACTSCR
0xb04 MACSSIR
0xb08 MACSTSR
0xb0c MACSTNR
0xb10 MACSTSUR
0xb14 MACSTNUR
0xb18 MACTSAR
0xb20 MACTSSR
0xb30 MACTxTSSNR
0xb34 MACTxTSSSR
0xb40 MACACR
0xb48 MACATSNR
0xb4c MACATSSR
0xb50 MACTSIACR
0xb54 MACTSEACR
0xb58 MACTSICNR
0xb5c MACTSECNR
0xb70 MACPPSCR
0xb80 MACPPSTTSR
0xb84 MACPPSTTNR
0xb88 MACPPSIR
0xb8c MACPPSWR
0xbc0 MACPOCR
0xbc4 MACSPI0R
0xbc8 MACSPI1R
0xbcc MACSPI2R
0xbd0 MACLMIR
Toggle registers

MACCR

The MAC Configuration Register establishes the operating mode of the MAC.

Offset: 0x0, size: 32, reset: 0x00008000, access: read-write

0/25 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARPEN
rw 		SARC
rw 		IPC
rw 		IPG
rw 		GPSLCE
rw 		S2KP
rw 		CST
rw 		ACS
rw 		WD
rw 		BE
rw 		JD
rw 		JE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS
rw 		FES
rw 		DM
rw 		LM
rw 		ECRSFD
rw 		DO
rw 		DCRS
rw 		DR
rw 		BL
rw 		DC
rw 		PRELEN
rw 		TE
rw 		RE
rw
Toggle fields

RE

Bit 0: RE.

TE

Bit 1: TE.

PRELEN

Bits 2-3: PRELEN.

DC

Bit 4: DC.

BL

Bits 5-6: BL.

DR

Bit 8: DR.

DCRS

Bit 9: DCRS.

DO

Bit 10: DO.

ECRSFD

Bit 11: ECRSFD.

LM

Bit 12: LM.

DM

Bit 13: DM.

FES

Bit 14: FES.

PS

Bit 15: PS.

JE

Bit 16: JE.

JD

Bit 17: JD.

BE

Bit 18: BE.

WD

Bit 19: WD.

ACS

Bit 20: ACS.

CST

Bit 21: CST.

S2KP

Bit 22: S2KP.

GPSLCE

Bit 23: GPSLCE.

IPG

Bits 24-26: IPG.

IPC

Bit 27: IPC.

SARC

Bits 28-30: SARC.

ARPEN

Bit 31: ARPEN.

MACECR

The MAC Extended Configuration Register establishes the operating mode of the MAC.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIPG
rw 		EIPGEN
rw 		USP
rw 		SPEN
rw 		DCRCC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPSL
rw
Toggle fields

GPSL

Bits 0-13: GPSL.

DCRCC

Bit 16: DCRCC.

SPEN

Bit 17: SPEN.

USP

Bit 18: USP.

EIPGEN

Bit 24: EIPGEN.

EIPG

Bits 25-29: EIPG.

MACPFR

The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of filtering is performed on the incoming packet based on other controls such as Pass Bad Packets and Pass Control Packets.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw 		DNTU
rw 		IPFE
rw 		VTFE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPF
rw 		SAF
rw 		SAIF
rw 		PCF
rw 		DBF
rw 		PM
rw 		DAIF
rw 		HMC
rw 		HUC
rw 		PR
rw
Toggle fields

PR

Bit 0: PR.

HUC

Bit 1: HUC.

HMC

Bit 2: HMC.

DAIF

Bit 3: DAIF.

PM

Bit 4: PM.

DBF

Bit 5: DBF.

PCF

Bits 6-7: PCF.

SAIF

Bit 8: SAIF.

SAF

Bit 9: SAF.

HPF

Bit 10: HPF.

VTFE

Bit 16: VTFE.

IPFE

Bit 20: IPFE.

DNTU

Bit 21: DNTU.

RA

Bit 31: RA.

MACWTR

The Watchdog Timeout register controls the watchdog timeout for received packets.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWE
rw 		WTO
rw
Toggle fields

WTO

Bits 0-3: WTO.

PWE

Bit 8: PWE.

MACHT0R

The Hash Table Register 0 contains the first 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT31T0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT31T0
rw
Toggle fields

HT31T0

Bits 0-31: HT31T0.

MACHT1R

The Hash Table Register 1contains the last 32 bits of the Hash table (64 bits). For Hash filtering, the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register 0 or 1). The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). Perform bitwise reversal for the value obtained in Step 1. Take the upper 7 or 8 bits from the value obtained in Step 2. If the corresponding bit value of the register is 1, the packet is accepted. Otherwise, it is rejected. If the PM bit is set in ETH_MACPFR, all multicast packets are accepted regardless of the multicast Hash values. If the Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HT63T32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HT63T32
rw
Toggle fields

HT63T32

Bits 0-31: HT63T32.

MACVTR

The VLAN Tag register identifies the IEEE 802.1Q VLAN type packets.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIVLRXS
rw 		EIVLS
rw 		ERIVLT
rw 		EDVLP
rw 		VTHM
rw 		EVLRXS
rw 		EVLS
rw 		DOVLTC
rw 		ERSVLM
rw 		ESVL
rw 		VTIM
rw 		ETV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VL
rw
Toggle fields

VL

Bits 0-15: VL.

ETV

Bit 16: ETV.

VTIM

Bit 17: VTIM.

ESVL

Bit 18: ESVL.

ERSVLM

Bit 19: ERSVLM.

DOVLTC

Bit 20: DOVLTC.

EVLS

Bits 21-22: EVLS.

EVLRXS

Bit 24: EVLRXS.

VTHM

Bit 25: VTHM.

EDVLP

Bit 26: EDVLP.

ERIVLT

Bit 27: ERIVLT.

EIVLS

Bits 28-29: EIVLS.

EIVLRXS

Bit 31: EIVLRXS.

MACVHTR

When the ERSVLM bit of ETH_MACHT1R register is set, the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For Hash filtering, the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the ETV bit of ETH_MACVTR register) in the incoming packet is passed through the CRC logic. The upper four bits of the calculated CRC are used to index the contents of the VLAN Hash table. For example, a Hash value of 1000 selects Bit 8 of the VLAN Hash table. The Hash value of the destination address is calculated in the following way: Calculate the 32-bit CRC for the VLAN tag or ID (For steps to calculate CRC32, see Section 3.2.8 of IEEE 802.3). Perform bitwise reversal for the value obtained in step 1. Take the upper four bits from the value obtained in step 2. If the VLAN Hash Table register is configured to be double-synchronized to the GMII clock domain, the synchronization is triggered only when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLHT
rw
Toggle fields

VLHT

Bits 0-15: VLHT.

MACVIR

The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLTI
rw 		CSVL
rw 		VLP
rw 		VLC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLT
rw
Toggle fields

VLT

Bits 0-15: VLT.

VLC

Bits 16-17: VLC.

VLP

Bit 18: VLP.

CSVL

Bit 19: CSVL.

VLTI

Bit 20: VLTI.

MACIVIR

The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VLTI
rw 		CSVL
rw 		VLP
rw 		VLC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VLT
rw
Toggle fields

VLT

Bits 0-15: VLT.

VLC

Bits 16-17: VLC.

VLP

Bit 18: VLP.

CSVL

Bit 19: CSVL.

VLTI

Bit 20: VLTI.

MACQ0TxFCR

The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a Pause packet. The fields of the control packet are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control packet. The Busy bit remains set until the control packet is transferred onto the cable. The application must make sure that the Busy bit is cleared before writing to the register.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DZPQ
rw 		PLT
rw 		TFE
rw 		FCB_BPA
rw
Toggle fields

FCB_BPA

Bit 0: FCB_BPA.

TFE

Bit 1: TFE.

PLT

Bits 4-6: PLT.

DZPQ

Bit 7: DZPQ.

PT

Bits 16-31: PT.

MACRxFCR

The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UP
rw 		RFE
rw
Toggle fields

RFE

Bit 0: RFE.

UP

Bit 1: UP.

MACTxQPMR

The transmit queue priority mapping 0 register contains the priority values assigned to Tx queue 0 and tx queue 1.

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSTQ1
r 		PSTQ0
r
Toggle fields

PSTQ0

Bits 0-7: PSTQ0.

PSTQ1

Bits 8-15: PSTQ1.

MACRxQC0R

The Receive Queue Control 0 register controls the queue management in the MAC Receiver.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXQ1EN
rw 		RXQ0EN
rw
Toggle fields

RXQ0EN

Bits 0-1: RXQ0EN.

RXQ1EN

Bits 2-3: RXQ1EN.

MACRxQC1R

The Receive Queue Control 1 register controls queue 1 management in the MAC receiver.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TACPQE
rw 		MCBCQEN
rw 		MCBCQ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPQ
rw 		AVPTPQ
rw 		AVCPQ
rw
Toggle fields

AVCPQ

Bits 0-2: AVCPQ.

AVPTPQ

Bits 4-6: AVPTPQ.

UPQ

Bits 12-14: UPQ.

MCBCQ

Bits 16-18: MCBCQ.

MCBCQEN

Bit 20: MCBCQEN.

TACPQE

Bit 21: TACPQE.

MACRxQC2R

This register controls the routing of tagged packets based on the USP (user priority) field of the received packets to the Rx queue 0 and 1.

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSRQ1
rw 		PSRQ0
rw
Toggle fields

PSRQ0

Bits 0-7: PSRQ0.

PSRQ1

Bits 8-15: PSRQ1.

MACISR

The Interrupt Status register contains the status of interrupts.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSTSIS
r 		TXSTSIS
r 		TSIS
r 		MMCTXIS
r 		MMCRXIS
r 		MMCIS
r 		LPIIS
r 		PMTIS
r 		PHYIS
r 		RGSMIIIS
r
Toggle fields

RGSMIIIS

Bit 0: RGSMIIIS.

PHYIS

Bit 3: PHYIS.

PMTIS

Bit 4: PMTIS.

LPIIS

Bit 5: LPIIS.

MMCIS

Bit 8: MMCIS.

MMCRXIS

Bit 9: MMCRXIS.

MMCTXIS

Bit 10: MMCTXIS.

TSIS

Bit 12: TSIS.

TXSTSIS

Bit 13: TXSTSIS.

RXSTSIS

Bit 14: RXSTSIS.

MACIER

The Interrupt Enable register contains the masks for generating the interrupts.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXSTSIE
rw 		TXSTSIE
rw 		TSIE
rw 		LPIIE
rw 		PMTIE
rw 		PHYIE
rw 		RGSMIIIE
rw
Toggle fields

RGSMIIIE

Bit 0: RGSMIIIE.

PHYIE

Bit 3: PHYIE.

PMTIE

Bit 4: PMTIE.

LPIIE

Bit 5: LPIIE.

TSIE

Bit 12: TSIE.

TXSTSIE

Bit 13: TXSTSIE.

RXSTSIE

Bit 14: RXSTSIE.

MACRxTxSR

The Receive Transmit Status register contains the Receive and Transmit Error status.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RWT
r 		EXCOL
r 		LCOL
r 		EXDEF
r 		LCARR
r 		NCARR
r 		TJT
r
Toggle fields

TJT

Bit 0: TJT.

NCARR

Bit 1: NCARR.

LCARR

Bit 2: LCARR.

EXDEF

Bit 3: EXDEF.

LCOL

Bit 4: LCOL.

EXCOL

Bit 5: EXCOL.

RWT

Bit 8: RWT.

MACPCSR

The PMT Control and Status Register is present only when you select the PMT module in coreConsultant.

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RWKFILTRST
rw 		RWKPTR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RWKPFE
rw 		GLBLUCAST
rw 		RWKPRCVD
r 		MGKPRCVD
r 		RWKPKTEN
rw 		MGKPKTEN
rw 		PWRDWN
rw
Toggle fields

PWRDWN

Bit 0: PWRDWN.

MGKPKTEN

Bit 1: MGKPKTEN.

RWKPKTEN

Bit 2: RWKPKTEN.

MGKPRCVD

Bit 5: MGKPRCVD.

RWKPRCVD

Bit 6: RWKPRCVD.

GLBLUCAST

Bit 9: GLBLUCAST.

RWKPFE

Bit 10: RWKPFE.

RWKPTR

Bits 24-28: RWKPTR.

RWKFILTRST

Bit 31: RWKFILTRST.

MACRWKPFR

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

6/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPITE
rw 		LPITXA
rw 		PLSEN
rw 		PLS
rw 		LPIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLPIST
r 		TLPIST
r 		RLPIEX
r 		RLPIEN
r 		TLPIEX
r 		TLPIEN
r
Toggle fields

TLPIEN

Bit 0: TLPIEN.

TLPIEX

Bit 1: TLPIEX.

RLPIEN

Bit 2: RLPIEN.

RLPIEX

Bit 3: RLPIEX.

TLPIST

Bit 8: TLPIST.

RLPIST

Bit 9: RLPIST.

LPIEN

Bit 16: LPIEN.

PLS

Bit 17: PLS.

PLSEN

Bit 18: PLSEN.

LPITXA

Bit 19: LPITXA.

LPITE

Bit 20: LPITE.

MACLCSR

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

6/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPITE
rw 		LPITXA
rw 		PLSEN
rw 		PLS
rw 		LPIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RLPIST
r 		TLPIST
r 		RLPIEX
r 		RLPIEN
r 		TLPIEX
r 		TLPIEN
r
Toggle fields

TLPIEN

Bit 0: TLPIEN.

TLPIEX

Bit 1: TLPIEX.

RLPIEN

Bit 2: RLPIEN.

RLPIEX

Bit 3: RLPIEX.

TLPIST

Bit 8: TLPIST.

RLPIST

Bit 9: RLPIST.

LPIEN

Bit 16: LPIEN.

PLS

Bit 17: PLS.

PLSEN

Bit 18: PLSEN.

LPITXA

Bit 19: LPITXA.

LPITE

Bit 20: LPITE.

MACLTCR

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission.

Offset: 0xd4, size: 32, reset: 0x03E80000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TWT
rw
Toggle fields

TWT

Bits 0-15: TWT.

LST

Bits 16-25: LST.

MACLETR

The LPI Entry Timer Register is used to store the LPI Idle Timer Value in Micro-Seconds.

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPIET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPIET
rw
Toggle fields

LPIET

Bits 3-19: LPIET.

MAC1USTCR

This register controls the generation of the Reference time (1-microsecond tick) for all the LPI timers. This timer has to be programmed by the software initially.

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIC_1US_CNTR
rw
Toggle fields

TIC_1US_CNTR

Bits 0-11: TIC_1US_CNTR.

MACPHYCSR

The PHY Interface Control and Status register indicates the status signals received by the, RGMII interface from the PHY.

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

5/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FALSCARDET
r 		JABTO
r 		LNKSTS
r 		LNKSPEED
r 		LNKMOD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LUD
rw 		TC
rw
Toggle fields

TC

Bit 0: TC.

LUD

Bit 1: LUD.

LNKMOD

Bit 16: LNKMOD.

LNKSPEED

Bits 17-18: LNKSPEED.

LNKSTS

Bit 19: LNKSTS.

JABTO

Bit 20: JABTO.

FALSCARDET

Bit 21: FALSCARDET.

MACVR

The version register identifies the version of the Ethernet peripheral.

Offset: 0x110, size: 32, reset: 0x00004042, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USERVER
r 		SNPSVER
r
Toggle fields

SNPSVER

Bits 0-7: SNPSVER.

USERVER

Bits 8-15: USERVER.

MACDR

The Debug register provides the debug status of various MAC blocks.

Offset: 0x114, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFCSTS
r 		TPESTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFCFCSTS
r 		RPESTS
r
Toggle fields

RPESTS

Bit 0: RPESTS.

RFCFCSTS

Bits 1-2: RFCFCSTS.

TPESTS

Bit 16: TPESTS.

TFCSTS

Bits 17-18: TFCSTS.

MACHWF1R

This register indicates the presence of second set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Offset: 0x120, size: 32, reset: 0x11141945, access: read-only

13/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3L4FNUM
r 		HASHTBLSZ
r 		AVSEL
r 		DBGMEMA
r 		TSOEN
r 		SPHEN
r 		DCBEN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR64
r 		ADVTHWORD
r 		PTOEN
r 		OSTEN
r 		TXFIFOSIZE
r 		RXFIFOSIZE
r
Toggle fields

RXFIFOSIZE

Bits 0-4: RXFIFOSIZE.

TXFIFOSIZE

Bits 6-10: TXFIFOSIZE.

OSTEN

Bit 11: OSTEN.

PTOEN

Bit 12: PTOEN.

ADVTHWORD

Bit 13: ADVTHWORD.

ADDR64

Bits 14-15: ADDR64.

DCBEN

Bit 16: DCBEN.

SPHEN

Bit 17: SPHEN.

TSOEN

Bit 18: TSOEN.

DBGMEMA

Bit 19: DBGMEMA.

AVSEL

Bit 20: AVSEL.

HASHTBLSZ

Bits 24-25: HASHTBLSZ.

L3L4FNUM

Bits 27-30: L3L4FNUM.

MACHWF2R

This register indicates the presence of third set of the optional features or functions of the Ethernet peripheral. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Offset: 0x124, size: 32, reset: 0x41040041, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUXSNAPNUM
r 		PPSOUTNUM
r 		TXCHCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCHCNT
r 		TXQCNT
r 		RXQCNT
r
Toggle fields

RXQCNT

Bits 0-3: RXQCNT.

TXQCNT

Bits 6-9: TXQCNT.

RXCHCNT

Bits 12-15: RXCHCNT.

TXCHCNT

Bits 18-21: TXCHCNT.

PPSOUTNUM

Bits 24-26: PPSOUTNUM.

AUXSNAPNUM

Bits 28-30: AUXSNAPNUM.

MACMDIOAR

The MDIO Address register controls the management cycles to external PHY through a management interface.

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSE
rw 		BTB
rw 		PA
rw 		RDA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTC
rw 		CR
rw 		SKAP
rw 		GOC
rw 		C45E
rw 		GB
rw
Toggle fields

GB

Bit 0: GB.

C45E

Bit 1: C45E.

GOC

Bits 2-3: GOC.

SKAP

Bit 4: SKAP.

CR

Bits 8-11: CR.

NTC

Bits 12-14: NTC.

RDA

Bits 16-20: RDA.

PA

Bits 21-25: PA.

BTB

Bit 26: BTB.

PSE

Bit 27: PSE.

MACMDIODR

The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in ETH_MACMDIOAR. This register also stores the Read data from the PHY register located at the address specified by MDIO Address register.

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GD
rw
Toggle fields

GD

Bits 0-15: GD.

RA

Bits 16-31: RA.

MACA0HR

The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the GMII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211. If the MAC address registers are configured to be double-synchronized to the GMII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.

Offset: 0x300, size: 32, reset: 0x8000FFFF, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRHI
rw
Toggle fields

ADDRHI

Bits 0-15: ADDRHI.

AE

Bit 31: AE.

MACA0LR

The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.

Offset: 0x304, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRLO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRLO
rw
Toggle fields

ADDRLO

Bits 0-31: ADDRLO.

MACA1HR

The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.

Offset: 0x308, size: 32, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw 		SA
rw 		MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRHI
rw
Toggle fields

ADDRHI

Bits 0-15: ADDRHI.

MBC

Bits 24-29: MBC.

SA

Bit 30: SA.

AE

Bit 31: AE.

MACA1LR

The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.

Offset: 0x30c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRLO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRLO
rw
Toggle fields

ADDRLO

Bits 0-31: ADDRLO.

MACA2HR

The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.

Offset: 0x310, size: 32, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw 		SA
rw 		MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRHI
rw
Toggle fields

ADDRHI

Bits 0-15: ADDRHI.

MBC

Bits 24-29: MBC.

SA

Bit 30: SA.

AE

Bit 31: AE.

MACA2LR

The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.

Offset: 0x314, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRLO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRLO
rw
Toggle fields

ADDRLO

Bits 0-31: ADDRLO.

MACA3HR

The MAC Address x High register holds the upper 16 bits of the second 6-byte MAC address of the station.

Offset: 0x318, size: 32, reset: 0x0000FFFF, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AE
rw 		SA
rw 		MBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRHI
rw
Toggle fields

ADDRHI

Bits 0-15: ADDRHI.

MBC

Bits 24-29: MBC.

SA

Bit 30: SA.

AE

Bit 31: AE.

MACA3LR

The MAC Address x Low register holds the lower 32 bits of the 6-byte first MAC address of the station.

Offset: 0x31c, size: 32, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRLO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRLO
rw
Toggle fields

ADDRLO

Bits 0-31: ADDRLO.

MMC_CONTROL

This register configures the MMC operating mode.

Offset: 0x700, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCDBC
rw 		CNTPRSTLVL
rw 		CNTPRST
rw 		CNTFREEZ
rw 		RSTONRD
rw 		CNTSTOPRO
rw 		CNTRST
rw
Toggle fields

CNTRST

Bit 0: CNTRST.

CNTSTOPRO

Bit 1: CNTSTOPRO.

RSTONRD

Bit 2: RSTONRD.

CNTFREEZ

Bit 3: CNTFREEZ.

CNTPRST

Bit 4: CNTPRST.

CNTPRSTLVL

Bit 5: CNTPRSTLVL.

UCDBC

Bit 8: UCDBC.

MMC_RX_INTERRUPT

This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: Receive statistic counters reach half of their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter). Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32 bit counter and 0xFFFF for 16 bit counter). When the Counter Stop Rollover is set, interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.

Offset: 0x704, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXLPITRCIS
r 		RXLPIUSCIS
r 		RXUCGPIS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXALGNERPIS
r 		RXCRCERPIS
r
Toggle fields

RXCRCERPIS

Bit 5: RXCRCERPIS.

RXALGNERPIS

Bit 6: RXALGNERPIS.

RXUCGPIS

Bit 17: RXUCGPIS.

RXLPIUSCIS

Bit 26: RXLPIUSCIS.

RXLPITRCIS

Bit 27: RXLPITRCIS.

MMC_TX_INTERRUPT

This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000 for 32 bit counter and 0x8000 for 16 bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, the interrupts are set but the counter remains at all-ones. The MMC Transmit Interrupt register is a 32 bit register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read to clear the interrupt bit.

Offset: 0x708, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXLPITRCIS
r 		TXLPIUSCIS
r 		TXGPKTIS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXMCOLGPIS
r 		TXSCOLGPIS
r
Toggle fields

TXSCOLGPIS

Bit 14: TXSCOLGPIS.

TXMCOLGPIS

Bit 15: TXMCOLGPIS.

TXGPKTIS

Bit 21: TXGPKTIS.

TXLPIUSCIS

Bit 26: TXLPIUSCIS.

TXLPITRCIS

Bit 27: TXLPITRCIS.

MMC_RX_INTERRUPT_MASK

The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of their maximum value or the maximum values.

Offset: 0x70c, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXLPITRCIM
r 		RXLPIUSCIM
rw 		RXUCGPIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXALGNERPIM
rw 		RXCRCERPIM
rw
Toggle fields

RXCRCERPIM

Bit 5: RXCRCERPIM.

RXALGNERPIM

Bit 6: RXALGNERPIM.

RXUCGPIM

Bit 17: RXUCGPIM.

RXLPIUSCIM

Bit 26: RXLPIUSCIM.

RXLPITRCIM

Bit 27: RXLPITRCIM.

MMC_TX_INTERRUPT_MASK

This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or the maximum values. This register is 32 bit wide. This register is present only when any one of the MMC Transmit Counters is selected during core configuration.

Offset: 0x710, size: 32, reset: 0x00000000, access: read-write

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXLPITRCIM
r 		TXLPIUSCIM
rw 		TXGPKTIM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXMCOLGPIM
rw 		TXSCOLGPIM
rw
Toggle fields

TXSCOLGPIM

Bit 14: TXSCOLGPIM.

TXMCOLGPIM

Bit 15: TXMCOLGPIM.

TXGPKTIM

Bit 21: TXGPKTIM.

TXLPIUSCIM

Bit 26: TXLPIUSCIM.

TXLPITRCIM

Bit 27: TXLPITRCIM.

TX_SINGLE_COLLISION_GOOD_PACKETS

This register provides the number of successfully transmitted packets by Ethernet peripheral after a single collision in the half-duplex mode.

Offset: 0x74c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXSNGLCOLG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSNGLCOLG
r
Toggle fields

TXSNGLCOLG

Bits 0-31: TXSNGLCOLG.

TX_MULTIPLE_COLLISION_GOOD_PACKETS

This register provides the number of successfully transmitted packets by Ethernet peripheral after multiple collisions in the half-duplex mode.

Offset: 0x750, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXMULTCOLG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXMULTCOLG
r
Toggle fields

TXMULTCOLG

Bits 0-31: TXMULTCOLG.

TX_PACKET_COUNT_GOOD

This register provides the number of good packets transmitted by Ethernet peripheral.

Offset: 0x768, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXPKTG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXPKTG
r
Toggle fields

TXPKTG

Bits 0-31: TXPKTG.

RX_CRC_ERROR_PACKETS

This register provides the number of packets received by Ethernet peripheral with CRC error.

Offset: 0x794, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRCERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRCERR
r
Toggle fields

RXCRCERR

Bits 0-31: RXCRCERR.

RX_ALIGNMENT_ERROR_PACKETS

This register provides the number of packets received by Ethernet peripheral with alignment (dribble) error. It is valid only in 10/100 mode.

Offset: 0x798, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXALGNERR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXALGNERR
r
Toggle fields

RXALGNERR

Bits 0-31: RXALGNERR.

RX_UNICAST_PACKETS_GOOD

This register provides the number of good unicast packets received by Ethernet peripheral.

Offset: 0x7c4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXUCASTG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXUCASTG
r
Toggle fields

RXUCASTG

Bits 0-31: RXUCASTG.

TX_LPI_USEC_CNTR

This register provides the number of microseconds Tx LPI is asserted by Ethernet peripheral.

Offset: 0x7ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXLPIUSC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXLPIUSC
r
Toggle fields

TXLPIUSC

Bits 0-31: TXLPIUSC.

TX_LPI_TRAN_CNTR

This register provides the number of times Ethernet peripheral has entered Tx LPI.

Offset: 0x7f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXLPITRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXLPITRC
r
Toggle fields

TXLPITRC

Bits 0-31: TXLPITRC.

RX_LPI_USEC_CNTR

This register provides the number of microseconds Rx LPI is sampled by Ethernet peripheral.

Offset: 0x7f4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXLPIUSC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXLPIUSC
r
Toggle fields

RXLPIUSC

Bits 0-31: RXLPIUSC.

RX_LPI_TRAN_CNTR

This register provides the number of times Ethernet peripheral has entered Rx LPI.

Offset: 0x7f8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXLPITRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXLPITRC
r
Toggle fields

RXLPITRC

Bits 0-31: RXLPITRC.

MACL3L4C0R

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.

Offset: 0x900, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L4DPIM0
rw 		L4DPM0
rw 		L4SPIM0
rw 		L4SPM0
rw 		L4PEN0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3HDBM0
rw 		L3HSBM0
rw 		L3DAIM0
rw 		L3DAM0
rw 		L3SAIM0
rw 		L3SAM0
rw 		L3PEN0
rw
Toggle fields

L3PEN0

Bit 0: L3PEN0.

L3SAM0

Bit 2: L3SAM0.

L3SAIM0

Bit 3: L3SAIM0.

L3DAM0

Bit 4: L3DAM0.

L3DAIM0

Bit 5: L3DAIM0.

L3HSBM0

Bits 6-10: L3HSBM0.

L3HDBM0

Bits 11-15: L3HDBM0.

L4PEN0

Bit 16: L4PEN0.

L4SPM0

Bit 18: L4SPM0.

L4SPIM0

Bit 19: L4SPIM0.

L4DPM0

Bit 20: L4DPM0.

L4DPIM0

Bit 21: L4DPIM0.

MACL4A0R

Layer4 address filter 0 register

Offset: 0x904, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L4DP0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L4SP0
rw
Toggle fields

L4SP0

Bits 0-15: L4SP0.

L4DP0

Bits 16-31: L4DP0.

MACL3A00R

For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Offset: 0x910, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A00
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A00
rw
Toggle fields

L3A00

Bits 0-31: L3A00.

MACL3A10R

For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

Offset: 0x914, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A10
rw
Toggle fields

L3A10

Bits 0-31: L3A10.

MACL3A20

The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.

Offset: 0x918, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A20
rw
Toggle fields

L3A20

Bits 0-31: L3A20.

MACL3A30

The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.

Offset: 0x91c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A30
rw
Toggle fields

L3A30

Bits 0-31: L3A30.

MACL3L4C1R

The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4.

Offset: 0x930, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L4DPIM1
rw 		L4DPM1
rw 		L4SPIM1
rw 		L4SPM1
rw 		L4PEN1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3HDBM1
rw 		L3HSBM1
rw 		L3DAIM1
rw 		L3DAM1
rw 		L3SAIM1
rw 		L3SAM1
rw 		L3PEN1
rw
Toggle fields

L3PEN1

Bit 0: L3PEN1.

L3SAM1

Bit 2: L3SAM1.

L3SAIM1

Bit 3: L3SAIM1.

L3DAM1

Bit 4: L3DAM1.

L3DAIM1

Bit 5: L3DAIM1.

L3HSBM1

Bits 6-10: L3HSBM1.

L3HDBM1

Bits 11-15: L3HDBM1.

L4PEN1

Bit 16: L4PEN1.

L4SPM1

Bit 18: L4SPM1.

L4SPIM1

Bit 19: L4SPIM1.

L4DPM1

Bit 20: L4DPM1.

L4DPIM1

Bit 21: L4DPIM1.

MACL4A1R

The Layer 4 Address 0 register and registers 580 through 667 are reserved (RO with default value) if Enable Layer 3 and Layer 4 Packet Filter option is not selected while configuring the core. You can configure the Layer 3 and Layer 4 Address Registers to be double-synchronized by selecting the Synchronize Layer 3 and Layer 4 Address Registers to Rx Clock Domain option while configuring the core. When you select this option, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform consecutive writes to same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

Offset: 0x934, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L4DP1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L4SP1
rw
Toggle fields

L4SP1

Bits 0-15: L4SP1.

L4DP1

Bits 16-31: L4DP1.

MACL3A01R

For IPv4 packets, the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Offset: 0x940, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A01
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A01
rw
Toggle fields

L3A01

Bits 0-31: L3A01.

MACL3A11R

For IPv4 packets, the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.

Offset: 0x944, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A11
rw
Toggle fields

L3A11

Bits 0-31: L3A11.

MACL3A21R

The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field.

Offset: 0x948, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A21
rw
Toggle fields

L3A21

Bits 0-31: L3A21.

MACL3A31R

The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets, it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field.

Offset: 0x94c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L3A31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L3A31
rw
Toggle fields

L3A31

Bits 0-31: L3A31.

MACARPAR

The ARP Address register contains the IPv4 Destination Address of the MAC.

Offset: 0xae0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARPPA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARPPA
rw
Toggle fields

ARPPA

Bits 0-31: ARPPA.

MACTSCR

This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver.

Offset: 0xb00, size: 32, reset: 0x00002000, access: read-write

1/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AV8021ASMEN
rw 		TXTSSTSM
rw 		CSC
r 		TSENMACADDR
rw 		SNAPTYPSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSMSTRENA
rw 		TSEVNTENA
rw 		TSIPV4ENA
rw 		TSIPV6ENA
rw 		TSIPENA
rw 		TSVER2ENA
rw 		TSCTRLSSR
rw 		TSENALL
rw 		TSADDREG
rw 		TSUPDT
rw 		TSINIT
rw 		TSCFUPDT
rw 		TSENA
rw
Toggle fields

TSENA

Bit 0: TSENA.

TSCFUPDT

Bit 1: TSCFUPDT.

TSINIT

Bit 2: TSINIT.

TSUPDT

Bit 3: TSUPDT.

TSADDREG

Bit 5: TSADDREG.

TSENALL

Bit 8: TSENALL.

TSCTRLSSR

Bit 9: TSCTRLSSR.

TSVER2ENA

Bit 10: TSVER2ENA.

TSIPENA

Bit 11: TSIPENA.

TSIPV6ENA

Bit 12: TSIPV6ENA.

TSIPV4ENA

Bit 13: TSIPV4ENA.

TSEVNTENA

Bit 14: TSEVNTENA.

TSMSTRENA

Bit 15: TSMSTRENA.

SNAPTYPSEL

Bits 16-17: SNAPTYPSEL.

TSENMACADDR

Bit 18: TSENMACADDR.

CSC

Bit 19: CSC.

TXTSSTSM

Bit 24: TXTSSTSM.

AV8021ASMEN

Bit 28: AV8021ASMEN.

MACSSIR

The Sub-second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in ETH_MACTSCR register, the value in this register is added to the system time every clock cycle of HCLK. In Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.

Offset: 0xb04, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSINC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SNSINC
rw
Toggle fields

SNSINC

Bits 8-15: SNSINC.

SSINC

Bits 16-23: SSINC.

MACSTSR

The System Time Seconds register, along with System Time Nanoseconds register, indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis, there is some delay from the actual time because of clock domain transfer latencies (from HCLK to CSR clock). This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.

Offset: 0xb08, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
r
Toggle fields

TSS

Bits 0-31: TSS.

MACSTNR

The System Time Nanoseconds register, along with System Time Seconds register, indicates the current value of the system time maintained by the MAC. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.

Offset: 0xb0c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSSS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSSS
r
Toggle fields

TSSS

Bits 0-30: TSSS.

MACSTSUR

The System Time Seconds Update register, along with the System Time Nanoseconds Update register, initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or TSUPDT bits in ETH_MACTSCR register. This register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input.

Offset: 0xb10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-31: TSS.

MACSTNUR

This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input.

Offset: 0xb14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDSUB
rw 		TSSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSSS
rw
Toggle fields

TSSS

Bits 0-30: TSSS.

ADDSUB

Bit 31: ADDSUB.

MACTSAR

The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the ETH_MACTSCR register). The content of this register is added to a 32-bit accumulator in every clock cycle (of HCLK) and the system time is updated whenever the accumulator overflows.

Offset: 0xb18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSAR
rw
Toggle fields

TSAR

Bits 0-31: TSAR.

MACTSSR

The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[27:25] gets cleared when the application reads this register.

Offset: 0xb20, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATSNS
r 		ATSSTM
r 		ATSSTN
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTSSIS
r 		TSTRGTERR0
r 		AUXTSTRIG
r 		TSTARGT0
r 		TSSOVF
r
Toggle fields

TSSOVF

Bit 0: TSSOVF.

TSTARGT0

Bit 1: TSTARGT0.

AUXTSTRIG

Bit 2: AUXTSTRIG.

TSTRGTERR0

Bit 3: TSTRGTERR0.

TXTSSIS

Bit 15: TXTSSIS.

ATSSTN

Bits 16-19: ATSSTN.

ATSSTM

Bit 24: ATSSTM.

ATSNS

Bits 25-29: ATSNS.

MACTxTSSNR

This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled.

Offset: 0xb30, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXTSSMIS
r 		TXTSSLO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTSSLO
r
Toggle fields

TXTSSLO

Bits 0-30: TXTSSLO.

TXTSSMIS

Bit 31: TXTSSMIS.

MACTxTSSSR

The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted.

Offset: 0xb34, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXTSSHI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTSSHI
r
Toggle fields

TXTSSHI

Bits 0-31: TXTSSHI.

MACACR

The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot.

Offset: 0xb40, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATSEN3
rw 		ATSEN2
rw 		ATSEN1
rw 		ATSEN0
rw 		ATSFC
rw
Toggle fields

ATSFC

Bit 0: ATSFC.

ATSEN0

Bit 4: ATSEN0.

ATSEN1

Bit 5: ATSEN1.

ATSEN2

Bit 6: ATSEN2.

ATSEN3

Bit 7: ATSEN3.

MACATSNR

The Auxiliary Timestamp Nanoseconds register, along with ETH_MACATSSR, gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a depth of 4 words. You can store multiple snapshots in this FIFO. Bits[29:25] in ETH_MACTSSR indicate the fill-level of the FIFO. The top of the FIFO is removed only when the last byte of MAC Register 91 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when Bits[31:24] are read and in big-endian mode, Bits[7:0] are read.

Offset: 0xb48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUXTSLO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUXTSLO
r
Toggle fields

AUXTSLO

Bits 0-30: AUXTSLO.

MACATSSR

The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register.

Offset: 0xb4c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AUXTSHI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUXTSHI
r
Toggle fields

AUXTSHI

Bits 0-31: AUXTSHI.

MACTSIACR

The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages.

Offset: 0xb50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSTIAC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSTIAC
rw
Toggle fields

OSTIAC

Bits 0-31: OSTIAC.

MACTSEACR

The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages.

Offset: 0xb54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSTEAC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSTEAC
rw
Toggle fields

OSTEAC

Bits 0-31: OSTEAC.

MACTSICNR

This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path.

Offset: 0xb58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSIC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIC
rw
Toggle fields

TSIC

Bits 0-31: TSIC.

MACTSECNR

This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path.

Offset: 0xb5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSEC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEC
rw
Toggle fields

TSEC

Bits 0-31: TSEC.

MACPPSCR

The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more Flexible PPS outputs are selected. Bits[6:4] are valid only when Flexible PPS feature is selected.

Offset: 0xb70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRGTMODSEL0
rw 		PPSEN0
rw 		PPSCTRL
rw
Toggle fields

PPSCTRL

Bits 0-3: PPSCTRL.

PPSEN0

Bit 4: PPSEN0.

TRGTMODSEL0

Bits 5-6: TRGTMODSEL0.

MACPPSTTSR

The PPS Target Time Seconds register, along with PPS Target Time Nanoseconds register, is used to schedule an interrupt event [Bit 1 of ETH_MACTSSR] when the system time exceeds the value programmed in these registers.

Offset: 0xb80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSTRH0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSTRH0
rw
Toggle fields

TSTRH0

Bits 0-31: TSTRH0.

MACPPSTTNR

The PPS Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected.

Offset: 0xb84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRGTBUSY0
rw 		TTSL0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTSL0
rw
Toggle fields

TTSL0

Bits 0-30: TTSL0.

TRGTBUSY0

Bit 31: TRGTBUSY0.

MACPPSIR

The PPS Interval register contains the number of units of sub-second increment value between the rising edges of PPS signal output (ptp_pps_o[0]).

Offset: 0xb88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPSINT0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPSINT0
rw
Toggle fields

PPSINT0

Bits 0-31: PPSINT0.

MACPPSWR

The PPS Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS signal output (ptp_pps_o).

Offset: 0xb8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PPSWIDTH0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPSWIDTH0
rw
Toggle fields

PPSWIDTH0

Bits 0-31: PPSWIDTH0.

MACPOCR

This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Offset: 0xbc0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DN
rw 		DRRDIS
rw 		APDREQTRIG
rw 		ASYNCTRIG
rw 		APDREQEN
rw 		ASYNCEN
rw 		PTOEN
rw
Toggle fields

PTOEN

Bit 0: PTOEN.

ASYNCEN

Bit 1: ASYNCEN.

APDREQEN

Bit 2: APDREQEN.

ASYNCTRIG

Bit 4: ASYNCTRIG.

APDREQTRIG

Bit 5: APDREQTRIG.

DRRDIS

Bit 6: DRRDIS.

DN

Bits 8-15: DN.

MACSPI0R

This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Offset: 0xbc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI0
rw
Toggle fields

SPI0

Bits 0-31: SPI0.

MACSPI1R

This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected.

Offset: 0xbc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPI1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI1
rw
Toggle fields

SPI1

Bits 0-31: SPI1.

MACSPI2R

This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node.

Offset: 0xbcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2
rw
Toggle fields

SPI2

Bits 0-15: SPI2.

MACLMIR

This register contains the periodic intervals for automatic PTP packet generation.

Offset: 0xbd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LMPDRI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRSYNCR
rw 		LSI
rw
Toggle fields

LSI

Bits 0-7: LSI.

DRSYNCR

Bits 8-10: DRSYNCR.

LMPDRI

Bits 24-31: LMPDRI.

ETH_MTL

0x5800ac00: ETH_MTL

46/94 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MTLOMR
0x20 MTLISR
0x100 MTLTxQ0OMR
0x104 MTLTxQ0UR
0x108 MTLTxQ0DR
0x114 MTLTxQ0ESR
0x12c MTLQ0ICSR
0x130 MTLRxQ0OMR
0x134 MTLRxQ0MPOCR
0x138 MTLRxQ0DR
0x13c MTLRxQ0CR
0x140 MTLTxQ1OMR
0x144 MTLTxQ1UR
0x148 MTLTxQ1DR
0x150 MTLTxQ1ECR
0x154 MTLTxQ1ESR
0x158 MTLTxQ1QWR
0x15c MTLTxQ1SSCR
0x160 MTLTxQ1HCR
0x164 MTLTxQ1LCR
0x16c MTLQ1ICSR
0x170 MTLRxQ1OMR
0x174 MTLRxQ1MPOCR
0x178 MTLRxQ1DR
0x17c MTLRxQ1CR
Toggle registers

MTLOMR

The Operating Mode register establishes the Transmit and Receive operating modes and commands.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTCLR
rw 		CNTPRST
rw 		SCHALG
rw 		RAA
rw 		DTXSTS
rw
Toggle fields

DTXSTS

Bit 1: DTXSTS.

RAA

Bit 2: RAA.

SCHALG

Bits 5-6: SCHALG.

CNTPRST

Bit 8: CNTPRST.

CNTCLR

Bit 9: CNTCLR.

MTLISR

The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Q1IS
r 		Q0IS
r
Toggle fields

Q0IS

Bit 0: Q0IS.

Q1IS

Bit 1: Q1IS.

MTLTxQ0OMR

Tx queue 0 operating mode Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TQS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTC
rw 		TXQEN
rw 		TSF
rw 		FTQ
rw
Toggle fields

FTQ

Bit 0: FTQ.

TSF

Bit 1: TSF.

TXQEN

Bits 2-3: TXQEN.

TTC

Bits 4-5: TTC.

TQS

Bits 16-24: TQS.

MTLTxQ0UR

Tx queue 0 underflow register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UFCNTOVF
r 		UFFRMCNT
r
Toggle fields

UFFRMCNT

Bits 0-10: UFFRMCNT.

UFCNTOVF

Bit 11: UFCNTOVF.

MTLTxQ0DR

Tx queue 0 underflow register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STXSTSF
r 		PTXQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSTSFSTS
r 		TXQSTS
r 		TWCSTS
r 		TRCSTS
r 		TXQPAUSED
r
Toggle fields

TXQPAUSED

Bit 0: TXQPAUSED.

TRCSTS

Bits 1-2: TRCSTS.

TWCSTS

Bit 3: TWCSTS.

TXQSTS

Bit 4: TXQSTS.

TXSTSFSTS

Bit 5: TXSTSFSTS.

PTXQ

Bits 16-18: PTXQ.

STXSTSF

Bits 20-22: STXSTSF.

MTLTxQ0ESR

Tx queue x ETS status Register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ABS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABS
r
Toggle fields

ABS

Bits 0-23: ABS.

MTLQ0ICSR

Queue 0 interrupt control status Register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXOIE
rw 		RXOVFIS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABPSIE
rw 		TXUIE
rw 		ABPSIS
rw 		TXUNFIS
r
Toggle fields

TXUNFIS

Bit 0: TXUNFIS.

ABPSIS

Bit 1: ABPSIS.

TXUIE

Bit 8: TXUIE.

ABPSIE

Bit 9: ABPSIE.

RXOVFIS

Bit 16: RXOVFIS.

RXOIE

Bit 24: RXOIE.

MTLRxQ0OMR

Rx queue 0 operating mode register

Offset: 0x130, size: 32, reset: 0x00700000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RQS
r 		RFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD
rw 		RFA
rw 		EHFC
rw 		DIS_TCP_EF
rw 		RSF
rw 		FEP
rw 		FUP
rw 		RTC
rw
Toggle fields

RTC

Bits 0-1: RTC.

FUP

Bit 3: FUP.

FEP

Bit 4: FEP.

RSF

Bit 5: RSF.

DIS_TCP_EF

Bit 6: DIS_TCP_EF.

EHFC

Bit 7: EHFC.

RFA

Bits 8-10: RFA.

RFD

Bits 14-16: RFD.

RQS

Bits 20-23: RQS.

MTLRxQ0MPOCR

Rx queue 0 missed packet and overflow counter register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISCNTOVF
r 		MISPKTCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVFCNTOVF
r 		OVFPKTCNT
r
Toggle fields

OVFPKTCNT

Bits 0-10: OVFPKTCNT.

OVFCNTOVF

Bit 11: OVFCNTOVF.

MISPKTCNT

Bits 16-26: MISPKTCNT.

MISCNTOVF

Bit 27: MISCNTOVF.

MTLRxQ0DR

Rx queue i debug register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRXQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXQSTS
r 		RRCSTS
r 		RWCSTS
r
Toggle fields

RWCSTS

Bit 0: RWCSTS.

RRCSTS

Bits 1-2: RRCSTS.

RXQSTS

Bits 4-5: RXQSTS.

PRXQ

Bits 16-29: PRXQ.

MTLRxQ0CR

Rx queue 0 control register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXQ_FRM_ARBIT
r 		RXQ_WEGT
r
Toggle fields

RXQ_WEGT

Bits 0-2: RXQ_WEGT.

RXQ_FRM_ARBIT

Bit 3: RXQ_FRM_ARBIT.

MTLTxQ1OMR

Tx queue 1 operating mode Register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TQS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TTC
rw 		TXQEN
rw 		TSF
rw 		FTQ
rw
Toggle fields

FTQ

Bit 0: FTQ.

TSF

Bit 1: TSF.

TXQEN

Bits 2-3: TXQEN.

TTC

Bits 4-5: TTC.

TQS

Bits 16-24: TQS.

MTLTxQ1UR

Tx queue 1 underflow register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UFCNTOVF
r 		UFFRMCNT
r
Toggle fields

UFFRMCNT

Bits 0-10: UFFRMCNT.

UFCNTOVF

Bit 11: UFCNTOVF.

MTLTxQ1DR

Tx queue 1 underflow register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STXSTSF
r 		PTXQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXSTSFSTS
r 		TXQSTS
r 		TWCSTS
r 		TRCSTS
r 		TXQPAUSED
r
Toggle fields

TXQPAUSED

Bit 0: TXQPAUSED.

TRCSTS

Bits 1-2: TRCSTS.

TWCSTS

Bit 3: TWCSTS.

TXQSTS

Bit 4: TXQSTS.

TXSTSFSTS

Bit 5: TXSTSFSTS.

PTXQ

Bits 16-18: PTXQ.

STXSTSF

Bits 20-22: STXSTSF.

MTLTxQ1ECR

The Queue ETS Control register controls the enhanced transmission selection operation.

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLC
rw 		CC
rw 		AVALG
rw
Toggle fields

AVALG

Bit 2: AVALG.

CC

Bit 3: CC.

SLC

Bits 4-6: SLC.

MTLTxQ1ESR

Tx queue x ETS status Register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ABS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABS
r
Toggle fields

ABS

Bits 0-23: ABS.

MTLTxQ1QWR

This register provides the average traffic transmitted on queue 1.

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISCQW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISCQW
rw
Toggle fields

ISCQW

Bits 0-20: ISCQW.

MTLTxQ1SSCR

The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue.

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSC
rw
Toggle fields

SSC

Bits 0-13: SSC.

MTLTxQ1HCR

The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue.

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HC
rw
Toggle fields

HC

Bits 0-28: HC.

MTLTxQ1LCR

The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue.

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LC
rw
Toggle fields

LC

Bits 0-28: LC.

MTLQ1ICSR

Queue 1 interrupt control status Register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

1/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXOIE
rw 		RXOVFIS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABPSIE
rw 		TXUIE
rw 		ABPSIS
rw 		TXUNFIS
r
Toggle fields

TXUNFIS

Bit 0: TXUNFIS.

ABPSIS

Bit 1: ABPSIS.

TXUIE

Bit 8: TXUIE.

ABPSIE

Bit 9: ABPSIE.

RXOVFIS

Bit 16: RXOVFIS.

RXOIE

Bit 24: RXOIE.

MTLRxQ1OMR

Rx queue 1 operating mode register

Offset: 0x170, size: 32, reset: 0x00700000, access: read-write

1/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RQS
r 		RFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RFD
rw 		RFA
rw 		EHFC
rw 		DIS_TCP_EF
rw 		RSF
rw 		FEP
rw 		FUP
rw 		RTC
rw
Toggle fields

RTC

Bits 0-1: RTC.

FUP

Bit 3: FUP.

FEP

Bit 4: FEP.

RSF

Bit 5: RSF.

DIS_TCP_EF

Bit 6: DIS_TCP_EF.

EHFC

Bit 7: EHFC.

RFA

Bits 8-10: RFA.

RFD

Bits 14-16: RFD.

RQS

Bits 20-23: RQS.

MTLRxQ1MPOCR

Rx queue 1 missed packet and overflow counter register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISCNTOVF
r 		MISPKTCNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVFCNTOVF
r 		OVFPKTCNT
r
Toggle fields

OVFPKTCNT

Bits 0-10: OVFPKTCNT.

OVFCNTOVF

Bit 11: OVFCNTOVF.

MISPKTCNT

Bits 16-26: MISPKTCNT.

MISCNTOVF

Bit 27: MISCNTOVF.

MTLRxQ1DR

Rx queue i debug register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRXQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXQSTS
r 		RRCSTS
r 		RWCSTS
r
Toggle fields

RWCSTS

Bit 0: RWCSTS.

RRCSTS

Bits 1-2: RRCSTS.

RXQSTS

Bits 4-5: RXQSTS.

PRXQ

Bits 16-29: PRXQ.

MTLRxQ1CR

Rx queue 1 control register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXQ_FRM_ARBIT
r 		RXQ_WEGT
r
Toggle fields

RXQ_WEGT

Bits 0-2: RXQ_WEGT.

RXQ_FRM_ARBIT

Bit 3: RXQ_FRM_ARBIT.

ETZPC

0x5c007000: ETZPC

8/204 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TZMA0_SIZE
0x4 TZMA1_SIZE
0x10 DECPROT0
0x14 DECPROT1
0x18 DECPROT2
0x1c DECPROT3
0x20 DECPROT4
0x24 DECPROT5
0x30 DECPROT_LOCK0
0x34 DECPROT_LOCK1
0x38 DECPROT_LOCK2
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IDR
0x3fc SIDR
Toggle registers

TZMA0_SIZE

ETZPC ROM secure size definition

Offset: 0x0, size: 32, reset: 0x000003FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SIZE
rw
Toggle fields

R0SIZE

Bits 0-9: R0SIZE.

LOCK

Bit 31: LOCK.

TZMA1_SIZE

ETZPC RAM secure size definition

Offset: 0x4, size: 32, reset: 0x000003FF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0SIZE
rw
Toggle fields

R0SIZE

Bits 0-9: R0SIZE.

LOCK

Bit 31: LOCK.

DECPROT0

Register reset values

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECPROT15
rw 		DECPROT14
rw 		DECPROT13
rw 		DECPROT12
rw 		DECPROT11
rw 		DECPROT10
rw 		DECPROT9
rw 		DECPROT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT7
rw 		DECPROT6
rw 		DECPROT5
rw 		DECPROT4
rw 		DECPROT3
rw 		DECPROT2
rw 		DECPROT1
rw 		DECPROT0
rw
Toggle fields

DECPROT0

Bits 0-1: DECPROT0.

DECPROT1

Bits 2-3: DECPROT1.

DECPROT2

Bits 4-5: DECPROT2.

DECPROT3

Bits 6-7: DECPROT3.

DECPROT4

Bits 8-9: DECPROT4.

DECPROT5

Bits 10-11: DECPROT5.

DECPROT6

Bits 12-13: DECPROT6.

DECPROT7

Bits 14-15: DECPROT7.

DECPROT8

Bits 16-17: DECPROT8.

DECPROT9

Bits 18-19: DECPROT9.

DECPROT10

Bits 20-21: DECPROT10.

DECPROT11

Bits 22-23: DECPROT11.

DECPROT12

Bits 24-25: DECPROT12.

DECPROT13

Bits 26-27: DECPROT13.

DECPROT14

Bits 28-29: DECPROT14.

DECPROT15

Bits 30-31: DECPROT15.

DECPROT1

Register reset values

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECPROT15
rw 		DECPROT14
rw 		DECPROT13
rw 		DECPROT12
rw 		DECPROT11
rw 		DECPROT10
rw 		DECPROT9
rw 		DECPROT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT7
rw 		DECPROT6
rw 		DECPROT5
rw 		DECPROT4
rw 		DECPROT3
rw 		DECPROT2
rw 		DECPROT1
rw 		DECPROT0
rw
Toggle fields

DECPROT0

Bits 0-1: DECPROT0.

DECPROT1

Bits 2-3: DECPROT1.

DECPROT2

Bits 4-5: DECPROT2.

DECPROT3

Bits 6-7: DECPROT3.

DECPROT4

Bits 8-9: DECPROT4.

DECPROT5

Bits 10-11: DECPROT5.

DECPROT6

Bits 12-13: DECPROT6.

DECPROT7

Bits 14-15: DECPROT7.

DECPROT8

Bits 16-17: DECPROT8.

DECPROT9

Bits 18-19: DECPROT9.

DECPROT10

Bits 20-21: DECPROT10.

DECPROT11

Bits 22-23: DECPROT11.

DECPROT12

Bits 24-25: DECPROT12.

DECPROT13

Bits 26-27: DECPROT13.

DECPROT14

Bits 28-29: DECPROT14.

DECPROT15

Bits 30-31: DECPROT15.

DECPROT2

Register reset values

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECPROT15
rw 		DECPROT14
rw 		DECPROT13
rw 		DECPROT12
rw 		DECPROT11
rw 		DECPROT10
rw 		DECPROT9
rw 		DECPROT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT7
rw 		DECPROT6
rw 		DECPROT5
rw 		DECPROT4
rw 		DECPROT3
rw 		DECPROT2
rw 		DECPROT1
rw 		DECPROT0
rw
Toggle fields

DECPROT0

Bits 0-1: DECPROT0.

DECPROT1

Bits 2-3: DECPROT1.

DECPROT2

Bits 4-5: DECPROT2.

DECPROT3

Bits 6-7: DECPROT3.

DECPROT4

Bits 8-9: DECPROT4.

DECPROT5

Bits 10-11: DECPROT5.

DECPROT6

Bits 12-13: DECPROT6.

DECPROT7

Bits 14-15: DECPROT7.

DECPROT8

Bits 16-17: DECPROT8.

DECPROT9

Bits 18-19: DECPROT9.

DECPROT10

Bits 20-21: DECPROT10.

DECPROT11

Bits 22-23: DECPROT11.

DECPROT12

Bits 24-25: DECPROT12.

DECPROT13

Bits 26-27: DECPROT13.

DECPROT14

Bits 28-29: DECPROT14.

DECPROT15

Bits 30-31: DECPROT15.

DECPROT3

Register reset values

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECPROT15
rw 		DECPROT14
rw 		DECPROT13
rw 		DECPROT12
rw 		DECPROT11
rw 		DECPROT10
rw 		DECPROT9
rw 		DECPROT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT7
rw 		DECPROT6
rw 		DECPROT5
rw 		DECPROT4
rw 		DECPROT3
rw 		DECPROT2
rw 		DECPROT1
rw 		DECPROT0
rw
Toggle fields

DECPROT0

Bits 0-1: DECPROT0.

DECPROT1

Bits 2-3: DECPROT1.

DECPROT2

Bits 4-5: DECPROT2.

DECPROT3

Bits 6-7: DECPROT3.

DECPROT4

Bits 8-9: DECPROT4.

DECPROT5

Bits 10-11: DECPROT5.

DECPROT6

Bits 12-13: DECPROT6.

DECPROT7

Bits 14-15: DECPROT7.

DECPROT8

Bits 16-17: DECPROT8.

DECPROT9

Bits 18-19: DECPROT9.

DECPROT10

Bits 20-21: DECPROT10.

DECPROT11

Bits 22-23: DECPROT11.

DECPROT12

Bits 24-25: DECPROT12.

DECPROT13

Bits 26-27: DECPROT13.

DECPROT14

Bits 28-29: DECPROT14.

DECPROT15

Bits 30-31: DECPROT15.

DECPROT4

Register reset values

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECPROT15
rw 		DECPROT14
rw 		DECPROT13
rw 		DECPROT12
rw 		DECPROT11
rw 		DECPROT10
rw 		DECPROT9
rw 		DECPROT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT7
rw 		DECPROT6
rw 		DECPROT5
rw 		DECPROT4
rw 		DECPROT3
rw 		DECPROT2
rw 		DECPROT1
rw 		DECPROT0
rw
Toggle fields

DECPROT0

Bits 0-1: DECPROT0.

DECPROT1

Bits 2-3: DECPROT1.

DECPROT2

Bits 4-5: DECPROT2.

DECPROT3

Bits 6-7: DECPROT3.

DECPROT4

Bits 8-9: DECPROT4.

DECPROT5

Bits 10-11: DECPROT5.

DECPROT6

Bits 12-13: DECPROT6.

DECPROT7

Bits 14-15: DECPROT7.

DECPROT8

Bits 16-17: DECPROT8.

DECPROT9

Bits 18-19: DECPROT9.

DECPROT10

Bits 20-21: DECPROT10.

DECPROT11

Bits 22-23: DECPROT11.

DECPROT12

Bits 24-25: DECPROT12.

DECPROT13

Bits 26-27: DECPROT13.

DECPROT14

Bits 28-29: DECPROT14.

DECPROT15

Bits 30-31: DECPROT15.

DECPROT5

Register reset values

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DECPROT15
rw 		DECPROT14
rw 		DECPROT13
rw 		DECPROT12
rw 		DECPROT11
rw 		DECPROT10
rw 		DECPROT9
rw 		DECPROT8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT7
rw 		DECPROT6
rw 		DECPROT5
rw 		DECPROT4
rw 		DECPROT3
rw 		DECPROT2
rw 		DECPROT1
rw 		DECPROT0
rw
Toggle fields

DECPROT0

Bits 0-1: DECPROT0.

DECPROT1

Bits 2-3: DECPROT1.

DECPROT2

Bits 4-5: DECPROT2.

DECPROT3

Bits 6-7: DECPROT3.

DECPROT4

Bits 8-9: DECPROT4.

DECPROT5

Bits 10-11: DECPROT5.

DECPROT6

Bits 12-13: DECPROT6.

DECPROT7

Bits 14-15: DECPROT7.

DECPROT8

Bits 16-17: DECPROT8.

DECPROT9

Bits 18-19: DECPROT9.

DECPROT10

Bits 20-21: DECPROT10.

DECPROT11

Bits 22-23: DECPROT11.

DECPROT12

Bits 24-25: DECPROT12.

DECPROT13

Bits 26-27: DECPROT13.

DECPROT14

Bits 28-29: DECPROT14.

DECPROT15

Bits 30-31: DECPROT15.

DECPROT_LOCK0

ETZPC decprot lock 0 register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK31
rw 		LOCK30
rw 		LOCK29
rw 		LOCK28
rw 		LOCK27
rw 		LOCK26
rw 		LOCK25
rw 		LOCK24
rw 		LOCK23
rw 		LOCK22
rw 		LOCK21
rw 		LOCK20
rw 		LOCK19
rw 		LOCK18
rw 		LOCK17
rw 		LOCK16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK15
rw 		LOCK14
rw 		LOCK13
rw 		LOCK12
rw 		LOCK11
rw 		LOCK10
rw 		LOCK9
rw 		LOCK8
rw 		LOCK7
rw 		LOCK6
rw 		LOCK5
rw 		LOCK4
rw 		LOCK3
rw 		LOCK2
rw 		LOCK1
rw 		LOCK0
rw
Toggle fields

LOCK0

Bit 0: LOCK0.

LOCK1

Bit 1: LOCK1.

LOCK2

Bit 2: LOCK2.

LOCK3

Bit 3: LOCK3.

LOCK4

Bit 4: LOCK4.

LOCK5

Bit 5: LOCK5.

LOCK6

Bit 6: LOCK6.

LOCK7

Bit 7: LOCK7.

LOCK8

Bit 8: LOCK8.

LOCK9

Bit 9: LOCK9.

LOCK10

Bit 10: LOCK10.

LOCK11

Bit 11: LOCK11.

LOCK12

Bit 12: LOCK12.

LOCK13

Bit 13: LOCK13.

LOCK14

Bit 14: LOCK14.

LOCK15

Bit 15: LOCK15.

LOCK16

Bit 16: LOCK16.

LOCK17

Bit 17: LOCK17.

LOCK18

Bit 18: LOCK18.

LOCK19

Bit 19: LOCK19.

LOCK20

Bit 20: LOCK20.

LOCK21

Bit 21: LOCK21.

LOCK22

Bit 22: LOCK22.

LOCK23

Bit 23: LOCK23.

LOCK24

Bit 24: LOCK24.

LOCK25

Bit 25: LOCK25.

LOCK26

Bit 26: LOCK26.

LOCK27

Bit 27: LOCK27.

LOCK28

Bit 28: LOCK28.

LOCK29

Bit 29: LOCK29.

LOCK30

Bit 30: LOCK30.

LOCK31

Bit 31: LOCK31.

DECPROT_LOCK1

ETZPC decprot lock 1 register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK31
rw 		LOCK30
rw 		LOCK29
rw 		LOCK28
rw 		LOCK27
rw 		LOCK26
rw 		LOCK25
rw 		LOCK24
rw 		LOCK23
rw 		LOCK22
rw 		LOCK21
rw 		LOCK20
rw 		LOCK19
rw 		LOCK18
rw 		LOCK17
rw 		LOCK16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK15
rw 		LOCK14
rw 		LOCK13
rw 		LOCK12
rw 		LOCK11
rw 		LOCK10
rw 		LOCK9
rw 		LOCK8
rw 		LOCK7
rw 		LOCK6
rw 		LOCK5
rw 		LOCK4
rw 		LOCK3
rw 		LOCK2
rw 		LOCK1
rw 		LOCK0
rw
Toggle fields

LOCK0

Bit 0: LOCK0.

LOCK1

Bit 1: LOCK1.

LOCK2

Bit 2: LOCK2.

LOCK3

Bit 3: LOCK3.

LOCK4

Bit 4: LOCK4.

LOCK5

Bit 5: LOCK5.

LOCK6

Bit 6: LOCK6.

LOCK7

Bit 7: LOCK7.

LOCK8

Bit 8: LOCK8.

LOCK9

Bit 9: LOCK9.

LOCK10

Bit 10: LOCK10.

LOCK11

Bit 11: LOCK11.

LOCK12

Bit 12: LOCK12.

LOCK13

Bit 13: LOCK13.

LOCK14

Bit 14: LOCK14.

LOCK15

Bit 15: LOCK15.

LOCK16

Bit 16: LOCK16.

LOCK17

Bit 17: LOCK17.

LOCK18

Bit 18: LOCK18.

LOCK19

Bit 19: LOCK19.

LOCK20

Bit 20: LOCK20.

LOCK21

Bit 21: LOCK21.

LOCK22

Bit 22: LOCK22.

LOCK23

Bit 23: LOCK23.

LOCK24

Bit 24: LOCK24.

LOCK25

Bit 25: LOCK25.

LOCK26

Bit 26: LOCK26.

LOCK27

Bit 27: LOCK27.

LOCK28

Bit 28: LOCK28.

LOCK29

Bit 29: LOCK29.

LOCK30

Bit 30: LOCK30.

LOCK31

Bit 31: LOCK31.

DECPROT_LOCK2

ETZPC decprot lock 2 register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK31
rw 		LOCK30
rw 		LOCK29
rw 		LOCK28
rw 		LOCK27
rw 		LOCK26
rw 		LOCK25
rw 		LOCK24
rw 		LOCK23
rw 		LOCK22
rw 		LOCK21
rw 		LOCK20
rw 		LOCK19
rw 		LOCK18
rw 		LOCK17
rw 		LOCK16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK15
rw 		LOCK14
rw 		LOCK13
rw 		LOCK12
rw 		LOCK11
rw 		LOCK10
rw 		LOCK9
rw 		LOCK8
rw 		LOCK7
rw 		LOCK6
rw 		LOCK5
rw 		LOCK4
rw 		LOCK3
rw 		LOCK2
rw 		LOCK1
rw 		LOCK0
rw
Toggle fields

LOCK0

Bit 0: LOCK0.

LOCK1

Bit 1: LOCK1.

LOCK2

Bit 2: LOCK2.

LOCK3

Bit 3: LOCK3.

LOCK4

Bit 4: LOCK4.

LOCK5

Bit 5: LOCK5.

LOCK6

Bit 6: LOCK6.

LOCK7

Bit 7: LOCK7.

LOCK8

Bit 8: LOCK8.

LOCK9

Bit 9: LOCK9.

LOCK10

Bit 10: LOCK10.

LOCK11

Bit 11: LOCK11.

LOCK12

Bit 12: LOCK12.

LOCK13

Bit 13: LOCK13.

LOCK14

Bit 14: LOCK14.

LOCK15

Bit 15: LOCK15.

LOCK16

Bit 16: LOCK16.

LOCK17

Bit 17: LOCK17.

LOCK18

Bit 18: LOCK18.

LOCK19

Bit 19: LOCK19.

LOCK20

Bit 20: LOCK20.

LOCK21

Bit 21: LOCK21.

LOCK22

Bit 22: LOCK22.

LOCK23

Bit 23: LOCK23.

LOCK24

Bit 24: LOCK24.

LOCK25

Bit 25: LOCK25.

LOCK26

Bit 26: LOCK26.

LOCK27

Bit 27: LOCK27.

LOCK28

Bit 28: LOCK28.

LOCK29

Bit 29: LOCK29.

LOCK30

Bit 30: LOCK30.

LOCK31

Bit 31: LOCK31.

HWCFGR

ETZPC IP HW configuration register

Offset: 0x3f0, size: 32, reset: 0x00006002, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHUNKS1N4
r 		NUM_AHB_SEC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NUM_PER_SEC
r 		NUM_TZMA
r
Toggle fields

NUM_TZMA

Bits 0-7: NUM_TZMA.

NUM_PER_SEC

Bits 8-15: NUM_PER_SEC.

NUM_AHB_SEC

Bits 16-23: NUM_AHB_SEC.

CHUNKS1N4

Bits 24-31: CHUNKS1N4.

VERR

ETZPC IP version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IDR

ETZPC IP version register

Offset: 0x3f8, size: 32, reset: 0x00100061, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

ETZPC IP version register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

EXTI

0x5000d000: EXTI

17/364 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 RTSR1
0x4 FTSR1
0x8 SWIER1
0xc RPR1
0x10 FPR1
0x14 TZENR1
0x20 RTSR2
0x24 FTSR2
0x28 SWIER2
0x2c RPR2
0x30 FPR2
0x34 TZENR2
0x40 RTSR3
0x44 FTSR3
0x48 SWIER3
0x4c RPR3
0x50 FPR3
0x54 TZENR3
0x60 EXTICR1
0x64 EXTICR2
0x68 EXTICR3
0x6c EXTICR4
0x80 IMR1
0x84 EMR1
0x90 IMR2
0x94 EMR2
0xa0 IMR3
0xa4 EMR3
0xc0 C2IMR1
0xc4 C2EMR1
0xd0 C2IMR2
0xd4 C2EMR2
0xe0 C2IMR3
0xe4 C2EMR3
0x3c0 HWCFGR13
0x3c4 HWCFGR12
0x3c8 HWCFGR11
0x3cc HWCFGR10
0x3d0 HWCFGR9
0x3d4 HWCFGR8
0x3d8 HWCFGR7
0x3dc HWCFGR6
0x3e0 HWCFGR5
0x3e4 HWCFGR4
0x3e8 HWCFGR3
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

RTSR1

Contains only register bits for configurable events.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT15
rw 		RT14
rw 		RT13
rw 		RT12
rw 		RT11
rw 		RT10
rw 		RT9
rw 		RT8
rw 		RT7
rw 		RT6
rw 		RT5
rw 		RT4
rw 		RT3
rw 		RT2
rw 		RT1
rw 		RT0
rw
Toggle fields

RT0

Bit 0: RT0.

RT1

Bit 1: RT1.

RT2

Bit 2: RT2.

RT3

Bit 3: RT3.

RT4

Bit 4: RT4.

RT5

Bit 5: RT5.

RT6

Bit 6: RT6.

RT7

Bit 7: RT7.

RT8

Bit 8: RT8.

RT9

Bit 9: RT9.

RT10

Bit 10: RT10.

RT11

Bit 11: RT11.

RT12

Bit 12: RT12.

RT13

Bit 13: RT13.

RT14

Bit 14: RT14.

RT15

Bit 15: RT15.

RT16

Bit 16: RT16.

FTSR1

Contains only register bits for configurable events.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FT16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT15
rw 		FT14
rw 		FT13
rw 		FT12
rw 		FT11
rw 		FT10
rw 		FT9
rw 		FT8
rw 		FT7
rw 		FT6
rw 		FT5
rw 		FT4
rw 		FT3
rw 		FT2
rw 		FT1
rw 		FT0
rw
Toggle fields

FT0

Bit 0: FT0.

FT1

Bit 1: FT1.

FT2

Bit 2: FT2.

FT3

Bit 3: FT3.

FT4

Bit 4: FT4.

FT5

Bit 5: FT5.

FT6

Bit 6: FT6.

FT7

Bit 7: FT7.

FT8

Bit 8: FT8.

FT9

Bit 9: FT9.

FT10

Bit 10: FT10.

FT11

Bit 11: FT11.

FT12

Bit 12: FT12.

FT13

Bit 13: FT13.

FT14

Bit 14: FT14.

FT15

Bit 15: FT15.

FT16

Bit 16: FT16.

SWIER1

Contains only register bits for configurable events.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWI16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI15
rw 		SWI14
rw 		SWI13
rw 		SWI12
rw 		SWI11
rw 		SWI10
rw 		SWI9
rw 		SWI8
rw 		SWI7
rw 		SWI6
rw 		SWI5
rw 		SWI4
rw 		SWI3
rw 		SWI2
rw 		SWI1
rw 		SWI0
rw
Toggle fields

SWI0

Bit 0: SWI0.

SWI1

Bit 1: SWI1.

SWI2

Bit 2: SWI2.

SWI3

Bit 3: SWI3.

SWI4

Bit 4: SWI4.

SWI5

Bit 5: SWI5.

SWI6

Bit 6: SWI6.

SWI7

Bit 7: SWI7.

SWI8

Bit 8: SWI8.

SWI9

Bit 9: SWI9.

SWI10

Bit 10: SWI10.

SWI11

Bit 11: SWI11.

SWI12

Bit 12: SWI12.

SWI13

Bit 13: SWI13.

SWI14

Bit 14: SWI14.

SWI15

Bit 15: SWI15.

SWI16

Bit 16: SWI16.

RPR1

Contains only register bits for configurable events.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF15
rw 		RPIF14
rw 		RPIF13
rw 		RPIF12
rw 		RPIF11
rw 		RPIF10
rw 		RPIF9
rw 		RPIF8
rw 		RPIF7
rw 		RPIF6
rw 		RPIF5
rw 		RPIF4
rw 		RPIF3
rw 		RPIF2
rw 		RPIF1
rw 		RPIF0
rw
Toggle fields

RPIF0

Bit 0: RPIF0.

RPIF1

Bit 1: RPIF1.

RPIF2

Bit 2: RPIF2.

RPIF3

Bit 3: RPIF3.

RPIF4

Bit 4: RPIF4.

RPIF5

Bit 5: RPIF5.

RPIF6

Bit 6: RPIF6.

RPIF7

Bit 7: RPIF7.

RPIF8

Bit 8: RPIF8.

RPIF9

Bit 9: RPIF9.

RPIF10

Bit 10: RPIF10.

RPIF11

Bit 11: RPIF11.

RPIF12

Bit 12: RPIF12.

RPIF13

Bit 13: RPIF13.

RPIF14

Bit 14: RPIF14.

RPIF15

Bit 15: RPIF15.

RPIF16

Bit 16: RPIF16.

FPR1

Contains only register bits for configurable events.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPIF16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF15
rw 		FPIF14
rw 		FPIF13
rw 		FPIF12
rw 		FPIF11
rw 		FPIF10
rw 		FPIF9
rw 		FPIF8
rw 		FPIF7
rw 		FPIF6
rw 		FPIF5
rw 		FPIF4
rw 		FPIF3
rw 		FPIF2
rw 		FPIF1
rw 		FPIF0
rw
Toggle fields

FPIF0

Bit 0: FPIF0.

FPIF1

Bit 1: FPIF1.

FPIF2

Bit 2: FPIF2.

FPIF3

Bit 3: FPIF3.

FPIF4

Bit 4: FPIF4.

FPIF5

Bit 5: FPIF5.

FPIF6

Bit 6: FPIF6.

FPIF7

Bit 7: FPIF7.

FPIF8

Bit 8: FPIF8.

FPIF9

Bit 9: FPIF9.

FPIF10

Bit 10: FPIF10.

FPIF11

Bit 11: FPIF11.

FPIF12

Bit 12: FPIF12.

FPIF13

Bit 13: FPIF13.

FPIF14

Bit 14: FPIF14.

FPIF15

Bit 15: FPIF15.

FPIF16

Bit 16: FPIF16.

TZENR1

This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZEN26
rw 		TZEN24
rw 		TZEN19
rw 		TZEN18
rw 		TZEN17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZEN15
rw 		TZEN14
rw 		TZEN13
rw 		TZEN12
rw 		TZEN11
rw 		TZEN10
rw 		TZEN9
rw 		TZEN8
rw 		TZEN7
rw 		TZEN6
rw 		TZEN5
rw 		TZEN4
rw 		TZEN3
rw 		TZEN2
rw 		TZEN1
rw 		TZEN0
rw
Toggle fields

TZEN0

Bit 0: TZEN0.

TZEN1

Bit 1: TZEN1.

TZEN2

Bit 2: TZEN2.

TZEN3

Bit 3: TZEN3.

TZEN4

Bit 4: TZEN4.

TZEN5

Bit 5: TZEN5.

TZEN6

Bit 6: TZEN6.

TZEN7

Bit 7: TZEN7.

TZEN8

Bit 8: TZEN8.

TZEN9

Bit 9: TZEN9.

TZEN10

Bit 10: TZEN10.

TZEN11

Bit 11: TZEN11.

TZEN12

Bit 12: TZEN12.

TZEN13

Bit 13: TZEN13.

TZEN14

Bit 14: TZEN14.

TZEN15

Bit 15: TZEN15.

TZEN17

Bit 17: TZEN17.

TZEN18

Bit 18: TZEN18.

TZEN19

Bit 19: TZEN19.

TZEN24

Bit 24: TZEN24.

TZEN26

Bit 26: TZEN26.

RTSR2

Contains only register bits for configurable events.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

Toggle fields

FTSR2

Contains only register bits for configurable events.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

Toggle fields

SWIER2

Contains only register bits for configurable events.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

Toggle fields

RPR2

Contains only register bits for configurable events.

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

Toggle fields

FPR2

Contains only register bits for configurable events.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

Toggle fields

TZENR2

This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZEN60
rw 		TZEN59
rw 		TZEN58
rw 		TZEN57
rw 		TZEN56
rw 		TZEN55
rw 		TZEN54
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZEN41
rw
Toggle fields

TZEN41

Bit 9: TZEN41.

TZEN54

Bit 22: TZEN54.

TZEN55

Bit 23: TZEN55.

TZEN56

Bit 24: TZEN56.

TZEN57

Bit 25: TZEN57.

TZEN58

Bit 26: TZEN58.

TZEN59

Bit 27: TZEN59.

TZEN60

Bit 28: TZEN60.

RTSR3

Contains only register bits for configurable events.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RT74
rw 		RT73
rw 		RT68
rw 		RT66
rw 		RT65
rw
Toggle fields

RT65

Bit 1: RT65.

RT66

Bit 2: RT66.

RT68

Bit 4: RT68.

RT73

Bit 9: RT73.

RT74

Bit 10: RT74.

FTSR3

Contains only register bits for configurable events.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FT74
rw 		FT73
rw 		FT68
rw 		FT66
rw 		FT65
rw
Toggle fields

FT65

Bit 1: FT65.

FT66

Bit 2: FT66.

FT68

Bit 4: FT68.

FT73

Bit 9: FT73.

FT74

Bit 10: FT74.

SWIER3

Contains only register bits for configurable events.

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWI74
rw 		SWI73
rw 		SWI68
rw 		SWI66
rw 		SWI65
rw
Toggle fields

SWI65

Bit 1: SWI65.

SWI66

Bit 2: SWI66.

SWI68

Bit 4: SWI68.

SWI73

Bit 9: SWI73.

SWI74

Bit 10: SWI74.

RPR3

Contains only register bits for configurable events.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPIF74
rw 		RPIF73
rw 		RPIF68
rw 		RPIF66
rw 		RPIF65
rw
Toggle fields

RPIF65

Bit 1: RPIF65.

RPIF66

Bit 2: RPIF66.

RPIF68

Bit 4: RPIF68.

RPIF73

Bit 9: RPIF73.

RPIF74

Bit 10: RPIF74.

FPR3

Contains only register bits for configurable events.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPIF74
rw 		FPIF73
rw 		FPIF68
rw 		FPIF66
rw 		FPIF65
rw
Toggle fields

FPIF65

Bit 1: FPIF65.

FPIF66

Bit 2: FPIF66.

FPIF68

Bit 4: FPIF68.

FPIF73

Bit 9: FPIF73.

FPIF74

Bit 10: FPIF74.

TZENR3

This register provides TrustZone Write access security, a non-secure write access will generate a bus error. A non-secure read will return the register data. Contains only register bits for TrustZone capable Input events.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

Toggle fields

EXTICR1

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI3
rw 		EXTI2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI1
rw 		EXTI0
rw
Toggle fields

EXTI0

Bits 0-7: EXTI0.

EXTI1

Bits 8-15: EXTI1.

EXTI2

Bits 16-23: EXTI2.

EXTI3

Bits 24-31: EXTI3.

EXTICR2

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI7
rw 		EXTI6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI5
rw 		EXTI4
rw
Toggle fields

EXTI4

Bits 0-7: EXTI4.

EXTI5

Bits 8-15: EXTI5.

EXTI6

Bits 16-23: EXTI6.

EXTI7

Bits 24-31: EXTI7.

EXTICR3

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI11
rw 		EXTI10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI9
rw 		EXTI8
rw
Toggle fields

EXTI8

Bits 0-7: EXTI8.

EXTI9

Bits 8-15: EXTI9.

EXTI10

Bits 16-23: EXTI10.

EXTI11

Bits 24-31: EXTI11.

EXTICR4

EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXTI15
rw 		EXTI14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI13
rw 		EXTI12
rw
Toggle fields

EXTI12

Bits 0-7: EXTI12.

EXTI13

Bits 8-15: EXTI13.

EXTI14

Bits 16-23: EXTI14.

EXTI15

Bits 24-31: EXTI15.

IMR1

Contains register bits for configurable events and Direct events.

Offset: 0x80, size: 32, reset: 0xFFFE0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw 		IM30
rw 		IM29
rw 		IM28
rw 		IM27
rw 		IM26
rw 		IM25
rw 		IM24
rw 		IM23
rw 		IM22
rw 		IM21
rw 		IM20
rw 		IM19
rw 		IM18
rw 		IM17
rw 		IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw 		IM14
rw 		IM13
rw 		IM12
rw 		IM11
rw 		IM10
rw 		IM9
rw 		IM8
rw 		IM7
rw 		IM6
rw 		IM5
rw 		IM4
rw 		IM3
rw 		IM2
rw 		IM1
rw 		IM0
rw
Toggle fields

IM0

Bit 0: IM0.

IM1

Bit 1: IM1.

IM2

Bit 2: IM2.

IM3

Bit 3: IM3.

IM4

Bit 4: IM4.

IM5

Bit 5: IM5.

IM6

Bit 6: IM6.

IM7

Bit 7: IM7.

IM8

Bit 8: IM8.

IM9

Bit 9: IM9.

IM10

Bit 10: IM10.

IM11

Bit 11: IM11.

IM12

Bit 12: IM12.

IM13

Bit 13: IM13.

IM14

Bit 14: IM14.

IM15

Bit 15: IM15.

IM16

Bit 16: IM16.

IM17

Bit 17: IM17.

IM18

Bit 18: IM18.

IM19

Bit 19: IM19.

IM20

Bit 20: IM20.

IM21

Bit 21: IM21.

IM22

Bit 22: IM22.

IM23

Bit 23: IM23.

IM24

Bit 24: IM24.

IM25

Bit 25: IM25.

IM26

Bit 26: IM26.

IM27

Bit 27: IM27.

IM28

Bit 28: IM28.

IM29

Bit 29: IM29.

IM30

Bit 30: IM30.

IM31

Bit 31: IM31.

EMR1

EXTI CPU wakeup with event mask register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM19
rw 		EM18
rw 		EM17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle fields

EM0

Bit 0: EM0.

EM1

Bit 1: EM1.

EM2

Bit 2: EM2.

EM3

Bit 3: EM3.

EM4

Bit 4: EM4.

EM5

Bit 5: EM5.

EM6

Bit 6: EM6.

EM7

Bit 7: EM7.

EM8

Bit 8: EM8.

EM9

Bit 9: EM9.

EM10

Bit 10: EM10.

EM11

Bit 11: EM11.

EM12

Bit 12: EM12.

EM13

Bit 13: EM13.

EM14

Bit 14: EM14.

EM15

Bit 15: EM15.

EM17

Bit 17: EM17.

EM18

Bit 18: EM18.

EM19

Bit 19: EM19.

IMR2

Contains register bits for configurable events and direct events.

Offset: 0x90, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM63
rw 		IM62
rw 		IM61
rw 		IM60
rw 		IM59
rw 		IM58
rw 		IM57
rw 		IM56
rw 		IM55
rw 		IM54
rw 		IM53
rw 		IM52
rw 		IM51
rw 		IM50
rw 		IM49
rw 		IM48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM47
rw 		IM46
rw 		IM45
rw 		IM44
rw 		IM43
rw 		IM42
rw 		IM41
rw 		IM40
rw 		IM39
rw 		IM38
rw 		IM37
rw 		IM36
rw 		IM35
rw 		IM34
rw 		IM33
rw 		IM32
rw
Toggle fields

IM32

Bit 0: IM32.

IM33

Bit 1: IM33.

IM34

Bit 2: IM34.

IM35

Bit 3: IM35.

IM36

Bit 4: IM36.

IM37

Bit 5: IM37.

IM38

Bit 6: IM38.

IM39

Bit 7: IM39.

IM40

Bit 8: IM40.

IM41

Bit 9: IM41.

IM42

Bit 10: IM42.

IM43

Bit 11: IM43.

IM44

Bit 12: IM44.

IM45

Bit 13: IM45.

IM46

Bit 14: IM46.

IM47

Bit 15: IM47.

IM48

Bit 16: IM48.

IM49

Bit 17: IM49.

IM50

Bit 18: IM50.

IM51

Bit 19: IM51.

IM52

Bit 20: IM52.

IM53

Bit 21: IM53.

IM54

Bit 22: IM54.

IM55

Bit 23: IM55.

IM56

Bit 24: IM56.

IM57

Bit 25: IM57.

IM58

Bit 26: IM58.

IM59

Bit 27: IM59.

IM60

Bit 28: IM60.

IM61

Bit 29: IM61.

IM62

Bit 30: IM62.

IM63

Bit 31: IM63.

EMR2

EXTI CPU wakeup with event mask register

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IMR3

Contains register bits for configurable events and direct events.

Offset: 0xa0, size: 32, reset: 0x00000DE9, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM75
rw 		IM74
rw 		IM73
rw 		IM72
rw 		IM71
rw 		IM70
rw 		IM69
rw 		IM68
rw 		IM67
rw 		IM66
rw 		IM65
rw 		IM64
rw
Toggle fields

IM64

Bit 0: IM64.

IM65

Bit 1: IM65.

IM66

Bit 2: IM66.

IM67

Bit 3: IM67.

IM68

Bit 4: IM68.

IM69

Bit 5: IM69.

IM70

Bit 6: IM70.

IM71

Bit 7: IM71.

IM72

Bit 8: IM72.

IM73

Bit 9: IM73.

IM74

Bit 10: IM74.

IM75

Bit 11: IM75.

EMR3

EXTI CPU wakeup with event mask register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM66
rw
Toggle fields

EM66

Bit 2: EM66.

C2IMR1

Contains register bits for configurable events and Direct events.

Offset: 0xc0, size: 32, reset: 0xFFFE0000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM31
rw 		IM30
rw 		IM29
rw 		IM28
rw 		IM27
rw 		IM26
rw 		IM25
rw 		IM24
rw 		IM23
rw 		IM22
rw 		IM21
rw 		IM20
rw 		IM19
rw 		IM18
rw 		IM17
rw 		IM16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM15
rw 		IM14
rw 		IM13
rw 		IM12
rw 		IM11
rw 		IM10
rw 		IM9
rw 		IM8
rw 		IM7
rw 		IM6
rw 		IM5
rw 		IM4
rw 		IM3
rw 		IM2
rw 		IM1
rw 		IM0
rw
Toggle fields

IM0

Bit 0: IM0.

IM1

Bit 1: IM1.

IM2

Bit 2: IM2.

IM3

Bit 3: IM3.

IM4

Bit 4: IM4.

IM5

Bit 5: IM5.

IM6

Bit 6: IM6.

IM7

Bit 7: IM7.

IM8

Bit 8: IM8.

IM9

Bit 9: IM9.

IM10

Bit 10: IM10.

IM11

Bit 11: IM11.

IM12

Bit 12: IM12.

IM13

Bit 13: IM13.

IM14

Bit 14: IM14.

IM15

Bit 15: IM15.

IM16

Bit 16: IM16.

IM17

Bit 17: IM17.

IM18

Bit 18: IM18.

IM19

Bit 19: IM19.

IM20

Bit 20: IM20.

IM21

Bit 21: IM21.

IM22

Bit 22: IM22.

IM23

Bit 23: IM23.

IM24

Bit 24: IM24.

IM25

Bit 25: IM25.

IM26

Bit 26: IM26.

IM27

Bit 27: IM27.

IM28

Bit 28: IM28.

IM29

Bit 29: IM29.

IM30

Bit 30: IM30.

IM31

Bit 31: IM31.

C2EMR1

EXTI CPU2 wakeup with event mask register

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EM19
rw 		EM18
rw 		EM17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM15
rw 		EM14
rw 		EM13
rw 		EM12
rw 		EM11
rw 		EM10
rw 		EM9
rw 		EM8
rw 		EM7
rw 		EM6
rw 		EM5
rw 		EM4
rw 		EM3
rw 		EM2
rw 		EM1
rw 		EM0
rw
Toggle fields

EM0

Bit 0: EM0.

EM1

Bit 1: EM1.

EM2

Bit 2: EM2.

EM3

Bit 3: EM3.

EM4

Bit 4: EM4.

EM5

Bit 5: EM5.

EM6

Bit 6: EM6.

EM7

Bit 7: EM7.

EM8

Bit 8: EM8.

EM9

Bit 9: EM9.

EM10

Bit 10: EM10.

EM11

Bit 11: EM11.

EM12

Bit 12: EM12.

EM13

Bit 13: EM13.

EM14

Bit 14: EM14.

EM15

Bit 15: EM15.

EM17

Bit 17: EM17.

EM18

Bit 18: EM18.

EM19

Bit 19: EM19.

C2IMR2

Contains register bits for configurable events and direct events.

Offset: 0xd0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM63
rw 		IM62
rw 		IM61
rw 		IM60
rw 		IM59
rw 		IM58
rw 		IM57
rw 		IM56
rw 		IM55
rw 		IM54
rw 		IM53
rw 		IM52
rw 		IM51
rw 		IM50
rw 		IM49
rw 		IM48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM47
rw 		IM46
rw 		IM45
rw 		IM44
rw 		IM43
rw 		IM42
rw 		IM41
rw 		IM40
rw 		IM39
rw 		IM38
rw 		IM37
rw 		IM36
rw 		IM35
rw 		IM34
rw 		IM33
rw 		IM32
rw
Toggle fields

IM32

Bit 0: IM32.

IM33

Bit 1: IM33.

IM34

Bit 2: IM34.

IM35

Bit 3: IM35.

IM36

Bit 4: IM36.

IM37

Bit 5: IM37.

IM38

Bit 6: IM38.

IM39

Bit 7: IM39.

IM40

Bit 8: IM40.

IM41

Bit 9: IM41.

IM42

Bit 10: IM42.

IM43

Bit 11: IM43.

IM44

Bit 12: IM44.

IM45

Bit 13: IM45.

IM46

Bit 14: IM46.

IM47

Bit 15: IM47.

IM48

Bit 16: IM48.

IM49

Bit 17: IM49.

IM50

Bit 18: IM50.

IM51

Bit 19: IM51.

IM52

Bit 20: IM52.

IM53

Bit 21: IM53.

IM54

Bit 22: IM54.

IM55

Bit 23: IM55.

IM56

Bit 24: IM56.

IM57

Bit 25: IM57.

IM58

Bit 26: IM58.

IM59

Bit 27: IM59.

IM60

Bit 28: IM60.

IM61

Bit 29: IM61.

IM62

Bit 30: IM62.

IM63

Bit 31: IM63.

C2EMR2

EXTI CPU2 wakeup with event mask register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

Toggle fields

C2IMR3

Contains register bits for configurable events and direct events.

Offset: 0xe0, size: 32, reset: 0x00000DE9, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IM75
rw 		IM74
rw 		IM73
rw 		IM72
rw 		IM71
rw 		IM70
rw 		IM69
rw 		IM68
rw 		IM67
rw 		IM66
rw 		IM65
rw 		IM64
rw
Toggle fields

IM64

Bit 0: IM64.

IM65

Bit 1: IM65.

IM66

Bit 2: IM66.

IM67

Bit 3: IM67.

IM68

Bit 4: IM68.

IM69

Bit 5: IM69.

IM70

Bit 6: IM70.

IM71

Bit 7: IM71.

IM72

Bit 8: IM72.

IM73

Bit 9: IM73.

IM74

Bit 10: IM74.

IM75

Bit 11: IM75.

C2EMR3

EXTI CPU2 wakeup with event mask register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EM66
rw
Toggle fields

EM66

Bit 2: EM66.

HWCFGR13

EXTI hardware configuration register 13

Offset: 0x3c0, size: 32, reset: 0x050EFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZ
r
Toggle fields

TZ

Bits 0-31: TZ.

HWCFGR12

EXTI hardware configuration register 12

Offset: 0x3c4, size: 32, reset: 0x050EFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZ
r
Toggle fields

TZ

Bits 0-31: TZ.

HWCFGR11

EXTI hardware configuration register 11

Offset: 0x3c8, size: 32, reset: 0x050EFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TZ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZ
r
Toggle fields

TZ

Bits 0-31: TZ.

HWCFGR10

EXTI hardware configuration register 10

Offset: 0x3cc, size: 32, reset: 0x00000000, access: read-only

Toggle fields

HWCFGR9

EXTI hardware configuration register 9

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

Toggle fields

HWCFGR8

EXTI hardware configuration register 8

Offset: 0x3d4, size: 32, reset: 0x00000000, access: read-only

Toggle fields

HWCFGR7

EXTI hardware configuration register 7

Offset: 0x3d8, size: 32, reset: 0x000EFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPUEVENT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUEVENT
r
Toggle fields

CPUEVENT

Bits 0-31: CPUEVENT.

HWCFGR6

EXTI hardware configuration register 6

Offset: 0x3dc, size: 32, reset: 0x000EFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPUEVENT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUEVENT
r
Toggle fields

CPUEVENT

Bits 0-31: CPUEVENT.

HWCFGR5

EXTI hardware configuration register 5

Offset: 0x3e0, size: 32, reset: 0x000EFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPUEVENT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUEVENT
r
Toggle fields

CPUEVENT

Bits 0-31: CPUEVENT.

HWCFGR4

EXTI hardware configuration register 4

Offset: 0x3e4, size: 32, reset: 0x0001FFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVENT_TRG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVENT_TRG
r
Toggle fields

EVENT_TRG

Bits 0-31: EVENT_TRG.

HWCFGR3

EXTI hardware configuration register 3

Offset: 0x3e8, size: 32, reset: 0x0001FFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVENT_TRG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVENT_TRG
r
Toggle fields

EVENT_TRG

Bits 0-31: EVENT_TRG.

HWCFGR2

EXTI hardware configuration register 2

Offset: 0x3ec, size: 32, reset: 0x0001FFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVENT_TRG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVENT_TRG
r
Toggle fields

EVENT_TRG

Bits 0-31: EVENT_TRG.

HWCFGR1

EXTI hardware configuration register 1

Offset: 0x3f0, size: 32, reset: 0x000B214B, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NBIOPORT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUEVTEN
r 		NBCPUS
r 		NBEVENTS
r
Toggle fields

NBEVENTS

Bits 0-7: NBEVENTS.

NBCPUS

Bits 8-11: NBCPUS.

CPUEVTEN

Bits 12-15: CPUEVTEN.

NBIOPORT

Bits 16-23: NBIOPORT.

VERR

EXTI IP version register

Offset: 0x3f4, size: 32, reset: 0x00000030, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

EXTI identification register

Offset: 0x3f8, size: 32, reset: 0x000E0001, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IPID.

SIDR

EXTI size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

FDCAN1

0x4400e000: FDCAN1

69/396 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 ENDN
0xc DBTP
0x10 TEST
0x14 RWD
0x18 CCCR
0x1c NBTP
0x20 TSCC
0x24 TSCV
0x28 TOCC
0x2c TOCV
0x40 ECR
0x44 PSR
0x48 TDCR
0x50 IR
0x54 IE
0x58 ILS
0x5c ILE
0x80 GFC
0x84 SIDFC
0x88 XIDFC
0x90 XIDAM
0x94 HPMS
0x98 NDAT1
0x9c NDAT2
0xa0 RXF0C
0xa4 RXF0S
0xa8 RXF0A
0xac RXBC
0xb0 RXF1C
0xb4 RXF1S
0xb8 RXF1A
0xbc RXESC
0xc0 TXBC
0xc4 TXFQS
0xc8 TXESC
0xd0 TXBAR
0xd4 TXBCR
0xd8 TXBTO
0xdc TXBCF
0xe0 TXBTIE
0xe4 TXBCIE
0xf0 TXEFC
0xf4 TXEFS
0xf8 TXEFA
0x100 TTTMC
0x104 TTRMC
0x108 TTOCF
0x10c TTMLM
0x110 TURCF
0x114 TTOCN
0x118 TTGTP
0x11c TTTMK
0x120 TTIR
0x124 TTIE
0x128 TTILS
0x12c TTOST
0x130 TURNA
0x134 TTLGT
0x138 TTCTC
0x13c TTCPT
0x140 TTCSM
0x300 TTTS
Toggle registers

CREL

FDCAN core release register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r 		STEP
r 		SUBSTEP
r 		YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r 		DAY
r
Toggle fields

DAY

Bits 0-7: DAY.

MON

Bits 8-15: MON.

YEAR

Bits 16-19: YEAR.

SUBSTEP

Bits 20-23: SUBSTEP.

STEP

Bits 24-27: STEP.

REL

Bits 28-31: REL.

ENDN

FDCAN Endian register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: ETV.

DBTP

This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw 		DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw 		DTSEG2
rw 		DSJW
rw
Toggle fields

DSJW

Bits 0-3: DSJW.

DTSEG2

Bits 4-7: DTSEG2.

DTSEG1

Bits 8-12: DTSEG1.

DBRP

Bits 16-20: DBRP.

TDC

Bit 23: TDC.

TEST

Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		TX
rw 		LBCK
rw
Toggle fields

LBCK

Bit 4: LBCK.

TX

Bits 5-6: TX.

RX

Bit 7: RX.

RWD

The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock.

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r 		WDC
rw
Toggle fields

WDC

Bits 0-7: WDC.

WDV

Bits 8-15: WDV.

CCCR

For details about setting and resetting of single bits see Software initialization.

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

1/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw 		TXP
rw 		EFBI
rw 		PXHD
rw 		BRSE
rw 		FDOE
rw 		TEST
rw 		DAR
rw 		MON
rw 		CSR
rw 		CSA
r 		ASM
rw 		CCE
rw 		INIT
rw
Toggle fields

INIT

Bit 0: INIT.

CCE

Bit 1: CCE.

ASM

Bit 2: ASM.

CSA

Bit 3: CSA.

CSR

Bit 4: CSR.

MON

Bit 5: MON.

DAR

Bit 6: DAR.

TEST

Bit 7: TEST.

FDOE

Bit 8: FDOE.

BRSE

Bit 9: BRSE.

PXHD

Bit 12: PXHD.

EFBI

Bit 13: EFBI.

TXP

Bit 14: TXP.

NISO

Bit 15: NISO.

NBTP

This register is dedicated to the nominal bit timing used during the arbitration phase.

Offset: 0x1c, size: 32, reset: 0x00000A33, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw 		NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw 		NTSEG2
rw
Toggle fields

NTSEG2

Bits 0-6: NTSEG2.

NTSEG1

Bits 8-15: NTSEG1.

NBRP

Bits 16-24: NBRP.

NSJW

Bits 25-31: NSJW.

TSCC

FDCAN timestamp counter configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: TSS.

TCP

Bits 16-19: TCP.

TSCV

FDCAN timestamp counter value register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: TSC.

TOCC

FDCAN timeout counter configuration register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw 		ETOC
rw
Toggle fields

ETOC

Bit 0: ETOC.

TOS

Bits 1-2: TOS.

TOP

Bits 16-31: TOP.

TOCV

FDCAN timeout counter value register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: TOC.

ECR

FDCAN error counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
r 		TREC
r 		TEC
r
Toggle fields

TEC

Bits 0-7: TEC.

TREC

Bits 8-14: TREC.

RP

Bit 15: RP.

CEL

Bits 16-23: CEL.

PSR

FDCAN protocol status register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

7/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw 		REDL
rw 		RBRS
rw 		RESI
rw 		DLEC
r 		BO
r 		EW
r 		EP
r 		ACT
r 		LEC
r
Toggle fields

LEC

Bits 0-2: LEC.

ACT

Bits 3-4: ACT.

EP

Bit 5: EP.

EW

Bit 6: EW.

BO

Bit 7: BO.

DLEC

Bits 8-10: DLEC.

RESI

Bit 11: RESI.

RBRS

Bit 12: RBRS.

REDL

Bit 13: REDL.

PXE

Bit 14: PXE.

TDCV

Bits 16-22: TDCV.

TDCR

FDCAN transmitter delay compensation register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw 		TDCF
rw
Toggle fields

TDCF

Bits 0-6: TDCF.

TDCO

Bits 8-14: TDCO.

IR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw 		PED
rw 		PEA
rw 		WDI
rw 		BO
rw 		EW
rw 		EP
rw 		ELO
rw 		DRX
rw 		TOO
rw 		MRAF
rw 		TSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFL
rw 		TEFF
rw 		TEFW
rw 		TEFN
rw 		TFE
rw 		TCF
rw 		TC
rw 		HPM
rw 		RF1L
rw 		RF1F
rw 		RF1W
rw 		RF1N
rw 		RF0L
rw 		RF0F
rw 		RF0W
rw 		RF0N
rw
Toggle fields

RF0N

Bit 0: RF0N.

RF0W

Bit 1: RF0W.

RF0F

Bit 2: RF0F.

RF0L

Bit 3: RF0L.

RF1N

Bit 4: RF1N.

RF1W

Bit 5: RF1W.

RF1F

Bit 6: RF1F.

RF1L

Bit 7: RF1L.

HPM

Bit 8: HPM.

TC

Bit 9: TC.

TCF

Bit 10: TCF.

TFE

Bit 11: TFE.

TEFN

Bit 12: TEFN.

TEFW

Bit 13: TEFW.

TEFF

Bit 14: TEFF.

TEFL

Bit 15: TEFL.

TSW

Bit 16: TSW.

MRAF

Bit 17: MRAF.

TOO

Bit 18: TOO.

DRX

Bit 19: DRX.

ELO

Bit 22: ELO.

EP

Bit 23: EP.

EW

Bit 24: EW.

BO

Bit 25: BO.

WDI

Bit 26: WDI.

PEA

Bit 27: PEA.

PED

Bit 28: PED.

ARA

Bit 29: ARA.

IE

The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw 		PEDE
rw 		PEAE
rw 		WDIE
rw 		BOE
rw 		EWE
rw 		EPE
rw 		ELOE
rw 		BEUE
rw 		BECE
rw 		DRXE
rw 		TOOE
rw 		MRAFE
rw 		TSWE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLE
rw 		TEFFE
rw 		TEFWE
rw 		TEFNE
rw 		TFEE
rw 		TCFE
rw 		TCE
rw 		HPME
rw 		RF1LE
rw 		RF1FE
rw 		RF1WE
rw 		RF1NE
rw 		RF0LE
rw 		RF0FE
rw 		RF0WE
rw 		RF0NE
rw
Toggle fields

RF0NE

Bit 0: RF0NE.

RF0WE

Bit 1: RF0WE.

RF0FE

Bit 2: RF0FE.

RF0LE

Bit 3: RF0LE.

RF1NE

Bit 4: RF1NE.

RF1WE

Bit 5: RF1WE.

RF1FE

Bit 6: RF1FE.

RF1LE

Bit 7: RF1LE.

HPME

Bit 8: HPME.

TCE

Bit 9: TCE.

TCFE

Bit 10: TCFE.

TFEE

Bit 11: TFEE.

TEFNE

Bit 12: TEFNE.

TEFWE

Bit 13: TEFWE.

TEFFE

Bit 14: TEFFE.

TEFLE

Bit 15: TEFLE.

TSWE

Bit 16: TSWE.

MRAFE

Bit 17: MRAFE.

TOOE

Bit 18: TOOE.

DRXE

Bit 19: DRXE.

BECE

Bit 20: BECE.

BEUE

Bit 21: BEUE.

ELOE

Bit 22: ELOE.

EPE

Bit 23: EPE.

EWE

Bit 24: EWE.

BOE

Bit 25: BOE.

WDIE

Bit 26: WDIE.

PEAE

Bit 27: PEAE.

PEDE

Bit 28: PEDE.

ARAE

Bit 29: ARAE.

ILS

This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAL
rw 		PEDL
rw 		PEAL
rw 		WDIL
rw 		BOL
rw 		EWL
rw 		EPL
rw 		ELOL
rw 		BEUL
rw 		BECL
rw 		DRXL
rw 		TOOL
rw 		MRAFL
rw 		TSWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLL
rw 		TEFFL
rw 		TEFWL
rw 		TEFNL
rw 		TFEL
rw 		TCFL
rw 		TCL
rw 		HPML
rw 		RF1LL
rw 		RF1FL
rw 		RF1WL
rw 		RF1NL
rw 		RF0LL
rw 		RF0FL
rw 		RF0WL
rw 		RF0NL
rw
Toggle fields

RF0NL

Bit 0: RF0NL.

RF0WL

Bit 1: RF0WL.

RF0FL

Bit 2: RF0FL.

RF0LL

Bit 3: RF0LL.

RF1NL

Bit 4: RF1NL.

RF1WL

Bit 5: RF1WL.

RF1FL

Bit 6: RF1FL.

RF1LL

Bit 7: RF1LL.

HPML

Bit 8: HPML.

TCL

Bit 9: TCL.

TCFL

Bit 10: TCFL.

TFEL

Bit 11: TFEL.

TEFNL

Bit 12: TEFNL.

TEFWL

Bit 13: TEFWL.

TEFFL

Bit 14: TEFFL.

TEFLL

Bit 15: TEFLL.

TSWL

Bit 16: TSWL.

MRAFL

Bit 17: MRAFL.

TOOL

Bit 18: TOOL.

DRXL

Bit 19: DRXL.

BECL

Bit 20: BECL.

BEUL

Bit 21: BEUL.

ELOL

Bit 22: ELOL.

EPL

Bit 23: EPL.

EWL

Bit 24: EWL.

BOL

Bit 25: BOL.

WDIL

Bit 26: WDIL.

PEAL

Bit 27: PEAL.

PEDL

Bit 28: PEDL.

ARAL

Bit 29: ARAL.

ILE

Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw 		EINT0
rw
Toggle fields

EINT0

Bit 0: EINT0.

EINT1

Bit 1: EINT1.

GFC

Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANFS
rw 		ANFE
rw 		RRFS
rw 		RRFE
rw
Toggle fields

RRFE

Bit 0: RRFE.

RRFS

Bit 1: RRFS.

ANFE

Bits 2-3: ANFE.

ANFS

Bits 4-5: ANFS.

SIDFC

Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLSSA
rw
Toggle fields

FLSSA

Bits 2-15: FLSSA.

LSS

Bits 16-23: LSS.

XIDFC

Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLESA
rw
Toggle fields

FLESA

Bits 2-15: FLESA.

LSE

Bits 16-23: LSE.

XIDAM

FDCAN extended ID and mask register

Offset: 0x90, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: EIDM.

HPMS

This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r 		FIDX
r 		MSI
r 		BIDX
r
Toggle fields

BIDX

Bits 0-5: BIDX.

MSI

Bits 6-7: MSI.

FIDX

Bits 8-14: FIDX.

FLST

Bit 15: FLST.

NDAT1

FDCAN new data 1 register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND31
rw 		ND30
rw 		ND29
rw 		ND28
rw 		ND27
rw 		ND26
rw 		ND25
rw 		ND24
rw 		ND23
rw 		ND22
rw 		ND21
rw 		ND20
rw 		ND19
rw 		ND18
rw 		ND17
rw 		ND16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND15
rw 		ND14
rw 		ND13
rw 		ND12
rw 		ND11
rw 		ND10
rw 		ND9
rw 		ND8
rw 		ND7
rw 		ND6
rw 		ND5
rw 		ND4
rw 		ND3
rw 		ND2
rw 		ND1
rw 		ND0
rw
Toggle fields

ND0

Bit 0: ND0.

ND1

Bit 1: ND1.

ND2

Bit 2: ND2.

ND3

Bit 3: ND3.

ND4

Bit 4: ND4.

ND5

Bit 5: ND5.

ND6

Bit 6: ND6.

ND7

Bit 7: ND7.

ND8

Bit 8: ND8.

ND9

Bit 9: ND9.

ND10

Bit 10: ND10.

ND11

Bit 11: ND11.

ND12

Bit 12: ND12.

ND13

Bit 13: ND13.

ND14

Bit 14: ND14.

ND15

Bit 15: ND15.

ND16

Bit 16: ND16.

ND17

Bit 17: ND17.

ND18

Bit 18: ND18.

ND19

Bit 19: ND19.

ND20

Bit 20: ND20.

ND21

Bit 21: ND21.

ND22

Bit 22: ND22.

ND23

Bit 23: ND23.

ND24

Bit 24: ND24.

ND25

Bit 25: ND25.

ND26

Bit 26: ND26.

ND27

Bit 27: ND27.

ND28

Bit 28: ND28.

ND29

Bit 29: ND29.

ND30

Bit 30: ND30.

ND31

Bit 31: ND31.

NDAT2

FDCAN new data 2 register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND63
rw 		ND62
rw 		ND61
rw 		ND60
rw 		ND59
rw 		ND58
rw 		ND57
rw 		ND56
rw 		ND55
rw 		ND54
rw 		ND53
rw 		ND52
rw 		ND51
rw 		ND50
rw 		ND49
rw 		ND48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND47
rw 		ND46
rw 		ND45
rw 		ND44
rw 		ND43
rw 		ND42
rw 		ND41
rw 		ND40
rw 		ND39
rw 		ND38
rw 		ND37
rw 		ND36
rw 		ND35
rw 		ND34
rw 		ND33
rw 		ND32
rw
Toggle fields

ND32

Bit 0: ND32.

ND33

Bit 1: ND33.

ND34

Bit 2: ND34.

ND35

Bit 3: ND35.

ND36

Bit 4: ND36.

ND37

Bit 5: ND37.

ND38

Bit 6: ND38.

ND39

Bit 7: ND39.

ND40

Bit 8: ND40.

ND41

Bit 9: ND41.

ND42

Bit 10: ND42.

ND43

Bit 11: ND43.

ND44

Bit 12: ND44.

ND45

Bit 13: ND45.

ND46

Bit 14: ND46.

ND47

Bit 15: ND47.

ND48

Bit 16: ND48.

ND49

Bit 17: ND49.

ND50

Bit 18: ND50.

ND51

Bit 19: ND51.

ND52

Bit 20: ND52.

ND53

Bit 21: ND53.

ND54

Bit 22: ND54.

ND55

Bit 23: ND55.

ND56

Bit 24: ND56.

ND57

Bit 25: ND57.

ND58

Bit 26: ND58.

ND59

Bit 27: ND59.

ND60

Bit 28: ND60.

ND61

Bit 29: ND61.

ND62

Bit 30: ND62.

ND63

Bit 31: ND63.

RXF0C

FDCAN Rx FIFO 0 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F0OM
rw 		F0WM
rw 		F0S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0SA
rw
Toggle fields

F0SA

Bits 2-15: F0SA.

F0S

Bits 16-22: F0S.

F0WM

Bits 24-30: F0WM.

F0OM

Bit 31: F0OM.

RXF0S

FDCAN Rx FIFO 0 status register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw 		F0F
rw 		F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw 		F0FL
rw
Toggle fields

F0FL

Bits 0-6: F0FL.

F0GI

Bits 8-13: F0GI.

F0PI

Bits 16-21: F0PI.

F0F

Bit 24: F0F.

RF0L

Bit 25: RF0L.

RXF0A

FDCAN Rx FIFO 0 acknowledge register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-5: F0AI.

RXBC

FDCAN Rx buffer configuration register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBSA
rw
Toggle fields

RBSA

Bits 2-15: RBSA.

RXF1C

FDCAN Rx FIFO 1 configuration register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F1OM
rw 		F1WM
rw 		F1S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1SA
rw
Toggle fields

F1SA

Bits 2-15: F1SA.

F1S

Bits 16-22: F1S.

F1WM

Bits 24-30: F1WM.

F1OM

Bit 31: F1OM.

RXF1S

FDCAN Rx FIFO 1 status register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMS
r 		RF1L
r 		F1F
r 		F1PI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
r 		F1FL
r
Toggle fields

F1FL

Bits 0-6: F1FL.

F1GI

Bits 8-13: F1GI.

F1PI

Bits 16-21: F1PI.

F1F

Bit 24: F1F.

RF1L

Bit 25: RF1L.

DMS

Bits 30-31: DMS.

RXF1A

FDCAN Rx FIFO 1 acknowledge register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-5: F1AI.

RXESC

Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only.

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBDS
r 		F1DS
r 		F0DS
r
Toggle fields

F0DS

Bits 0-2: F0DS.

F1DS

Bits 4-6: F1DS.

RBDS

Bits 8-10: RBDS.

TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw 		TFQS
rw 		NDTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBSA
rw
Toggle fields

TBSA

Bits 2-15: TBSA.

NDTB

Bits 16-21: NDTB.

TFQS

Bits 24-29: TFQS.

TFQM

Bit 30: TFQM.

TXFQS

The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated).

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r 		TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r 		TFFL
r
Toggle fields

TFFL

Bits 0-5: TFFL.

TFGI

Bits 8-12: TFGI.

TFQPI

Bits 16-20: TFQPI.

TFQF

Bit 21: TFQF.

TXESC

Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only.

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBDS
r
Toggle fields

TBDS

Bits 0-2: TBDS.

TXBAR

FDCAN Tx buffer add request register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-31: AR.

TXBCR

FDCAN Tx buffer cancellation request register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-31: CR.

TXBTO

FDCAN Tx buffer transmission occurred register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
r
Toggle fields

TO

Bits 0-31: TO.

TXBCF

FDCAN Tx buffer cancellation finished register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-31: CF.

TXBTIE

FDCAN Tx buffer transmission interrupt enable register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-31: TIE.

TXBCIE

FDCAN Tx buffer cancellation finished interrupt enable register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFIE
rw
Toggle fields

CFIE

Bits 0-31: CFIE.

TXEFC

FDCAN Tx event FIFO configuration register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EFWM
rw 		EFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFSA
rw
Toggle fields

EFSA

Bits 2-15: EFSA.

EFS

Bits 16-21: EFS.

EFWM

Bits 24-29: EFWM.

TXEFS

FDCAN Tx event FIFO status register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
r 		EFF
r 		EFPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
r 		EFFL
r
Toggle fields

EFFL

Bits 0-5: EFFL.

EFGI

Bits 8-12: EFGI.

EFPI

Bits 16-20: EFPI.

EFF

Bit 24: EFF.

TEFL

Bit 25: TEFL.

TXEFA

FDCAN Tx event FIFO acknowledge register

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-4: EFAI.

TTTMC

FDCAN TT trigger memory configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSA
rw
Toggle fields

TMSA

Bits 2-15: TMSA.

TME

Bits 16-22: TME.

TTRMC

FDCAN TT reference message configuration register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RMPS
rw 		XTD
rw 		RID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RID
rw
Toggle fields

RID

Bits 0-28: RID.

XTD

Bit 30: XTD.

RMPS

Bit 31: RMPS.

TTOCF

FDCAN TT operation configuration register

Offset: 0x108, size: 32, reset: 0x00010000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVTP
rw 		ECC
rw 		EGTF
rw 		AWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EECS
rw 		IRTO
rw 		LDSDL
rw 		TM
rw 		GEN
rw 		OM
rw
Toggle fields

OM

Bits 0-1: OM.

GEN

Bit 3: GEN.

TM

Bit 4: TM.

LDSDL

Bits 5-7: LDSDL.

IRTO

Bits 8-14: IRTO.

EECS

Bit 15: EECS.

AWL

Bits 16-23: AWL.

EGTF

Bit 24: EGTF.

ECC

Bit 25: ECC.

EVTP

Bit 26: EVTP.

TTMLM

FDCAN TT matrix limits register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENTT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEW
rw 		CSS
rw 		CCM
rw
Toggle fields

CCM

Bits 0-5: CCM.

CSS

Bits 6-7: CSS.

TXEW

Bits 8-11: TXEW.

ENTT

Bits 16-27: ENTT.

TURCF

The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ELT
rw 		DC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCL
rw
Toggle fields

NCL

Bits 0-15: NCL.

DC

Bits 16-29: DC.

ELT

Bit 31: ELT.

TTOCN

FDCAN TT operation control register

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

1/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKC
r 		ESCN
rw 		NIG
rw 		TMG
rw 		FGP
rw 		GCS
rw 		TTIE
rw 		TMC
rw 		RTIE
rw 		SWS
rw 		SWP
rw 		ECS
rw 		SGT
rw
Toggle fields

SGT

Bit 0: SGT.

ECS

Bit 1: ECS.

SWP

Bit 2: SWP.

SWS

Bits 3-4: SWS.

RTIE

Bit 5: RTIE.

TMC

Bits 6-7: TMC.

TTIE

Bit 8: TTIE.

GCS

Bit 9: GCS.

FGP

Bit 10: FGP.

TMG

Bit 11: TMG.

NIG

Bit 12: NIG.

ESCN

Bit 13: ESCN.

LCKC

Bit 15: LCKC.

TTGTP

If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master.

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TP
rw
Toggle fields

TP

Bits 0-15: TP.

CTP

Bits 16-31: CTP.

TTTMK

A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM.

Offset: 0x11c, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKM
r 		TICC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TM
rw
Toggle fields

TM

Bits 0-15: TM.

TICC

Bits 16-22: TICC.

LCKM

Bit 31: LCKM.

TTIR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CER
rw 		AW
rw 		WT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTG
rw 		ELC
rw 		SE2
rw 		SE1
rw 		TXO
rw 		TXU
rw 		GTE
rw 		GTD
rw 		GTW
rw 		SWE
rw 		TTMI
rw 		RTMI
rw 		SOG
rw 		CSM
rw 		SMC
rw 		SBC
rw
Toggle fields

SBC

Bit 0: SBC.

SMC

Bit 1: SMC.

CSM

Bit 2: CSM.

SOG

Bit 3: SOG.

RTMI

Bit 4: RTMI.

TTMI

Bit 5: TTMI.

SWE

Bit 6: SWE.

GTW

Bit 7: GTW.

GTD

Bit 8: GTD.

GTE

Bit 9: GTE.

TXU

Bit 10: TXU.

TXO

Bit 11: TXO.

SE1

Bit 12: SE1.

SE2

Bit 13: SE2.

ELC

Bit 14: ELC.

IWTG

Bit 15: IWTG.

WT

Bit 16: WT.

AW

Bit 17: AW.

CER

Bit 18: CER.

TTIE

The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt.

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERE
rw 		AWE
rw 		WTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTE
rw 		ELCE
rw 		SE2E
rw 		SE1E
rw 		TXOE
rw 		TXUE
rw 		GTEE
rw 		GTDE
rw 		GTWE
rw 		SWEE
rw 		TTMIE
rw 		RTMIE
rw 		SOGE
rw 		CSME
rw 		SMCE
rw 		SBCE
rw
Toggle fields

SBCE

Bit 0: SBCE.

SMCE

Bit 1: SMCE.

CSME

Bit 2: CSME.

SOGE

Bit 3: SOGE.

RTMIE

Bit 4: RTMIE.

TTMIE

Bit 5: TTMIE.

SWEE

Bit 6: SWEE.

GTWE

Bit 7: GTWE.

GTDE

Bit 8: GTDE.

GTEE

Bit 9: GTEE.

TXUE

Bit 10: TXUE.

TXOE

Bit 11: TXOE.

SE1E

Bit 12: SE1E.

SE2E

Bit 13: SE2E.

ELCE

Bit 14: ELCE.

IWTE

Bit 15: IWTE.

WTE

Bit 16: WTE.

AWE

Bit 17: AWE.

CERE

Bit 18: CERE.

TTILS

The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERL
rw 		AWL
rw 		WTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTL
rw 		ELCL
rw 		SE2L
rw 		SE1L
rw 		TXOL
rw 		TXUL
rw 		GTEL
rw 		GTDL
rw 		GTWL
rw 		SWEL
rw 		TTMIL
rw 		RTMIL
rw 		SOGL
rw 		CSML
rw 		SMCL
rw 		SBCL
rw
Toggle fields

SBCL

Bit 0: SBCL.

SMCL

Bit 1: SMCL.

CSML

Bit 2: CSML.

SOGL

Bit 3: SOGL.

RTMIL

Bit 4: RTMIL.

TTMIL

Bit 5: TTMIL.

SWEL

Bit 6: SWEL.

GTWL

Bit 7: GTWL.

GTDL

Bit 8: GTDL.

GTEL

Bit 9: GTEL.

TXUL

Bit 10: TXUL.

TXOL

Bit 11: TXOL.

SE1L

Bit 12: SE1L.

SE2L

Bit 13: SE2L.

ELCL

Bit 14: ELCL.

IWTL

Bit 15: IWTL.

WTL

Bit 16: WTL.

AWL

Bit 17: AWL.

CERL

Bit 18: CERL.

TTOST

FDCAN TT operation status register

Offset: 0x12c, size: 32, reset: 0x00000080, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPL
r 		WECS
r 		AWE
r 		WFE
r 		GSI
r 		TMP
r 		GFI
r 		WGTD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
r 		QCS
r 		QGTP
r 		SYS
r 		MS
r 		EL
r
Toggle fields

EL

Bits 0-1: EL.

MS

Bits 2-3: MS.

SYS

Bits 4-5: SYS.

QGTP

Bit 6: QGTP.

QCS

Bit 7: QCS.

RTO

Bits 8-15: RTO.

WGTD

Bit 22: WGTD.

GFI

Bit 23: GFI.

TMP

Bits 24-26: TMP.

GSI

Bit 27: GSI.

WFE

Bit 28: WFE.

AWE

Bit 29: AWE.

WECS

Bit 30: WECS.

SPL

Bit 31: SPL.

TURNA

There is no drift compensation in TTCAN level 1.

Offset: 0x130, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAV
r
Toggle fields

NAV

Bits 0-17: NAV.

TTLGT

FDCAN TT local and global time register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
r
Toggle fields

LT

Bits 0-15: LT.

GT

Bits 16-31: GT.

TTCTC

FDCAN TT cycle time and count register

Offset: 0x138, size: 32, reset: 0x003F0000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT
r
Toggle fields

CT

Bits 0-15: CT.

CC

Bits 16-21: CC.

TTCPT

FDCAN TT capture time register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCV
r
Toggle fields

CCV

Bits 0-5: CCV.

SWV

Bits 16-31: SWV.

TTCSM

FDCAN TT cycle sync mark register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSM
r
Toggle fields

CSM

Bits 0-15: CSM.

TTTS

The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger.

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVTSEL
rw 		SWTDEL
rw
Toggle fields

SWTDEL

Bits 0-1: SWTDEL.

EVTSEL

Bits 4-5: EVTSEL.

FDCAN2

0x4400f000: FDCAN1

69/396 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CREL
0x4 ENDN
0xc DBTP
0x10 TEST
0x14 RWD
0x18 CCCR
0x1c NBTP
0x20 TSCC
0x24 TSCV
0x28 TOCC
0x2c TOCV
0x40 ECR
0x44 PSR
0x48 TDCR
0x50 IR
0x54 IE
0x58 ILS
0x5c ILE
0x80 GFC
0x84 SIDFC
0x88 XIDFC
0x90 XIDAM
0x94 HPMS
0x98 NDAT1
0x9c NDAT2
0xa0 RXF0C
0xa4 RXF0S
0xa8 RXF0A
0xac RXBC
0xb0 RXF1C
0xb4 RXF1S
0xb8 RXF1A
0xbc RXESC
0xc0 TXBC
0xc4 TXFQS
0xc8 TXESC
0xd0 TXBAR
0xd4 TXBCR
0xd8 TXBTO
0xdc TXBCF
0xe0 TXBTIE
0xe4 TXBCIE
0xf0 TXEFC
0xf4 TXEFS
0xf8 TXEFA
0x100 TTTMC
0x104 TTRMC
0x108 TTOCF
0x10c TTMLM
0x110 TURCF
0x114 TTOCN
0x118 TTGTP
0x11c TTTMK
0x120 TTIR
0x124 TTIE
0x128 TTILS
0x12c TTOST
0x130 TURNA
0x134 TTLGT
0x138 TTCTC
0x13c TTCPT
0x140 TTCSM
0x300 TTTS
Toggle registers

CREL

FDCAN core release register

Offset: 0x0, size: 32, reset: 0x32141218, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL
r 		STEP
r 		SUBSTEP
r 		YEAR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MON
r 		DAY
r
Toggle fields

DAY

Bits 0-7: DAY.

MON

Bits 8-15: MON.

YEAR

Bits 16-19: YEAR.

SUBSTEP

Bits 20-23: SUBSTEP.

STEP

Bits 24-27: STEP.

REL

Bits 28-31: REL.

ENDN

FDCAN Endian register

Offset: 0x4, size: 32, reset: 0x87654321, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETV
r
Toggle fields

ETV

Bits 0-31: ETV.

DBTP

This register is dedicated to data bit timing phase and only writable if bits FDCAN_CCCR.CCE and FDCAN_CCCR.INIT are set. The CAN time quantum may be programmed in the range from 1 to 32 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock periods. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (DTSEG1 + DTSEG2 + 3) tq for programmed values, or (Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2) tq for functional values. The information processing time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

Offset: 0xc, size: 32, reset: 0x00000A33, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDC
rw 		DBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTSEG1
rw 		DTSEG2
rw 		DSJW
rw
Toggle fields

DSJW

Bits 0-3: DSJW.

DTSEG2

Bits 4-7: DTSEG2.

DTSEG1

Bits 8-12: DTSEG1.

DBRP

Bits 16-20: DBRP.

TDC

Bit 23: TDC.

TEST

Write access to this register has to be enabled by setting bit FDCAN_CCCR.TEST to 1. All register functions are set to their reset values when bit FDCAN_CCCR.TEST is reset. Loop back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RX
r 		TX
rw 		LBCK
rw
Toggle fields

LBCK

Bit 4: LBCK.

TX

Bits 5-6: TX.

RX

Bit 7: RX.

RWD

The RAM watchdog monitors the READY output of the message RAM. A message RAM access starts the message RAM watchdog counter with the value configured by the FDCAN_RWD.WDC bits. The counter is reloaded with FDCAN_RWD.WDC bits when the message RAM signals successful completion by activating its READY output. In case there is no response from the message RAM until the counter has counted down to 0, the counter stops and interrupt flag FDCAN_IR.WDI bit is set. The RAM watchdog counter is clocked by the fdcan_pclk clock.

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDV
r 		WDC
rw
Toggle fields

WDC

Bits 0-7: WDC.

WDV

Bits 8-15: WDV.

CCCR

For details about setting and resetting of single bits see Software initialization.

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

1/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NISO
rw 		TXP
rw 		EFBI
rw 		PXHD
rw 		BRSE
rw 		FDOE
rw 		TEST
rw 		DAR
rw 		MON
rw 		CSR
rw 		CSA
r 		ASM
rw 		CCE
rw 		INIT
rw
Toggle fields

INIT

Bit 0: INIT.

CCE

Bit 1: CCE.

ASM

Bit 2: ASM.

CSA

Bit 3: CSA.

CSR

Bit 4: CSR.

MON

Bit 5: MON.

DAR

Bit 6: DAR.

TEST

Bit 7: TEST.

FDOE

Bit 8: FDOE.

BRSE

Bit 9: BRSE.

PXHD

Bit 12: PXHD.

EFBI

Bit 13: EFBI.

TXP

Bit 14: TXP.

NISO

Bit 15: NISO.

NBTP

This register is dedicated to the nominal bit timing used during the arbitration phase.

Offset: 0x1c, size: 32, reset: 0x00000A33, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSJW
rw 		NBRP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NTSEG1
rw 		NTSEG2
rw
Toggle fields

NTSEG2

Bits 0-6: NTSEG2.

NTSEG1

Bits 8-15: NTSEG1.

NBRP

Bits 16-24: NBRP.

NSJW

Bits 25-31: NSJW.

TSCC

FDCAN timestamp counter configuration register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSS
rw
Toggle fields

TSS

Bits 0-1: TSS.

TCP

Bits 16-19: TCP.

TSCV

FDCAN timestamp counter value register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSC
rw
Toggle fields

TSC

Bits 0-15: TSC.

TOCC

FDCAN timeout counter configuration register

Offset: 0x28, size: 32, reset: 0xFFFF0000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOS
rw 		ETOC
rw
Toggle fields

ETOC

Bit 0: ETOC.

TOS

Bits 1-2: TOS.

TOP

Bits 16-31: TOP.

TOCV

FDCAN timeout counter value register

Offset: 0x2c, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOC
rw
Toggle fields

TOC

Bits 0-15: TOC.

ECR

FDCAN error counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: Unspecified

3/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP
r 		TREC
r 		TEC
r
Toggle fields

TEC

Bits 0-7: TEC.

TREC

Bits 8-14: TREC.

RP

Bit 15: RP.

CEL

Bits 16-23: CEL.

PSR

FDCAN protocol status register

Offset: 0x44, size: 32, reset: 0x00000707, access: Unspecified

7/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDCV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PXE
rw 		REDL
rw 		RBRS
rw 		RESI
rw 		DLEC
r 		BO
r 		EW
r 		EP
r 		ACT
r 		LEC
r
Toggle fields

LEC

Bits 0-2: LEC.

ACT

Bits 3-4: ACT.

EP

Bit 5: EP.

EW

Bit 6: EW.

BO

Bit 7: BO.

DLEC

Bits 8-10: DLEC.

RESI

Bit 11: RESI.

RBRS

Bit 12: RBRS.

REDL

Bit 13: REDL.

PXE

Bit 14: PXE.

TDCV

Bits 16-22: TDCV.

TDCR

FDCAN transmitter delay compensation register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDCO
rw 		TDCF
rw
Toggle fields

TDCF

Bits 0-6: TDCF.

TDCO

Bits 8-14: TDCO.

IR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARA
rw 		PED
rw 		PEA
rw 		WDI
rw 		BO
rw 		EW
rw 		EP
rw 		ELO
rw 		DRX
rw 		TOO
rw 		MRAF
rw 		TSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFL
rw 		TEFF
rw 		TEFW
rw 		TEFN
rw 		TFE
rw 		TCF
rw 		TC
rw 		HPM
rw 		RF1L
rw 		RF1F
rw 		RF1W
rw 		RF1N
rw 		RF0L
rw 		RF0F
rw 		RF0W
rw 		RF0N
rw
Toggle fields

RF0N

Bit 0: RF0N.

RF0W

Bit 1: RF0W.

RF0F

Bit 2: RF0F.

RF0L

Bit 3: RF0L.

RF1N

Bit 4: RF1N.

RF1W

Bit 5: RF1W.

RF1F

Bit 6: RF1F.

RF1L

Bit 7: RF1L.

HPM

Bit 8: HPM.

TC

Bit 9: TC.

TCF

Bit 10: TCF.

TFE

Bit 11: TFE.

TEFN

Bit 12: TEFN.

TEFW

Bit 13: TEFW.

TEFF

Bit 14: TEFF.

TEFL

Bit 15: TEFL.

TSW

Bit 16: TSW.

MRAF

Bit 17: MRAF.

TOO

Bit 18: TOO.

DRX

Bit 19: DRX.

ELO

Bit 22: ELO.

EP

Bit 23: EP.

EW

Bit 24: EW.

BO

Bit 25: BO.

WDI

Bit 26: WDI.

PEA

Bit 27: PEA.

PED

Bit 28: PED.

ARA

Bit 29: ARA.

IE

The settings in the interrupt enable register determine which status changes in the interrupt register will be signaled on an interrupt line.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAE
rw 		PEDE
rw 		PEAE
rw 		WDIE
rw 		BOE
rw 		EWE
rw 		EPE
rw 		ELOE
rw 		BEUE
rw 		BECE
rw 		DRXE
rw 		TOOE
rw 		MRAFE
rw 		TSWE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLE
rw 		TEFFE
rw 		TEFWE
rw 		TEFNE
rw 		TFEE
rw 		TCFE
rw 		TCE
rw 		HPME
rw 		RF1LE
rw 		RF1FE
rw 		RF1WE
rw 		RF1NE
rw 		RF0LE
rw 		RF0FE
rw 		RF0WE
rw 		RF0NE
rw
Toggle fields

RF0NE

Bit 0: RF0NE.

RF0WE

Bit 1: RF0WE.

RF0FE

Bit 2: RF0FE.

RF0LE

Bit 3: RF0LE.

RF1NE

Bit 4: RF1NE.

RF1WE

Bit 5: RF1WE.

RF1FE

Bit 6: RF1FE.

RF1LE

Bit 7: RF1LE.

HPME

Bit 8: HPME.

TCE

Bit 9: TCE.

TCFE

Bit 10: TCFE.

TFEE

Bit 11: TFEE.

TEFNE

Bit 12: TEFNE.

TEFWE

Bit 13: TEFWE.

TEFFE

Bit 14: TEFFE.

TEFLE

Bit 15: TEFLE.

TSWE

Bit 16: TSWE.

MRAFE

Bit 17: MRAFE.

TOOE

Bit 18: TOOE.

DRXE

Bit 19: DRXE.

BECE

Bit 20: BECE.

BEUE

Bit 21: BEUE.

ELOE

Bit 22: ELOE.

EPE

Bit 23: EPE.

EWE

Bit 24: EWE.

BOE

Bit 25: BOE.

WDIE

Bit 26: WDIE.

PEAE

Bit 27: PEAE.

PEDE

Bit 28: PEDE.

ARAE

Bit 29: ARAE.

ILS

This register assigns an interrupt generated by a specific interrupt flag from the interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/30 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARAL
rw 		PEDL
rw 		PEAL
rw 		WDIL
rw 		BOL
rw 		EWL
rw 		EPL
rw 		ELOL
rw 		BEUL
rw 		BECL
rw 		DRXL
rw 		TOOL
rw 		MRAFL
rw 		TSWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEFLL
rw 		TEFFL
rw 		TEFWL
rw 		TEFNL
rw 		TFEL
rw 		TCFL
rw 		TCL
rw 		HPML
rw 		RF1LL
rw 		RF1FL
rw 		RF1WL
rw 		RF1NL
rw 		RF0LL
rw 		RF0FL
rw 		RF0WL
rw 		RF0NL
rw
Toggle fields

RF0NL

Bit 0: RF0NL.

RF0WL

Bit 1: RF0WL.

RF0FL

Bit 2: RF0FL.

RF0LL

Bit 3: RF0LL.

RF1NL

Bit 4: RF1NL.

RF1WL

Bit 5: RF1WL.

RF1FL

Bit 6: RF1FL.

RF1LL

Bit 7: RF1LL.

HPML

Bit 8: HPML.

TCL

Bit 9: TCL.

TCFL

Bit 10: TCFL.

TFEL

Bit 11: TFEL.

TEFNL

Bit 12: TEFNL.

TEFWL

Bit 13: TEFWL.

TEFFL

Bit 14: TEFFL.

TEFLL

Bit 15: TEFLL.

TSWL

Bit 16: TSWL.

MRAFL

Bit 17: MRAFL.

TOOL

Bit 18: TOOL.

DRXL

Bit 19: DRXL.

BECL

Bit 20: BECL.

BEUL

Bit 21: BEUL.

ELOL

Bit 22: ELOL.

EPL

Bit 23: EPL.

EWL

Bit 24: EWL.

BOL

Bit 25: BOL.

WDIL

Bit 26: WDIL.

PEAL

Bit 27: PEAL.

PEDL

Bit 28: PEDL.

ARAL

Bit 29: ARAL.

ILE

Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EINT1
rw 		EINT0
rw
Toggle fields

EINT0

Bit 0: EINT0.

EINT1

Bit 1: EINT1.

GFC

Global settings for message ID filtering. The global filter configuration register controls the filter path for standard and extended messages as described in Figure708: Standard message ID filter path and Figure709: Extended message ID filter path.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANFS
rw 		ANFE
rw 		RRFS
rw 		RRFE
rw
Toggle fields

RRFE

Bit 0: RRFE.

RRFS

Bit 1: RRFS.

ANFE

Bits 2-3: ANFE.

ANFS

Bits 4-5: ANFS.

SIDFC

Settings for 11-bit standard message ID filtering.The standard ID filter configuration register controls the filter path for standard messages as described in Figure708.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLSSA
rw
Toggle fields

FLSSA

Bits 2-15: FLSSA.

LSS

Bits 16-23: LSS.

XIDFC

Settings for 29-bit extended message ID filtering. The FDCAN extended ID filter configuration register controls the filter path for standard messages as described in Figure709: Extended message ID filter path.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLESA
rw
Toggle fields

FLESA

Bits 2-15: FLESA.

LSE

Bits 16-23: LSE.

XIDAM

FDCAN extended ID and mask register

Offset: 0x90, size: 32, reset: 0x1FFFFFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EIDM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIDM
rw
Toggle fields

EIDM

Bits 0-28: EIDM.

HPMS

This register is updated every time a message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLST
r 		FIDX
r 		MSI
r 		BIDX
r
Toggle fields

BIDX

Bits 0-5: BIDX.

MSI

Bits 6-7: MSI.

FIDX

Bits 8-14: FIDX.

FLST

Bit 15: FLST.

NDAT1

FDCAN new data 1 register

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND31
rw 		ND30
rw 		ND29
rw 		ND28
rw 		ND27
rw 		ND26
rw 		ND25
rw 		ND24
rw 		ND23
rw 		ND22
rw 		ND21
rw 		ND20
rw 		ND19
rw 		ND18
rw 		ND17
rw 		ND16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND15
rw 		ND14
rw 		ND13
rw 		ND12
rw 		ND11
rw 		ND10
rw 		ND9
rw 		ND8
rw 		ND7
rw 		ND6
rw 		ND5
rw 		ND4
rw 		ND3
rw 		ND2
rw 		ND1
rw 		ND0
rw
Toggle fields

ND0

Bit 0: ND0.

ND1

Bit 1: ND1.

ND2

Bit 2: ND2.

ND3

Bit 3: ND3.

ND4

Bit 4: ND4.

ND5

Bit 5: ND5.

ND6

Bit 6: ND6.

ND7

Bit 7: ND7.

ND8

Bit 8: ND8.

ND9

Bit 9: ND9.

ND10

Bit 10: ND10.

ND11

Bit 11: ND11.

ND12

Bit 12: ND12.

ND13

Bit 13: ND13.

ND14

Bit 14: ND14.

ND15

Bit 15: ND15.

ND16

Bit 16: ND16.

ND17

Bit 17: ND17.

ND18

Bit 18: ND18.

ND19

Bit 19: ND19.

ND20

Bit 20: ND20.

ND21

Bit 21: ND21.

ND22

Bit 22: ND22.

ND23

Bit 23: ND23.

ND24

Bit 24: ND24.

ND25

Bit 25: ND25.

ND26

Bit 26: ND26.

ND27

Bit 27: ND27.

ND28

Bit 28: ND28.

ND29

Bit 29: ND29.

ND30

Bit 30: ND30.

ND31

Bit 31: ND31.

NDAT2

FDCAN new data 2 register

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ND63
rw 		ND62
rw 		ND61
rw 		ND60
rw 		ND59
rw 		ND58
rw 		ND57
rw 		ND56
rw 		ND55
rw 		ND54
rw 		ND53
rw 		ND52
rw 		ND51
rw 		ND50
rw 		ND49
rw 		ND48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ND47
rw 		ND46
rw 		ND45
rw 		ND44
rw 		ND43
rw 		ND42
rw 		ND41
rw 		ND40
rw 		ND39
rw 		ND38
rw 		ND37
rw 		ND36
rw 		ND35
rw 		ND34
rw 		ND33
rw 		ND32
rw
Toggle fields

ND32

Bit 0: ND32.

ND33

Bit 1: ND33.

ND34

Bit 2: ND34.

ND35

Bit 3: ND35.

ND36

Bit 4: ND36.

ND37

Bit 5: ND37.

ND38

Bit 6: ND38.

ND39

Bit 7: ND39.

ND40

Bit 8: ND40.

ND41

Bit 9: ND41.

ND42

Bit 10: ND42.

ND43

Bit 11: ND43.

ND44

Bit 12: ND44.

ND45

Bit 13: ND45.

ND46

Bit 14: ND46.

ND47

Bit 15: ND47.

ND48

Bit 16: ND48.

ND49

Bit 17: ND49.

ND50

Bit 18: ND50.

ND51

Bit 19: ND51.

ND52

Bit 20: ND52.

ND53

Bit 21: ND53.

ND54

Bit 22: ND54.

ND55

Bit 23: ND55.

ND56

Bit 24: ND56.

ND57

Bit 25: ND57.

ND58

Bit 26: ND58.

ND59

Bit 27: ND59.

ND60

Bit 28: ND60.

ND61

Bit 29: ND61.

ND62

Bit 30: ND62.

ND63

Bit 31: ND63.

RXF0C

FDCAN Rx FIFO 0 configuration register

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F0OM
rw 		F0WM
rw 		F0S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0SA
rw
Toggle fields

F0SA

Bits 2-15: F0SA.

F0S

Bits 16-22: F0S.

F0WM

Bits 24-30: F0WM.

F0OM

Bit 31: F0OM.

RXF0S

FDCAN Rx FIFO 0 status register

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RF0L
rw 		F0F
rw 		F0PI
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0GI
rw 		F0FL
rw
Toggle fields

F0FL

Bits 0-6: F0FL.

F0GI

Bits 8-13: F0GI.

F0PI

Bits 16-21: F0PI.

F0F

Bit 24: F0F.

RF0L

Bit 25: RF0L.

RXF0A

FDCAN Rx FIFO 0 acknowledge register

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F0AI
rw
Toggle fields

F0AI

Bits 0-5: F0AI.

RXBC

FDCAN Rx buffer configuration register

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBSA
rw
Toggle fields

RBSA

Bits 2-15: RBSA.

RXF1C

FDCAN Rx FIFO 1 configuration register

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
F1OM
rw 		F1WM
rw 		F1S
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1SA
rw
Toggle fields

F1SA

Bits 2-15: F1SA.

F1S

Bits 16-22: F1S.

F1WM

Bits 24-30: F1WM.

F1OM

Bit 31: F1OM.

RXF1S

FDCAN Rx FIFO 1 status register

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMS
r 		RF1L
r 		F1F
r 		F1PI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1GI
r 		F1FL
r
Toggle fields

F1FL

Bits 0-6: F1FL.

F1GI

Bits 8-13: F1GI.

F1PI

Bits 16-21: F1PI.

F1F

Bit 24: F1F.

RF1L

Bit 25: RF1L.

DMS

Bits 30-31: DMS.

RXF1A

FDCAN Rx FIFO 1 acknowledge register

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1AI
rw
Toggle fields

F1AI

Bits 0-5: F1AI.

RXESC

Configures the number of data bytes belonging to an Rx buffer / Rx FIFO element. Data field sizes higher than 8 bytes are intended for CAN FD operation only.

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBDS
r 		F1DS
r 		F0DS
r
Toggle fields

F0DS

Bits 0-2: F0DS.

F1DS

Bits 4-6: F1DS.

RBDS

Bits 8-10: RBDS.

TXBC

FDCAN Tx buffer configuration register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQM
rw 		TFQS
rw 		NDTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBSA
rw
Toggle fields

TBSA

Bits 2-15: TBSA.

NDTB

Bits 16-21: NDTB.

TFQS

Bits 24-29: TFQS.

TFQM

Bit 30: TFQM.

TXFQS

The Tx FIFO/queue status is related to the pending Tx requests listed in register FDCAN_TXBRP. Therefore the effect of add/cancellation requests may be delayed due to a running Tx scan (FDCAN_TXBRP not yet updated).

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TFQF
r 		TFQPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TFGI
r 		TFFL
r
Toggle fields

TFFL

Bits 0-5: TFFL.

TFGI

Bits 8-12: TFGI.

TFQPI

Bits 16-20: TFQPI.

TFQF

Bit 21: TFQF.

TXESC

Configures the number of data bytes belonging to a Tx buffer element. Data field sizes >8 bytes are intended for CAN FD operation only.

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBDS
r
Toggle fields

TBDS

Bits 0-2: TBDS.

TXBAR

FDCAN Tx buffer add request register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AR
rw
Toggle fields

AR

Bits 0-31: AR.

TXBCR

FDCAN Tx buffer cancellation request register

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
rw
Toggle fields

CR

Bits 0-31: CR.

TXBTO

FDCAN Tx buffer transmission occurred register

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO
r
Toggle fields

TO

Bits 0-31: TO.

TXBCF

FDCAN Tx buffer cancellation finished register

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CF
r
Toggle fields

CF

Bits 0-31: CF.

TXBTIE

FDCAN Tx buffer transmission interrupt enable register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw
Toggle fields

TIE

Bits 0-31: TIE.

TXBCIE

FDCAN Tx buffer cancellation finished interrupt enable register

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFIE
rw
Toggle fields

CFIE

Bits 0-31: CFIE.

TXEFC

FDCAN Tx event FIFO configuration register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EFWM
rw 		EFS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFSA
rw
Toggle fields

EFSA

Bits 2-15: EFSA.

EFS

Bits 16-21: EFS.

EFWM

Bits 24-29: EFWM.

TXEFS

FDCAN Tx event FIFO status register

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEFL
r 		EFF
r 		EFPI
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFGI
r 		EFFL
r
Toggle fields

EFFL

Bits 0-5: EFFL.

EFGI

Bits 8-12: EFGI.

EFPI

Bits 16-20: EFPI.

EFF

Bit 24: EFF.

TEFL

Bit 25: TEFL.

TXEFA

FDCAN Tx event FIFO acknowledge register

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EFAI
rw
Toggle fields

EFAI

Bits 0-4: EFAI.

TTTMC

FDCAN TT trigger memory configuration register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMSA
rw
Toggle fields

TMSA

Bits 2-15: TMSA.

TME

Bits 16-22: TME.

TTRMC

FDCAN TT reference message configuration register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RMPS
rw 		XTD
rw 		RID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RID
rw
Toggle fields

RID

Bits 0-28: RID.

XTD

Bit 30: XTD.

RMPS

Bit 31: RMPS.

TTOCF

FDCAN TT operation configuration register

Offset: 0x108, size: 32, reset: 0x00010000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EVTP
rw 		ECC
rw 		EGTF
rw 		AWL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EECS
rw 		IRTO
rw 		LDSDL
rw 		TM
rw 		GEN
rw 		OM
rw
Toggle fields

OM

Bits 0-1: OM.

GEN

Bit 3: GEN.

TM

Bit 4: TM.

LDSDL

Bits 5-7: LDSDL.

IRTO

Bits 8-14: IRTO.

EECS

Bit 15: EECS.

AWL

Bits 16-23: AWL.

EGTF

Bit 24: EGTF.

ECC

Bit 25: ECC.

EVTP

Bit 26: EVTP.

TTMLM

FDCAN TT matrix limits register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENTT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEW
rw 		CSS
rw 		CCM
rw
Toggle fields

CCM

Bits 0-5: CCM.

CSS

Bits 6-7: CSS.

TXEW

Bits 8-11: TXEW.

ENTT

Bits 16-27: ENTT.

TURCF

The length of the NTU is given by: NTU = CAN clock period x NC/DC. NC is an 18-bit value. Its high part, NCH[17:16] is hard wired to 0b01. Therefore the range of NC extends from 0x10000 to 0x1FFFF. The value configured by NCL is the initial value for FDCAN_TURNA.NAV[15:0]. DC is set to 0x1000 by hardware reset and it may not be written to 0x0000. Level 1: NC 4 * DC and NTU = CAN bit time Levels 0 and 2: NC 8 * DC The actual value of FDCAN_TUR may be changed by the clock drift compensation function of TTCAN level 0 and level 2 in order to adjust the node local view of the NTU to the time master view of the NTU. DC will not be changed by the automatic drift compensation, FDCAN_TURNA.NAV may be adjusted around NC in the range of the synchronization deviation limit given by FDCAN_TTOCF.LDSDL. NC and DC should be programmed to the largest suitable values in achieve the best computational accuracy for the drift compensation process.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ELT
rw 		DC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NCL
rw
Toggle fields

NCL

Bits 0-15: NCL.

DC

Bits 16-29: DC.

ELT

Bit 31: ELT.

TTOCN

FDCAN TT operation control register

Offset: 0x114, size: 32, reset: 0x00000000, access: Unspecified

1/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKC
r 		ESCN
rw 		NIG
rw 		TMG
rw 		FGP
rw 		GCS
rw 		TTIE
rw 		TMC
rw 		RTIE
rw 		SWS
rw 		SWP
rw 		ECS
rw 		SGT
rw
Toggle fields

SGT

Bit 0: SGT.

ECS

Bit 1: ECS.

SWP

Bit 2: SWP.

SWS

Bits 3-4: SWS.

RTIE

Bit 5: RTIE.

TMC

Bits 6-7: TMC.

TTIE

Bit 8: TTIE.

GCS

Bit 9: GCS.

FGP

Bit 10: FGP.

TMG

Bit 11: TMG.

NIG

Bit 12: NIG.

ESCN

Bit 13: ESCN.

LCKC

Bit 15: LCKC.

TTGTP

If TTOST.WGDT is set, the next reference message will be transmitted with the Master_Ref_Mark modified by the preset value and with Disc_Bit = 1, presetting the global time in all nodes simultaneously. TP is reset to 0x0000 each time a reference message with Disc_Bit = 1 becomes valid or if the node is not the current time master. TP is locked while FDCAN_TTOST.WGTD = 1 after setting FDCAN_TTOCN.SGT until the reference message with Disc_Bit = 1 becomes valid or until the node is no longer the current time master.

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TP
rw
Toggle fields

TP

Bits 0-15: TP.

CTP

Bits 16-31: CTP.

TTTMK

A time mark interrupt (FDCAN_TTIR.TMI = 1) is generated when the time base indicated by FDCAN_TTOCN.TMC (cycle time, local time, or global time) has the same value as TM.

Offset: 0x11c, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKM
r 		TICC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TM
rw
Toggle fields

TM

Bits 0-15: TM.

TICC

Bits 16-22: TICC.

LCKM

Bit 31: LCKM.

TTIR

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register.

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CER
rw 		AW
rw 		WT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTG
rw 		ELC
rw 		SE2
rw 		SE1
rw 		TXO
rw 		TXU
rw 		GTE
rw 		GTD
rw 		GTW
rw 		SWE
rw 		TTMI
rw 		RTMI
rw 		SOG
rw 		CSM
rw 		SMC
rw 		SBC
rw
Toggle fields

SBC

Bit 0: SBC.

SMC

Bit 1: SMC.

CSM

Bit 2: CSM.

SOG

Bit 3: SOG.

RTMI

Bit 4: RTMI.

TTMI

Bit 5: TTMI.

SWE

Bit 6: SWE.

GTW

Bit 7: GTW.

GTD

Bit 8: GTD.

GTE

Bit 9: GTE.

TXU

Bit 10: TXU.

TXO

Bit 11: TXO.

SE1

Bit 12: SE1.

SE2

Bit 13: SE2.

ELC

Bit 14: ELC.

IWTG

Bit 15: IWTG.

WT

Bit 16: WT.

AW

Bit 17: AW.

CER

Bit 18: CER.

TTIE

The settings in the TT interrupt enable register determine which status changes in the TT interrupt register will result in an interrupt.

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERE
rw 		AWE
rw 		WTE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTE
rw 		ELCE
rw 		SE2E
rw 		SE1E
rw 		TXOE
rw 		TXUE
rw 		GTEE
rw 		GTDE
rw 		GTWE
rw 		SWEE
rw 		TTMIE
rw 		RTMIE
rw 		SOGE
rw 		CSME
rw 		SMCE
rw 		SBCE
rw
Toggle fields

SBCE

Bit 0: SBCE.

SMCE

Bit 1: SMCE.

CSME

Bit 2: CSME.

SOGE

Bit 3: SOGE.

RTMIE

Bit 4: RTMIE.

TTMIE

Bit 5: TTMIE.

SWEE

Bit 6: SWEE.

GTWE

Bit 7: GTWE.

GTDE

Bit 8: GTDE.

GTEE

Bit 9: GTEE.

TXUE

Bit 10: TXUE.

TXOE

Bit 11: TXOE.

SE1E

Bit 12: SE1E.

SE2E

Bit 13: SE2E.

ELCE

Bit 14: ELCE.

IWTE

Bit 15: IWTE.

WTE

Bit 16: WTE.

AWE

Bit 17: AWE.

CERE

Bit 18: CERE.

TTILS

The TT interrupt Line select register assigns an interrupt generated by a specific interrupt flag from the TT interrupt register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via FDCAN_ILE.EINT0 and FDCAN_ILE.EINT1.

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CERL
rw 		AWL
rw 		WTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWTL
rw 		ELCL
rw 		SE2L
rw 		SE1L
rw 		TXOL
rw 		TXUL
rw 		GTEL
rw 		GTDL
rw 		GTWL
rw 		SWEL
rw 		TTMIL
rw 		RTMIL
rw 		SOGL
rw 		CSML
rw 		SMCL
rw 		SBCL
rw
Toggle fields

SBCL

Bit 0: SBCL.

SMCL

Bit 1: SMCL.

CSML

Bit 2: CSML.

SOGL

Bit 3: SOGL.

RTMIL

Bit 4: RTMIL.

TTMIL

Bit 5: TTMIL.

SWEL

Bit 6: SWEL.

GTWL

Bit 7: GTWL.

GTDL

Bit 8: GTDL.

GTEL

Bit 9: GTEL.

TXUL

Bit 10: TXUL.

TXOL

Bit 11: TXOL.

SE1L

Bit 12: SE1L.

SE2L

Bit 13: SE2L.

ELCL

Bit 14: ELCL.

IWTL

Bit 15: IWTL.

WTL

Bit 16: WTL.

AWL

Bit 17: AWL.

CERL

Bit 18: CERL.

TTOST

FDCAN TT operation status register

Offset: 0x12c, size: 32, reset: 0x00000080, access: read-only

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPL
r 		WECS
r 		AWE
r 		WFE
r 		GSI
r 		TMP
r 		GFI
r 		WGTD
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
r 		QCS
r 		QGTP
r 		SYS
r 		MS
r 		EL
r
Toggle fields

EL

Bits 0-1: EL.

MS

Bits 2-3: MS.

SYS

Bits 4-5: SYS.

QGTP

Bit 6: QGTP.

QCS

Bit 7: QCS.

RTO

Bits 8-15: RTO.

WGTD

Bit 22: WGTD.

GFI

Bit 23: GFI.

TMP

Bits 24-26: TMP.

GSI

Bit 27: GSI.

WFE

Bit 28: WFE.

AWE

Bit 29: AWE.

WECS

Bit 30: WECS.

SPL

Bit 31: SPL.

TURNA

There is no drift compensation in TTCAN level 1.

Offset: 0x130, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAV
r
Toggle fields

NAV

Bits 0-17: NAV.

TTLGT

FDCAN TT local and global time register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LT
r
Toggle fields

LT

Bits 0-15: LT.

GT

Bits 16-31: GT.

TTCTC

FDCAN TT cycle time and count register

Offset: 0x138, size: 32, reset: 0x003F0000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CT
r
Toggle fields

CT

Bits 0-15: CT.

CC

Bits 16-21: CC.

TTCPT

FDCAN TT capture time register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCV
r
Toggle fields

CCV

Bits 0-5: CCV.

SWV

Bits 16-31: SWV.

TTCSM

FDCAN TT cycle sync mark register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSM
r
Toggle fields

CSM

Bits 0-15: CSM.

TTTS

The settings in the FDCAN_TTTS register select the input to be used as event trigger and stop watch trigger.

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EVTSEL
rw 		SWTDEL
rw
Toggle fields

SWTDEL

Bits 0-1: SWTDEL.

EVTSEL

Bits 4-5: EVTSEL.

FMC

0x58002000: FMC register block

44/249 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BCR1
0x4 BTR1
0x8 BCR2
0xc BTR2
0x10 BCR3
0x14 BTR3
0x18 BCR4
0x1c BTR4
0x20 PCSCNTR
0x80 PCR
0x84 SR
0x88 PMEM
0x8c PATT
0x90 HPR
0x94 HECCR
0x104 BWTR1
0x10c BWTR2
0x114 BWTR3
0x11c BWTR4
0x200 CSQCR
0x204 CSQCFGR1
0x208 CSQCFGR2
0x20c CSQCFGR3
0x210 CSQAR1
0x214 CSQAR2
0x220 CSQIER
0x224 CSQISR
0x228 CSQICR
0x230 CSQEMSR
0x250 BCHIER
0x254 BCHISR
0x258 BCHICR
0x260 BCHPBR1
0x264 BCHPBR2
0x268 BCHPBR3
0x26c BCHPBR4
0x27c BCHDSR0
0x280 BCHDSR1
0x284 BCHDSR2
0x288 BCHDSR3
0x28c BCHDSR4
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

BCR1

This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.

Offset: 0x0, size: 32, reset: 0x000030DB, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMCEN
rw 		NBLSET
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

CCLKEN

Bit 20: CCLKEN.

NBLSET

Bits 22-23: NBLSET.

FMCEN

Bit 31: FMCEN.

BTR1

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x4, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

BCR2

This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.

Offset: 0x8, size: 32, reset: 0x000030DB, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMCEN
rw 		NBLSET
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

CCLKEN

Bit 20: CCLKEN.

NBLSET

Bits 22-23: NBLSET.

FMCEN

Bit 31: FMCEN.

BTR2

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0xc, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

BCR3

This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.

Offset: 0x10, size: 32, reset: 0x000030DB, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMCEN
rw 		NBLSET
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

CCLKEN

Bit 20: CCLKEN.

NBLSET

Bits 22-23: NBLSET.

FMCEN

Bit 31: FMCEN.

BTR3

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x14, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

BCR4

This register contains the control information of each memory bank, used for SRAMs, PSRAM, FRAM and NOR Flash memories.

Offset: 0x18, size: 32, reset: 0x000030DB, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FMCEN
rw 		NBLSET
rw 		CCLKEN
rw 		CBURSTRW
rw 		CPSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNCWAIT
rw 		EXTMOD
rw 		WAITEN
rw 		WREN
rw 		WAITCFG
rw 		WAITPOL
rw 		BURSTEN
rw 		FACCEN
rw 		MWID
rw 		MTYP
rw 		MUXEN
rw 		MBKEN
rw
Toggle fields

MBKEN

Bit 0: MBKEN.

MUXEN

Bit 1: MUXEN.

MTYP

Bits 2-3: MTYP.

MWID

Bits 4-5: MWID.

FACCEN

Bit 6: FACCEN.

BURSTEN

Bit 8: BURSTEN.

WAITPOL

Bit 9: WAITPOL.

WAITCFG

Bit 11: WAITCFG.

WREN

Bit 12: WREN.

WAITEN

Bit 13: WAITEN.

EXTMOD

Bit 14: EXTMOD.

ASYNCWAIT

Bit 15: ASYNCWAIT.

CPSIZE

Bits 16-18: CPSIZE.

CBURSTRW

Bit 19: CBURSTRW.

CCLKEN

Bit 20: CCLKEN.

NBLSET

Bits 22-23: NBLSET.

FMCEN

Bit 31: FMCEN.

BTR4

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, two registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers).

Offset: 0x1c, size: 32, reset: 0x0FFFFFFF, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		DATLAT
rw 		CLKDIV
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

CLKDIV

Bits 20-23: CLKDIV.

DATLAT

Bits 24-27: DATLAT.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

PCSCNTR

This register contains the PSRAM chip select counter value for synchronous mode. The chip select counter is common to all banks and can be enabled separately on each bank. During PSRAM read or write accesses, this value is loaded into a timer which is decremented using the fmc_ker_ck while the NE signal is held low. When the timer reaches 0, the PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh and restarts a new access. The programmed counter value guarantees a maximum NE pulse width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts decrementing each time a new access is started by a transition of NE from high to low. h

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB4EN
rw 		CNTB3EN
rw 		CNTB2EN
rw 		CNTB1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT
rw
Toggle fields

CSCOUNT

Bits 0-15: CSCOUNT.

CNTB1EN

Bit 16: CNTB1EN.

CNTB2EN

Bit 17: CNTB2EN.

CNTB3EN

Bit 18: CNTB3EN.

CNTB4EN

Bit 19: CNTB4EN.

PCR

NAND Flash Programmable control register

Offset: 0x80, size: 32, reset: 0x0007FE08, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WEN
rw 		BCHECC
rw 		TCEH
rw 		ECCSS
rw 		TAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR
rw 		TCLR
rw 		ECCALG
rw 		ECCEN
rw 		PWID
rw 		PBKEN
rw 		PWAITEN
rw
Toggle fields

PWAITEN

Bit 1: PWAITEN.

PBKEN

Bit 2: PBKEN.

PWID

Bits 4-5: PWID.

ECCEN

Bit 6: ECCEN.

ECCALG

Bit 8: ECCALG.

TCLR

Bits 9-12: TCLR.

TAR

Bits 13-16: TAR.

ECCSS

Bits 17-19: ECCSS.

TCEH

Bits 20-23: TCEH.

BCHECC

Bit 24: BCHECC.

WEN

Bit 25: WEN.

SR

This register contains information about the AXI interface isolation status and the NAND write requests status. The FMC has to be disabled before modifying some registers. As requests might be pending, it is necessary to wait till the AXI interface is stable and the core of the block is totally isolated from its AXI interface before reconfiguring the registers. The PEF and PNWEF bits indicate the status of the pipe. If Hamming algorithm is used, the ECC is calculated while data are written to the memory. To read the correct ECC, the software must consequently wait untill no write request to the NAND controller are pending, by polling PEF and NWRF bits.

Offset: 0x84, size: 32, reset: 0x00000040, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NWRF
r 		PEF
r 		ISOST
r
Toggle fields

ISOST

Bits 0-1: ISOST.

PEF

Bit 4: PEF.

NWRF

Bit 6: NWRF.

PMEM

The FMC_PMEM read/write register contains NAND Flash memory bank timing information. This information is used to access the NAND Flash common memory space for command, address write accesses or data read/write accesses.

Offset: 0x88, size: 32, reset: 0x0A0A0A0A, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ
rw 		MEMHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT
rw 		MEMSET
rw
Toggle fields

MEMSET

Bits 0-7: MEMSET.

MEMWAIT

Bits 8-15: MEMWAIT.

MEMHOLD

Bits 16-23: MEMHOLD.

MEMHIZ

Bits 24-31: MEMHIZ.

PATT

The FMC_PATT read/write register contains NAND Flash memory bank timing information. It is used for 8-bit accesses to the NAND Flash attribute memory space during the last address write access when the timing differs from previous accesses (for Ready/Busy management, refer to Section25.8.5: NAND Flash prewait function).

Offset: 0x8c, size: 32, reset: 0x0A0A0A0A, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ
rw 		ATTHOLD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT
rw 		ATTSET
rw
Toggle fields

ATTSET

Bits 0-7: ATTSET.

ATTWAIT

Bits 8-15: ATTWAIT.

ATTHOLD

Bits 16-23: ATTHOLD.

ATTHIZ

Bits 24-31: ATTHIZ.

HPR

This register is used during read accesses in conjunction with the FMC sequencer. It contains the current error correction code value computed by the FMC NAND controller Hamming module. When the FMC sequencer reads data from a NAND Flash memory page at the correct address, the data read are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area and stored in the and the FMC_HPR, to determine whether a page is valid, and to correct it otherwise. The FMC_HPR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HPR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HPR
r
Toggle fields

HPR

Bits 0-31: HPR.

HECCR

This register contain the current error correction code value computed by the FMC NAND controller Hamming module.When the CPU reads/writes data from/to a NAND Flash memory page at the correct address (refer to Section25.8.6: NAND ECC controller), the data read/written from/to the NAND Flash memory are automatically processed by the Hamming computation module. When X bytes have been read (according to the sector size ECCSS field in the FMC_PCR register), the CPU must read the computed ECC value from the FMC_HECCR register. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and to correct it otherwise. The FMC_HECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HECC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HECC
r
Toggle fields

HECC

Bits 0-31: HECC.

BWTR1

This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x104, size: 32, reset: 0x000FFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

BWTR2

This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x10c, size: 32, reset: 0x000FFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

BWTR3

This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x114, size: 32, reset: 0x000FFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

BWTR4

This register contains the control information of each memory bank. It is used for SRAMs, FRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Offset: 0x11c, size: 32, reset: 0x000FFFFF, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD
rw 		ACCMOD
rw 		BUSTURN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST
rw 		ADDHLD
rw 		ADDSET
rw
Toggle fields

ADDSET

Bits 0-3: ADDSET.

ADDHLD

Bits 4-7: ADDHLD.

DATAST

Bits 8-15: DATAST.

BUSTURN

Bits 16-19: BUSTURN.

ACCMOD

Bits 28-29: ACCMOD.

DATAHLD

Bits 30-31: DATAHLD.

CSQCR

FMC NAND Command Sequencer Control Register

Offset: 0x200, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSQSTART
w
Toggle fields

CSQSTART

Bit 0: CSQSTART.

CSQCFGR1

FMC NAND Command Sequencer Configuration Register 1

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMD2T
rw 		CMD1T
rw 		CMD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD1
rw 		ACYNBR
rw 		DMADEN
rw 		CMD2EN
rw
Toggle fields

CMD2EN

Bit 1: CMD2EN.

DMADEN

Bit 2: DMADEN.

ACYNBR

Bits 4-6: ACYNBR.

CMD1

Bits 8-15: CMD1.

CMD2

Bits 16-23: CMD2.

CMD1T

Bit 24: CMD1T.

CMD2T

Bit 25: CMD2T.

CSQCFGR2

This register is used to configure the command sequencer to issue random read/ write commands to read/ write data by sector and automatically read/write data from NAND Flash memory at a programmable address offset. This is useful when performing a sector read/write operation followed by an ECC read/write operation in the NAND Flash spare area.The command sequencer generates the random commands untill all the sectors are read/written. .

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RCMD2T
rw 		RCMD1T
rw 		RCMD2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCMD1
rw 		DMASEN
rw 		RCMD2EN
rw 		SQSDTEN
rw
Toggle fields

SQSDTEN

Bit 0: SQSDTEN.

RCMD2EN

Bit 1: RCMD2EN.

DMASEN

Bit 2: DMASEN.

RCMD1

Bits 8-15: RCMD1.

RCMD2

Bits 16-23: RCMD2.

RCMD1T

Bit 24: RCMD1T.

RCMD2T

Bit 25: RCMD2T.

CSQCFGR3

FMC NAND sequencer configuration register 3

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RAC2T
rw 		RAC1T
rw 		SDT
rw 		AC5T
rw 		AC4T
rw 		AC3T
rw 		AC2T
rw 		AC1T
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SNBR
rw
Toggle fields

SNBR

Bits 8-13: SNBR.

AC1T

Bit 16: AC1T.

AC2T

Bit 17: AC2T.

AC3T

Bit 18: AC3T.

AC4T

Bit 19: AC4T.

AC5T

Bit 20: AC5T.

SDT

Bit 21: SDT.

RAC1T

Bit 22: RAC1T.

RAC2T

Bit 23: RAC2T.

CSQAR1

This register is used to define the value of address cycles 1 to 4 to be issued by the command sequencer.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDC4
rw 		ADDC3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDC2
rw 		ADDC1
rw
Toggle fields

ADDC1

Bits 0-7: ADDC1.

ADDC2

Bits 8-15: ADDC2.

ADDC3

Bits 16-23: ADDC3.

ADDC4

Bits 24-31: ADDC4.

CSQAR2

This register is used to program the fifth address cycle and the address offset in spare area. It also selects the chip enable.

Offset: 0x214, size: 32, reset: 0x00020000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NANDCEN1
rw 		NANDCEN0
rw 		ADDC5
rw
Toggle fields

ADDC5

Bits 0-7: ADDC5.

NANDCEN0

Bit 10: NANDCEN0.

NANDCEN1

Bit 11: NANDCEN1.

SAO

Bits 16-31: SAO.

CSQIER

FMC NAND Command Sequencer Interrupt Enable Register

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDTCIE
rw 		SUEIE
rw 		SEIE
rw 		SCIE
rw 		TCIE
rw
Toggle fields

TCIE

Bit 0: TCIE.

SCIE

Bit 1: SCIE.

SEIE

Bit 2: SEIE.

SUEIE

Bit 3: SUEIE.

CMDTCIE

Bit 4: CMDTCIE.

CSQISR

FMC NAND Command Sequencer Interrupt Status Register

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDTCF
rw 		SUEF
rw 		SEF
rw 		SCF
rw 		TCF
rw
Toggle fields

TCF

Bit 0: TCF.

SCF

Bit 1: SCF.

SEF

Bit 2: SEF.

SUEF

Bit 3: SUEF.

CMDTCF

Bit 4: CMDTCF.

CSQICR

FMC NAND Command Sequencer Interrupt Clear Register

Offset: 0x228, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCMDTCF
w 		CSUEF
w 		CSEF
w 		CSCF
w 		CTCF
w
Toggle fields

CTCF

Bit 0: CTCF.

CSCF

Bit 1: CSCF.

CSEF

Bit 2: CSEF.

CSUEF

Bit 3: CSUEF.

CCMDTCF

Bit 4: CCMDTCF.

CSQEMSR

This register holds a sector error mapping status when the whole transfer is complete.

Offset: 0x230, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEM
r
Toggle fields

SEM

Bits 0-15: SEM.

BCHIER

FMC BCH Interrupt enable register

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPBRIE
rw 		DSRIE
rw 		DEFIE
rw 		DERIE
rw 		DUEIE
rw
Toggle fields

DUEIE

Bit 0: DUEIE.

DERIE

Bit 1: DERIE.

DEFIE

Bit 2: DEFIE.

DSRIE

Bit 3: DSRIE.

EPBRIE

Bit 4: EPBRIE.

BCHISR

This register holds the status of BCH encoder/decoder after processing each sector. When the sequencer is used, this register is automatically cleared.

Offset: 0x254, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPBRF
r 		DSRF
r 		DEFF
r 		DERF
r 		DUEF
r
Toggle fields

DUEF

Bit 0: DUEF.

DERF

Bit 1: DERF.

DEFF

Bit 2: DEFF.

DSRF

Bit 3: DSRF.

EPBRF

Bit 4: EPBRF.

BCHICR

FMC BCH Interrupt Clear Register

Offset: 0x258, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CEPBRF
w 		CDSRF
w 		CDEFF
w 		CDERF
w 		CDUEF
w
Toggle fields

CDUEF

Bit 0: CDUEF.

CDERF

Bit 1: CDERF.

CDEFF

Bit 2: CDEFF.

CDSRF

Bit 3: CDSRF.

CEPBRF

Bit 4: CEPBRF.

BCHPBR1

These registers contain the BCH parity bits (BCHPB). For the BCH 4-bit, only BCHPB[51:0] are significant and for the BCH 8-bit BCHPB[103:0] are significant.

Offset: 0x260, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCHPB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCHPB
r
Toggle fields

BCHPB

Bits 0-31: BCHPB.

BCHPBR2

FMC BCH Parity Bits Register 2

Offset: 0x264, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCHPB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCHPB
r
Toggle fields

BCHPB

Bits 0-31: BCHPB.

BCHPBR3

FMC BCH Parity Bits Register 3

Offset: 0x268, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCHPB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCHPB
r
Toggle fields

BCHPB

Bits 0-31: BCHPB.

BCHPBR4

FMC BCH Parity Bits Register 4

Offset: 0x26c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCHPB
r
Toggle fields

BCHPB

Bits 0-7: BCHPB.

BCHDSR0

This register contains some fields already available in other registers but that require to be saved when error correction is performed on several sectors at a time (for example a whole NAND Flash page). This allows a DMA channel to transfer the content of FMC_BCHDSR0..4 to a decoding status buffer. .

Offset: 0x27c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEN
r 		DEF
r 		DUE
r
Toggle fields

DUE

Bit 0: DUE.

DEF

Bit 1: DEF.

DEN

Bits 4-7: DEN.

BCHDSR1

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors

Offset: 0x280, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBP2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBP1
r
Toggle fields

EBP1

Bits 0-12: EBP1.

EBP2

Bits 16-28: EBP2.

BCHDSR2

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 3rd and 4th error bits in EBP3 and EPB4 fields, respectively.

Offset: 0x284, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBP4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBP3
r
Toggle fields

EBP3

Bits 0-12: EBP3.

EBP4

Bits 16-28: EBP4.

BCHDSR3

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors.

Offset: 0x288, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBP6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBP5
r
Toggle fields

EBP5

Bits 0-12: EBP5.

EBP6

Bits 16-28: EBP6.

BCHDSR4

The maximum error correction capability of the BCH block embedded in the FMC is 8 errors. This register contains the positions of the 7th and 8th error bits in EBP7 and EPB8 fields, respectively. .

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EBP8
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EBP7
r
Toggle fields

EBP7

Bits 0-12: EBP7.

EBP8

Bits 16-28: EBP8.

HWCFGR2

FMC Hardware configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00DC8762, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDRAM2_BASE
r 		SDRAM1_BASE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAND_BASE
r 		SDRAM_RBASE
r 		NOR_BASE
r 		RD_LN2DPTH
r
Toggle fields

RD_LN2DPTH

Bits 0-3: RD_LN2DPTH.

NOR_BASE

Bits 4-7: NOR_BASE.

SDRAM_RBASE

Bits 8-11: SDRAM_RBASE.

NAND_BASE

Bits 12-15: NAND_BASE.

SDRAM1_BASE

Bits 16-19: SDRAM1_BASE.

SDRAM2_BASE

Bits 20-23: SDRAM2_BASE.

HWCFGR1

FMC Hardware configuration register 1

Offset: 0x3f0, size: 32, reset: 0x2232B011, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RA_LN2DPTH
r 		WR_LN2DPTH
r 		WD_LN2DPTH
r 		WA_LN2DPTH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID_SIZE
r 		SDRAM_SEL
r 		NAND_ECC
r 		NAND_SEL
r
Toggle fields

NAND_SEL

Bit 0: NAND_SEL.

NAND_ECC

Bit 4: NAND_ECC.

SDRAM_SEL

Bit 8: SDRAM_SEL.

ID_SIZE

Bits 12-15: ID_SIZE.

WA_LN2DPTH

Bits 16-19: WA_LN2DPTH.

WD_LN2DPTH

Bits 20-23: WD_LN2DPTH.

WR_LN2DPTH

Bits 24-27: WR_LN2DPTH.

RA_LN2DPTH

Bits 28-31: RA_LN2DPTH.

VERR

FMC Version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

FMC Identification register

Offset: 0x3f8, size: 32, reset: 0x00140001, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

FMC Size Identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

GICC

0xa0022000: GICC

13/35 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTLR
0x4 PMR
0x8 BPR
0xc IAR
0x10 EOIR
0x14 RPR
0x18 HPPIR
0x1c ABPR
0x20 AIAR
0x24 AEOIR
0x28 AHPPIR
0xd0 APR0
0xe0 NSAPR0
0xfc IIDR
0x1000 DIR
Toggle registers

CTLR

GICC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOIMODENS
rw 		EOIMODES
rw 		IRQBYPDISGRP1
rw 		FIQBYPDISGRP1
rw 		IRQBYPDISGRP0
rw 		FIQBYPDISGRP0
rw 		CBPR
rw 		FIQEN
rw 		ACKCTL
rw 		ENABLEGRP1
rw 		ENABLEGRP0
rw
Toggle fields

ENABLEGRP0

Bit 0: ENABLEGRP0.

ENABLEGRP1

Bit 1: ENABLEGRP1.

ACKCTL

Bit 2: ACKCTL.

FIQEN

Bit 3: FIQEN.

CBPR

Bit 4: CBPR.

FIQBYPDISGRP0

Bit 5: FIQBYPDISGRP0.

IRQBYPDISGRP0

Bit 6: IRQBYPDISGRP0.

FIQBYPDISGRP1

Bit 7: FIQBYPDISGRP1.

IRQBYPDISGRP1

Bit 8: IRQBYPDISGRP1.

EOIMODES

Bit 9: EOIMODES.

EOIMODENS

Bit 10: EOIMODENS.

PMR

GICC input priority mask register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY
rw
Toggle fields

PRIORITY

Bits 3-7: PRIORITY.

BPR

GICC binary point register

Offset: 0x8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BINARY_POINT
rw
Toggle fields

BINARY_POINT

Bits 0-2: BINARY_POINT.

IAR

GICC interrupt acknowledge register

Offset: 0xc, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		INTERRUPT_ID
r
Toggle fields

INTERRUPT_ID

Bits 0-9: INTERRUPT_ID.

CPUID

Bit 10: CPUID.

EOIR

GICC end of interrupt register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
w 		EOIINTID
w
Toggle fields

EOIINTID

Bits 0-9: EOIINTID.

CPUID

Bit 10: CPUID.

RPR

GICC running priority register

Offset: 0x14, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY
r
Toggle fields

PRIORITY

Bits 3-7: PRIORITY.

HPPIR

GICC highest priority pending interrupt register

Offset: 0x18, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		PENDINTID
r
Toggle fields

PENDINTID

Bits 0-9: PENDINTID.

CPUID

Bit 10: CPUID.

ABPR

GICC_ABPR is an alias of the non-secure GICC_BPR. When GICC_CTLR.CBPR is set to 0, a secure access to this register is equivalent to a non-secure access to GICC_BPR.

Offset: 0x1c, size: 32, reset: 0x00000003, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BINARY_POINT
rw
Toggle fields

BINARY_POINT

Bits 0-2: BINARY_POINT.

AIAR

GICC_AIAR is an alias of the non-secure view of GICC_IAR. A secure access to this register is identical to a non-secure access to GICC_IAR.

Offset: 0x20, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		INTERRUPT_ID
r
Toggle fields

INTERRUPT_ID

Bits 0-9: INTERRUPT_ID.

CPUID

Bit 10: CPUID.

AEOIR

GICC_AEOIR is an alias of the Non-secure GICC_EOIR. A secure access to this register is similar to a non-secure access to GICC_EOIR, except that the GICC_CTLR.EOImodeS bit is used.

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
w 		EOIINTID
w
Toggle fields

EOIINTID

Bits 0-9: EOIINTID.

CPUID

Bit 10: CPUID.

AHPPIR

ICC_AHPPIR is an alias of the non-secure GICC_HPPIR. A secure access to this register is equivalent to a non-secure access to GICC_HPPIR.

Offset: 0x28, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		PENDINTID
r
Toggle fields

PENDINTID

Bits 0-9: PENDINTID.

CPUID

Bit 10: CPUID.

APR0

GICC active priority register

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APR0
rw
Toggle fields

APR0

Bits 0-31: APR0.

NSAPR0

GICC non-secure active priority register

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAPR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAPR0
rw
Toggle fields

NSAPR0

Bits 0-31: NSAPR0.

IIDR

GICC interface identification register

Offset: 0xfc, size: 32, reset: 0x0102143B, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCTID
r 		ARCH
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVISION
r 		IMPLEMENTER
r
Toggle fields

IMPLEMENTER

Bits 0-11: IMPLEMENTER.

REVISION

Bits 12-15: REVISION.

ARCH

Bits 16-19: ARCH.

PRODUCTID

Bits 20-31: PRODUCTID.

DIR

GICC deactivate interrupt register

Offset: 0x1000, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
w 		INTERRUPT_ID
w
Toggle fields

INTERRUPT_ID

Bits 0-9: INTERRUPT_ID.

CPUID

Bit 10: CPUID.

GICD

0xa0021000: GICD

66/999 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTLR
0x4 TYPER
0x8 IIDR
0x80 IGROUPR0
0x84 IGROUPR1
0x88 IGROUPR2
0x8c IGROUPR3
0x90 IGROUPR4
0x94 IGROUPR5
0x98 IGROUPR6
0x9c IGROUPR7
0xa0 IGROUPR8
0x100 ISENABLER0
0x104 ISENABLER1
0x108 ISENABLER2
0x10c ISENABLER3
0x110 ISENABLER4
0x114 ISENABLER5
0x118 ISENABLER6
0x11c ISENABLER7
0x120 ISENABLER8
0x180 ICENABLER0
0x184 ICENABLER1
0x188 ICENABLER2
0x18c ICENABLER3
0x190 ICENABLER4
0x194 ICENABLER5
0x198 ICENABLER6
0x19c ICENABLER7
0x1a0 ICENABLER8
0x200 ISPENDR0
0x204 ISPENDR1
0x208 ISPENDR2
0x20c ISPENDR3
0x210 ISPENDR4
0x214 ISPENDR5
0x218 ISPENDR6
0x21c ISPENDR7
0x220 ISPENDR8
0x280 ICPENDR0
0x284 ICPENDR1
0x288 ICPENDR2
0x28c ICPENDR3
0x290 ICPENDR4
0x294 ICPENDR5
0x298 ICPENDR6
0x29c ICPENDR7
0x2a0 ICPENDR8
0x300 ISACTIVER0
0x304 ISACTIVER1
0x308 ISACTIVER2
0x30c ISACTIVER3
0x310 ISACTIVER4
0x314 ISACTIVER5
0x318 ISACTIVER6
0x31c ISACTIVER7
0x320 ISACTIVER8
0x380 ICACTIVER0
0x384 ICACTIVER1
0x388 ICACTIVER2
0x38c ICACTIVER3
0x390 ICACTIVER4
0x394 ICACTIVER5
0x398 ICACTIVER6
0x39c ICACTIVER7
0x3a0 ICACTIVER8
0x400 IPRIORITYR0
0x404 IPRIORITYR1
0x408 IPRIORITYR2
0x40c IPRIORITYR3
0x410 IPRIORITYR4
0x414 IPRIORITYR5
0x418 IPRIORITYR6
0x41c IPRIORITYR7
0x420 IPRIORITYR8
0x424 IPRIORITYR9
0x428 IPRIORITYR10
0x42c IPRIORITYR11
0x430 IPRIORITYR12
0x434 IPRIORITYR13
0x438 IPRIORITYR14
0x43c IPRIORITYR15
0x440 IPRIORITYR16
0x444 IPRIORITYR17
0x448 IPRIORITYR18
0x44c IPRIORITYR19
0x450 IPRIORITYR20
0x454 IPRIORITYR21
0x458 IPRIORITYR22
0x45c IPRIORITYR23
0x460 IPRIORITYR24
0x464 IPRIORITYR25
0x468 IPRIORITYR26
0x46c IPRIORITYR27
0x470 IPRIORITYR28
0x474 IPRIORITYR29
0x478 IPRIORITYR30
0x47c IPRIORITYR31
0x480 IPRIORITYR32
0x484 IPRIORITYR33
0x488 IPRIORITYR34
0x48c IPRIORITYR35
0x490 IPRIORITYR36
0x494 IPRIORITYR37
0x498 IPRIORITYR38
0x49c IPRIORITYR39
0x4a0 IPRIORITYR40
0x4a4 IPRIORITYR41
0x4a8 IPRIORITYR42
0x4ac IPRIORITYR43
0x4b0 IPRIORITYR44
0x4b4 IPRIORITYR45
0x4b8 IPRIORITYR46
0x4bc IPRIORITYR47
0x4c0 IPRIORITYR48
0x4c4 IPRIORITYR49
0x4c8 IPRIORITYR50
0x4cc IPRIORITYR51
0x4d0 IPRIORITYR52
0x4d4 IPRIORITYR53
0x4d8 IPRIORITYR54
0x4dc IPRIORITYR55
0x4e0 IPRIORITYR56
0x4e4 IPRIORITYR57
0x4e8 IPRIORITYR58
0x4ec IPRIORITYR59
0x4f0 IPRIORITYR60
0x4f4 IPRIORITYR61
0x4f8 IPRIORITYR62
0x4fc IPRIORITYR63
0x500 IPRIORITYR64
0x504 IPRIORITYR65
0x508 IPRIORITYR66
0x50c IPRIORITYR67
0x510 IPRIORITYR68
0x514 IPRIORITYR69
0x518 IPRIORITYR70
0x51c IPRIORITYR71
0x800 ITARGETSR0
0x804 ITARGETSR1
0x808 ITARGETSR2
0x80c ITARGETSR3
0x810 ITARGETSR4
0x814 ITARGETSR5
0x818 ITARGETSR6
0x81c ITARGETSR7
0x820 ITARGETSR8
0x824 ITARGETSR9
0x828 ITARGETSR10
0x82c ITARGETSR11
0x830 ITARGETSR12
0x834 ITARGETSR13
0x838 ITARGETSR14
0x83c ITARGETSR15
0x840 ITARGETSR16
0x844 ITARGETSR17
0x848 ITARGETSR18
0x84c ITARGETSR19
0x850 ITARGETSR20
0x854 ITARGETSR21
0x858 ITARGETSR22
0x85c ITARGETSR23
0x860 ITARGETSR24
0x864 ITARGETSR25
0x868 ITARGETSR26
0x86c ITARGETSR27
0x870 ITARGETSR28
0x874 ITARGETSR29
0x878 ITARGETSR30
0x87c ITARGETSR31
0x880 ITARGETSR32
0x884 ITARGETSR33
0x888 ITARGETSR34
0x88c ITARGETSR35
0x890 ITARGETSR36
0x894 ITARGETSR37
0x898 ITARGETSR38
0x89c ITARGETSR39
0x8a0 ITARGETSR40
0x8a4 ITARGETSR41
0x8a8 ITARGETSR42
0x8ac ITARGETSR43
0x8b0 ITARGETSR44
0x8b4 ITARGETSR45
0x8b8 ITARGETSR46
0x8bc ITARGETSR47
0x8c0 ITARGETSR48
0x8c4 ITARGETSR49
0x8c8 ITARGETSR50
0x8cc ITARGETSR51
0x8d0 ITARGETSR52
0x8d4 ITARGETSR53
0x8d8 ITARGETSR54
0x8dc ITARGETSR55
0x8e0 ITARGETSR56
0x8e4 ITARGETSR57
0x8e8 ITARGETSR58
0x8ec ITARGETSR59
0x8f0 ITARGETSR60
0x8f4 ITARGETSR61
0x8f8 ITARGETSR62
0x8fc ITARGETSR63
0x900 ITARGETSR64
0x904 ITARGETSR65
0x908 ITARGETSR66
0x90c ITARGETSR67
0x910 ITARGETSR68
0x914 ITARGETSR69
0x918 ITARGETSR70
0x91c ITARGETSR71
0xc00 ICFGR0
0xc04 ICFGR1
0xc08 ICFGR2
0xc0c ICFGR3
0xc10 ICFGR4
0xc14 ICFGR5
0xc18 ICFGR6
0xc1c ICFGR7
0xc20 ICFGR8
0xc24 ICFGR9
0xc28 ICFGR10
0xc2c ICFGR11
0xc30 ICFGR12
0xc34 ICFGR13
0xc38 ICFGR14
0xc3c ICFGR15
0xc40 ICFGR16
0xc44 ICFGR17
0xd00 PPISR
0xd08 SPISR1
0xd0c SPISR2
0xd10 SPISR3
0xd14 SPISR4
0xd18 SPISR5
0xd1c SPISR6
0xd20 SPISR7
0xf00 SGIR
0xf10 CPENDSGIR0
0xf14 CPENDSGIR1
0xf18 CPENDSGIR2
0xf1c CPENDSGIR3
0xf20 SPENDSGIR0
0xf24 SPENDSGIR1
0xf28 SPENDSGIR2
0xf2c SPENDSGIR3
0xfd0 PIDR4
0xfd4 PIDR5
0xfd8 PIDR6
0xfdc PIDR7
0xfe0 PIDR0
0xfe4 PIDR1
0xfe8 PIDR2
0xfec PIDR3
0xff0 CIDR0
0xff4 CIDR1
0xff8 CIDR2
0xffc CIDR3
Toggle registers

CTLR

GICD control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENABLEGRP1
rw 		ENABLEGRP0
rw
Toggle fields

ENABLEGRP0

Bit 0: ENABLEGRP0.

ENABLEGRP1

Bit 1: ENABLEGRP1.

TYPER

GICD interrupt controller type register

Offset: 0x4, size: 32, reset: 0x0000FC28, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSPI
r 		SECURITYEXTN
r 		CPUNUMBER
r 		ITLINESNUMBER
r
Toggle fields

ITLINESNUMBER

Bits 0-4: ITLINESNUMBER.

CPUNUMBER

Bits 5-7: CPUNUMBER.

SECURITYEXTN

Bit 10: SECURITYEXTN.

LSPI

Bits 11-15: LSPI.

IIDR

GICD implementer identification register

Offset: 0x8, size: 32, reset: 0x0100143B, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCTID
r 		REVISION
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VARIANT
r 		IMPLEMENTER
r
Toggle fields

IMPLEMENTER

Bits 0-11: IMPLEMENTER.

VARIANT

Bits 12-15: VARIANT.

REVISION

Bits 16-19: REVISION.

PRODUCTID

Bits 24-31: PRODUCTID.

IGROUPR0

For interrupts ID

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR0
rw
Toggle fields

IGROUPR0

Bits 0-31: IGROUPR0.

IGROUPR1

For interrupts ID

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR1
rw
Toggle fields

IGROUPR1

Bits 0-31: IGROUPR1.

IGROUPR2

For interrupts ID

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR2
rw
Toggle fields

IGROUPR2

Bits 0-31: IGROUPR2.

IGROUPR3

For interrupts ID = x*32 to ID = x*32+31

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR3
rw
Toggle fields

IGROUPR3

Bits 0-31: IGROUPR3.

IGROUPR4

For interrupts ID = x*32 to ID = x*32+31

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR4
rw
Toggle fields

IGROUPR4

Bits 0-31: IGROUPR4.

IGROUPR5

For interrupts ID

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR5
rw
Toggle fields

IGROUPR5

Bits 0-31: IGROUPR5.

IGROUPR6

For interrupts ID

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR6
rw
Toggle fields

IGROUPR6

Bits 0-31: IGROUPR6.

IGROUPR7

For interrupts ID

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR7
rw
Toggle fields

IGROUPR7

Bits 0-31: IGROUPR7.

IGROUPR8

For interrupts ID

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IGROUPR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IGROUPR8
rw
Toggle fields

IGROUPR8

Bits 0-31: IGROUPR8.

ISENABLER0

For interrupts ID = 0 to ID = 31

Offset: 0x100, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER0
rw
Toggle fields

ISENABLER0

Bits 0-31: ISENABLER0.

ISENABLER1

For interrupts ID

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER1
rw
Toggle fields

ISENABLER1

Bits 0-31: ISENABLER1.

ISENABLER2

For interrupts ID

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER2
rw
Toggle fields

ISENABLER2

Bits 0-31: ISENABLER2.

ISENABLER3

For interrupts ID

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER3
rw
Toggle fields

ISENABLER3

Bits 0-31: ISENABLER3.

ISENABLER4

For interrupts ID

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER4
rw
Toggle fields

ISENABLER4

Bits 0-31: ISENABLER4.

ISENABLER5

For interrupts ID

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER5
rw
Toggle fields

ISENABLER5

Bits 0-31: ISENABLER5.

ISENABLER6

For interrupts ID

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER6
rw
Toggle fields

ISENABLER6

Bits 0-31: ISENABLER6.

ISENABLER7

For interrupts ID

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER7
rw
Toggle fields

ISENABLER7

Bits 0-31: ISENABLER7.

ISENABLER8

For interrupts ID

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISENABLER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISENABLER8
rw
Toggle fields

ISENABLER8

Bits 0-31: ISENABLER8.

ICENABLER0

For interrupts ID = 0 to ID = 31

Offset: 0x180, size: 32, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER0
rw
Toggle fields

ICENABLER0

Bits 0-31: ICENABLER0.

ICENABLER1

For interrupts ID

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER1
rw
Toggle fields

ICENABLER1

Bits 0-31: ICENABLER1.

ICENABLER2

For interrupts ID

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER2
rw
Toggle fields

ICENABLER2

Bits 0-31: ICENABLER2.

ICENABLER3

For interrupts ID

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER3
rw
Toggle fields

ICENABLER3

Bits 0-31: ICENABLER3.

ICENABLER4

For interrupts ID

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER4
rw
Toggle fields

ICENABLER4

Bits 0-31: ICENABLER4.

ICENABLER5

For interrupts ID

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER5
rw
Toggle fields

ICENABLER5

Bits 0-31: ICENABLER5.

ICENABLER6

For interrupts ID

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER6
rw
Toggle fields

ICENABLER6

Bits 0-31: ICENABLER6.

ICENABLER7

For interrupts ID

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER7
rw
Toggle fields

ICENABLER7

Bits 0-31: ICENABLER7.

ICENABLER8

For interrupts ID

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICENABLER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICENABLER8
rw
Toggle fields

ICENABLER8

Bits 0-31: ICENABLER8.

ISPENDR0

For interrupts ID

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR0
rw
Toggle fields

ISPENDR0

Bits 0-31: ISPENDR0.

ISPENDR1

For interrupts ID

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR1
rw
Toggle fields

ISPENDR1

Bits 0-31: ISPENDR1.

ISPENDR2

For interrupts ID

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR2
rw
Toggle fields

ISPENDR2

Bits 0-31: ISPENDR2.

ISPENDR3

For interrupts ID

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR3
rw
Toggle fields

ISPENDR3

Bits 0-31: ISPENDR3.

ISPENDR4

For interrupts ID

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR4
rw
Toggle fields

ISPENDR4

Bits 0-31: ISPENDR4.

ISPENDR5

For interrupts ID

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR5
rw
Toggle fields

ISPENDR5

Bits 0-31: ISPENDR5.

ISPENDR6

For interrupts ID

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR6
rw
Toggle fields

ISPENDR6

Bits 0-31: ISPENDR6.

ISPENDR7

For interrupts ID

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR7
rw
Toggle fields

ISPENDR7

Bits 0-31: ISPENDR7.

ISPENDR8

For interrupts ID

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISPENDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISPENDR8
rw
Toggle fields

ISPENDR8

Bits 0-31: ISPENDR8.

ICPENDR0

For interrupts ID

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR0
rw
Toggle fields

ICPENDR0

Bits 0-31: ICPENDR0.

ICPENDR1

For interrupts ID

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR1
rw
Toggle fields

ICPENDR1

Bits 0-31: ICPENDR1.

ICPENDR2

For interrupts ID

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR2
rw
Toggle fields

ICPENDR2

Bits 0-31: ICPENDR2.

ICPENDR3

For interrupts ID

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR3
rw
Toggle fields

ICPENDR3

Bits 0-31: ICPENDR3.

ICPENDR4

For interrupts ID

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR4
rw
Toggle fields

ICPENDR4

Bits 0-31: ICPENDR4.

ICPENDR5

For interrupts ID

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR5
rw
Toggle fields

ICPENDR5

Bits 0-31: ICPENDR5.

ICPENDR6

For interrupts ID

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR6
rw
Toggle fields

ICPENDR6

Bits 0-31: ICPENDR6.

ICPENDR7

For interrupts ID

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR7
rw
Toggle fields

ICPENDR7

Bits 0-31: ICPENDR7.

ICPENDR8

For interrupts ID

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICPENDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICPENDR8
rw
Toggle fields

ICPENDR8

Bits 0-31: ICPENDR8.

ISACTIVER0

For interrupts ID

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER0
rw
Toggle fields

ISACTIVER0

Bits 0-31: ISACTIVER0.

ISACTIVER1

For interrupts ID

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER1
rw
Toggle fields

ISACTIVER1

Bits 0-31: ISACTIVER1.

ISACTIVER2

For interrupts ID

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER2
rw
Toggle fields

ISACTIVER2

Bits 0-31: ISACTIVER2.

ISACTIVER3

For interrupts ID

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER3
rw
Toggle fields

ISACTIVER3

Bits 0-31: ISACTIVER3.

ISACTIVER4

For interrupts ID

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER4
rw
Toggle fields

ISACTIVER4

Bits 0-31: ISACTIVER4.

ISACTIVER5

For interrupts ID

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER5
rw
Toggle fields

ISACTIVER5

Bits 0-31: ISACTIVER5.

ISACTIVER6

For interrupts ID

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER6
rw
Toggle fields

ISACTIVER6

Bits 0-31: ISACTIVER6.

ISACTIVER7

For interrupts ID

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER7
rw
Toggle fields

ISACTIVER7

Bits 0-31: ISACTIVER7.

ISACTIVER8

For interrupts ID

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISACTIVER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISACTIVER8
rw
Toggle fields

ISACTIVER8

Bits 0-31: ISACTIVER8.

ICACTIVER0

For interrupts ID

Offset: 0x380, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER0
rw
Toggle fields

ICACTIVER0

Bits 0-31: ICACTIVER0.

ICACTIVER1

For interrupts ID

Offset: 0x384, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER1
rw
Toggle fields

ICACTIVER1

Bits 0-31: ICACTIVER1.

ICACTIVER2

For interrupts ID

Offset: 0x388, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER2
rw
Toggle fields

ICACTIVER2

Bits 0-31: ICACTIVER2.

ICACTIVER3

For interrupts ID

Offset: 0x38c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER3
rw
Toggle fields

ICACTIVER3

Bits 0-31: ICACTIVER3.

ICACTIVER4

For interrupts ID

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER4
rw
Toggle fields

ICACTIVER4

Bits 0-31: ICACTIVER4.

ICACTIVER5

For interrupts ID

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER5
rw
Toggle fields

ICACTIVER5

Bits 0-31: ICACTIVER5.

ICACTIVER6

For interrupts ID

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER6
rw
Toggle fields

ICACTIVER6

Bits 0-31: ICACTIVER6.

ICACTIVER7

For interrupts ID

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER7
rw
Toggle fields

ICACTIVER7

Bits 0-31: ICACTIVER7.

ICACTIVER8

For interrupts ID

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACTIVER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACTIVER8
rw
Toggle fields

ICACTIVER8

Bits 0-31: ICACTIVER8.

IPRIORITYR0

GICD interrupt priority register 0

Offset: 0x400, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR1

GICD interrupt priority register 1

Offset: 0x404, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR2

GICD interrupt priority register 2

Offset: 0x408, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR3

GICD interrupt priority register 3

Offset: 0x40c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR4

GICD interrupt priority register 4

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR5

GICD interrupt priority register 5

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR6

GICD interrupt priority register 6

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR7

GICD interrupt priority register 7

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR8

GICD interrupt priority register 8

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR9

GICD interrupt priority register 9

Offset: 0x424, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR10

GICD interrupt priority register 10

Offset: 0x428, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR11

GICD interrupt priority register 11

Offset: 0x42c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR12

GICD interrupt priority register 12

Offset: 0x430, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR13

GICD interrupt priority register 13

Offset: 0x434, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR14

GICD interrupt priority register 14

Offset: 0x438, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR15

GICD interrupt priority register 15

Offset: 0x43c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR16

GICD interrupt priority register 16

Offset: 0x440, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR17

GICD interrupt priority register 17

Offset: 0x444, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR18

GICD interrupt priority register 18

Offset: 0x448, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR19

GICD interrupt priority register 19

Offset: 0x44c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR20

GICD interrupt priority register 20

Offset: 0x450, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR21

GICD interrupt priority register 21

Offset: 0x454, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR22

GICD interrupt priority register 22

Offset: 0x458, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR23

GICD interrupt priority register 23

Offset: 0x45c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR24

GICD interrupt priority register 24

Offset: 0x460, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR25

GICD interrupt priority register 25

Offset: 0x464, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR26

GICD interrupt priority register 26

Offset: 0x468, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR27

GICD interrupt priority register 27

Offset: 0x46c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR28

GICD interrupt priority register 28

Offset: 0x470, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR29

GICD interrupt priority register 29

Offset: 0x474, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR30

GICD interrupt priority register 30

Offset: 0x478, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR31

GICD interrupt priority register 31

Offset: 0x47c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR32

GICD interrupt priority register 32

Offset: 0x480, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR33

GICD interrupt priority register 33

Offset: 0x484, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR34

GICD interrupt priority register 34

Offset: 0x488, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR35

GICD interrupt priority register 35

Offset: 0x48c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR36

GICD interrupt priority register 36

Offset: 0x490, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR37

GICD interrupt priority register 37

Offset: 0x494, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR38

GICD interrupt priority register 38

Offset: 0x498, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR39

GICD interrupt priority register 39

Offset: 0x49c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR40

GICD interrupt priority register 40

Offset: 0x4a0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR41

GICD interrupt priority register 41

Offset: 0x4a4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR42

GICD interrupt priority register 42

Offset: 0x4a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR43

GICD interrupt priority register 43

Offset: 0x4ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR44

GICD interrupt priority register 44

Offset: 0x4b0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR45

GICD interrupt priority register 45

Offset: 0x4b4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR46

GICD interrupt priority register 46

Offset: 0x4b8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR47

GICD interrupt priority register 47

Offset: 0x4bc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR48

GICD interrupt priority register 48

Offset: 0x4c0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR49

GICD interrupt priority register 49

Offset: 0x4c4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR50

GICD interrupt priority register 50

Offset: 0x4c8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR51

GICD interrupt priority register 51

Offset: 0x4cc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR52

GICD interrupt priority register 52

Offset: 0x4d0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR53

GICD interrupt priority register 53

Offset: 0x4d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR54

GICD interrupt priority register 54

Offset: 0x4d8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR55

GICD interrupt priority register 55

Offset: 0x4dc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR56

GICD interrupt priority register 56

Offset: 0x4e0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR57

GICD interrupt priority register 57

Offset: 0x4e4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR58

GICD interrupt priority register 58

Offset: 0x4e8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR59

GICD interrupt priority register 59

Offset: 0x4ec, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR60

GICD interrupt priority register 60

Offset: 0x4f0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR61

GICD interrupt priority register 61

Offset: 0x4f4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR62

GICD interrupt priority register 62

Offset: 0x4f8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR63

GICD interrupt priority register 63

Offset: 0x4fc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR64

GICD interrupt priority register 64

Offset: 0x500, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR65

GICD interrupt priority register 65

Offset: 0x504, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR66

GICD interrupt priority register 66

Offset: 0x508, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR67

GICD interrupt priority register 67

Offset: 0x50c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR68

GICD interrupt priority register 68

Offset: 0x510, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR69

GICD interrupt priority register 69

Offset: 0x514, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR70

GICD interrupt priority register 70

Offset: 0x518, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

IPRIORITYR71

GICD interrupt priority register 71

Offset: 0x51c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIORITY3
rw 		PRIORITY2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY1
rw 		PRIORITY0
rw
Toggle fields

PRIORITY0

Bits 3-7: PRIORITY0.

PRIORITY1

Bits 11-15: PRIORITY1.

PRIORITY2

Bits 19-23: PRIORITY2.

PRIORITY3

Bits 27-31: PRIORITY3.

ITARGETSR0

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x800, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR1

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x804, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR2

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x808, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR3

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x80c, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR4

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x810, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR5

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x814, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR6

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x818, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR7

For existing SGIs and PPIs, read of CPU targets field returns the number of the processor performing the read.

Offset: 0x81c, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
r 		CPU_TARGETS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
r 		CPU_TARGETS0
r
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR8

GICD interrupt processor target register 8

Offset: 0x820, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR9

GICD interrupt processor target register 9

Offset: 0x824, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR10

GICD interrupt processor target register 10

Offset: 0x828, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR11

GICD interrupt processor target register 11

Offset: 0x82c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR12

GICD interrupt processor target register 12

Offset: 0x830, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR13

GICD interrupt processor target register 13

Offset: 0x834, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR14

GICD interrupt processor target register 14

Offset: 0x838, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR15

GICD interrupt processor target register 15

Offset: 0x83c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR16

GICD interrupt processor target register 16

Offset: 0x840, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR17

GICD interrupt processor target register 17

Offset: 0x844, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR18

GICD interrupt processor target register 18

Offset: 0x848, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR19

GICD interrupt processor target register 19

Offset: 0x84c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR20

GICD interrupt processor target register 20

Offset: 0x850, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR21

GICD interrupt processor target register 21

Offset: 0x854, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR22

GICD interrupt processor target register 22

Offset: 0x858, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR23

GICD interrupt processor target register 23

Offset: 0x85c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR24

GICD interrupt processor target register 24

Offset: 0x860, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR25

GICD interrupt processor target register 25

Offset: 0x864, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR26

GICD interrupt processor target register 26

Offset: 0x868, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR27

GICD interrupt processor target register 27

Offset: 0x86c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR28

GICD interrupt processor target register 28

Offset: 0x870, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR29

GICD interrupt processor target register 29

Offset: 0x874, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR30

GICD interrupt processor target register 30

Offset: 0x878, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR31

GICD interrupt processor target register 31

Offset: 0x87c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR32

GICD interrupt processor target register 32

Offset: 0x880, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR33

GICD interrupt processor target register 33

Offset: 0x884, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR34

GICD interrupt processor target register 34

Offset: 0x888, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR35

GICD interrupt processor target register 35

Offset: 0x88c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR36

GICD interrupt processor target register 36

Offset: 0x890, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR37

GICD interrupt processor target register 37

Offset: 0x894, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR38

GICD interrupt processor target register 38

Offset: 0x898, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR39

GICD interrupt processor target register 39

Offset: 0x89c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR40

GICD interrupt processor target register 40

Offset: 0x8a0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR41

GICD interrupt processor target register 41

Offset: 0x8a4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR42

GICD interrupt processor target register 42

Offset: 0x8a8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR43

GICD interrupt processor target register 43

Offset: 0x8ac, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR44

GICD interrupt processor target register 44

Offset: 0x8b0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR45

GICD interrupt processor target register 45

Offset: 0x8b4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR46

GICD interrupt processor target register 46

Offset: 0x8b8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR47

GICD interrupt processor target register 47

Offset: 0x8bc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR48

GICD interrupt processor target register 48

Offset: 0x8c0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR49

GICD interrupt processor target register 49

Offset: 0x8c4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR50

GICD interrupt processor target register 50

Offset: 0x8c8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR51

GICD interrupt processor target register 51

Offset: 0x8cc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR52

GICD interrupt processor target register 52

Offset: 0x8d0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR53

GICD interrupt processor target register 53

Offset: 0x8d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR54

GICD interrupt processor target register 54

Offset: 0x8d8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR55

GICD interrupt processor target register 55

Offset: 0x8dc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR56

GICD interrupt processor target register 56

Offset: 0x8e0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR57

GICD interrupt processor target register 57

Offset: 0x8e4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR58

GICD interrupt processor target register 58

Offset: 0x8e8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR59

GICD interrupt processor target register 59

Offset: 0x8ec, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR60

GICD interrupt processor target register 60

Offset: 0x8f0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR61

GICD interrupt processor target register 61

Offset: 0x8f4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR62

GICD interrupt processor target register 62

Offset: 0x8f8, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR63

GICD interrupt processor target register 63

Offset: 0x8fc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR64

GICD interrupt processor target register 64

Offset: 0x900, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR65

GICD interrupt processor target register 65

Offset: 0x904, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR66

GICD interrupt processor target register 66

Offset: 0x908, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR67

GICD interrupt processor target register 67

Offset: 0x90c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR68

GICD interrupt processor target register 68

Offset: 0x910, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR69

GICD interrupt processor target register 69

Offset: 0x914, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR70

GICD interrupt processor target register 70

Offset: 0x918, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ITARGETSR71

GICD interrupt processor target register 71

Offset: 0x91c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CPU_TARGETS3
rw 		CPU_TARGETS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_TARGETS1
rw 		CPU_TARGETS0
rw
Toggle fields

CPU_TARGETS0

Bits 0-1: CPU_TARGETS0.

CPU_TARGETS1

Bits 8-9: CPU_TARGETS1.

CPU_TARGETS2

Bits 16-17: CPU_TARGETS2.

CPU_TARGETS3

Bits 24-25: CPU_TARGETS3.

ICFGR0

GICD interrupt configuration register

Offset: 0xc00, size: 32, reset: 0xAAAAAAAA, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR1

GICD interrupt configuration register

Offset: 0xc04, size: 32, reset: 0x55540000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR2

GICD interrupt configuration register 2

Offset: 0xc08, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR3

GICD interrupt configuration register 3

Offset: 0xc0c, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR4

GICD interrupt configuration register 4

Offset: 0xc10, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR5

GICD interrupt configuration register 5

Offset: 0xc14, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR6

GICD interrupt configuration register 6

Offset: 0xc18, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR7

GICD interrupt configuration register 7

Offset: 0xc1c, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR8

GICD interrupt configuration register 8

Offset: 0xc20, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR9

GICD interrupt configuration register 9

Offset: 0xc24, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR10

GICD interrupt configuration register 10

Offset: 0xc28, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR11

GICD interrupt configuration register 11

Offset: 0xc2c, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR12

GICD interrupt configuration register 12

Offset: 0xc30, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR13

GICD interrupt configuration register 13

Offset: 0xc34, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR14

GICD interrupt configuration register 14

Offset: 0xc38, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR15

GICD interrupt configuration register 15

Offset: 0xc3c, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR16

GICD interrupt configuration register 16

Offset: 0xc40, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

ICFGR17

GICD interrupt configuration register 17

Offset: 0xc44, size: 32, reset: 0x55555555, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_CONFIG15
rw 		INT_CONFIG14
rw 		INT_CONFIG13
rw 		INT_CONFIG12
rw 		INT_CONFIG11
rw 		INT_CONFIG10
rw 		INT_CONFIG9
rw 		INT_CONFIG8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT_CONFIG7
rw 		INT_CONFIG6
rw 		INT_CONFIG5
rw 		INT_CONFIG4
rw 		INT_CONFIG3
rw 		INT_CONFIG2
rw 		INT_CONFIG1
rw 		INT_CONFIG0
rw
Toggle fields

INT_CONFIG0

Bits 0-1: INT_CONFIG0.

INT_CONFIG1

Bits 2-3: INT_CONFIG1.

INT_CONFIG2

Bits 4-5: INT_CONFIG2.

INT_CONFIG3

Bits 6-7: INT_CONFIG3.

INT_CONFIG4

Bits 8-9: INT_CONFIG4.

INT_CONFIG5

Bits 10-11: INT_CONFIG5.

INT_CONFIG6

Bits 12-13: INT_CONFIG6.

INT_CONFIG7

Bits 14-15: INT_CONFIG7.

INT_CONFIG8

Bits 16-17: INT_CONFIG8.

INT_CONFIG9

Bits 18-19: INT_CONFIG9.

INT_CONFIG10

Bits 20-21: INT_CONFIG10.

INT_CONFIG11

Bits 22-23: INT_CONFIG11.

INT_CONFIG12

Bits 24-25: INT_CONFIG12.

INT_CONFIG13

Bits 26-27: INT_CONFIG13.

INT_CONFIG14

Bits 28-29: INT_CONFIG14.

INT_CONFIG15

Bits 30-31: INT_CONFIG15.

PPISR

GICD private peripheral interrupt status register

Offset: 0xd00, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPI3
r 		PPI2
r 		PPI1
r 		PPI0
r 		PPI4
r 		PPI5
r 		PPI6
r
Toggle fields

PPI6

Bit 9: PPI6.

PPI5

Bit 10: PPI5.

PPI4

Bit 11: PPI4.

PPI0

Bit 12: PPI0.

PPI1

Bit 13: PPI1.

PPI2

Bit 14: PPI2.

PPI3

Bit 15: PPI3.

SPISR1

For interrupts ID = SPI number+32, from SPI [x*32+31] to SPI [x*32]

Offset: 0xd08, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR1
r
Toggle fields

SPISR1

Bits 0-31: SPISR1.

SPISR2

For interrupts ID

Offset: 0xd0c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR2
r
Toggle fields

SPISR2

Bits 0-31: SPISR2.

SPISR3

For interrupts ID

Offset: 0xd10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR3
r
Toggle fields

SPISR3

Bits 0-31: SPISR3.

SPISR4

For interrupts ID

Offset: 0xd14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR4
r
Toggle fields

SPISR4

Bits 0-31: SPISR4.

SPISR5

For interrupts ID

Offset: 0xd18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR5
r
Toggle fields

SPISR5

Bits 0-31: SPISR5.

SPISR6

For interrupts ID

Offset: 0xd1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR6
r
Toggle fields

SPISR6

Bits 0-31: SPISR6.

SPISR7

For interrupts ID

Offset: 0xd20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPISR7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPISR7
r
Toggle fields

SPISR7

Bits 0-31: SPISR7.

SGIR

GICD software generated interrupt register

Offset: 0xf00, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TARGETLISTFILTER
w 		CPUTARGETLIST
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSATT
w 		SGIINTID
w
Toggle fields

SGIINTID

Bits 0-3: SGIINTID.

NSATT

Bit 15: NSATT.

CPUTARGETLIST

Bits 16-17: CPUTARGETLIST.

TARGETLISTFILTER

Bits 24-25: TARGETLISTFILTER.

CPENDSGIR0

For SGI x*4 to SGI x*4+3

Offset: 0xf10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_CLEAR_PENDING3
rw 		SGI_CLEAR_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_CLEAR_PENDING1
rw 		SGI_CLEAR_PENDING0
rw
Toggle fields

SGI_CLEAR_PENDING0

Bits 0-1: SGI_CLEAR_PENDING0.

SGI_CLEAR_PENDING1

Bits 8-9: SGI_CLEAR_PENDING1.

SGI_CLEAR_PENDING2

Bits 16-17: SGI_CLEAR_PENDING2.

SGI_CLEAR_PENDING3

Bits 24-25: SGI_CLEAR_PENDING3.

CPENDSGIR1

For SGI x*4 to SGI x*4+3

Offset: 0xf14, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_CLEAR_PENDING3
rw 		SGI_CLEAR_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_CLEAR_PENDING1
rw 		SGI_CLEAR_PENDING0
rw
Toggle fields

SGI_CLEAR_PENDING0

Bits 0-1: SGI_CLEAR_PENDING0.

SGI_CLEAR_PENDING1

Bits 8-9: SGI_CLEAR_PENDING1.

SGI_CLEAR_PENDING2

Bits 16-17: SGI_CLEAR_PENDING2.

SGI_CLEAR_PENDING3

Bits 24-25: SGI_CLEAR_PENDING3.

CPENDSGIR2

For SGI x*4 to SGI x*4+3

Offset: 0xf18, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_CLEAR_PENDING3
rw 		SGI_CLEAR_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_CLEAR_PENDING1
rw 		SGI_CLEAR_PENDING0
rw
Toggle fields

SGI_CLEAR_PENDING0

Bits 0-1: SGI_CLEAR_PENDING0.

SGI_CLEAR_PENDING1

Bits 8-9: SGI_CLEAR_PENDING1.

SGI_CLEAR_PENDING2

Bits 16-17: SGI_CLEAR_PENDING2.

SGI_CLEAR_PENDING3

Bits 24-25: SGI_CLEAR_PENDING3.

CPENDSGIR3

For SGI x*4 to SGI x*4+3

Offset: 0xf1c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_CLEAR_PENDING3
rw 		SGI_CLEAR_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_CLEAR_PENDING1
rw 		SGI_CLEAR_PENDING0
rw
Toggle fields

SGI_CLEAR_PENDING0

Bits 0-1: SGI_CLEAR_PENDING0.

SGI_CLEAR_PENDING1

Bits 8-9: SGI_CLEAR_PENDING1.

SGI_CLEAR_PENDING2

Bits 16-17: SGI_CLEAR_PENDING2.

SGI_CLEAR_PENDING3

Bits 24-25: SGI_CLEAR_PENDING3.

SPENDSGIR0

For SGI x*4 to SGI x*4+3

Offset: 0xf20, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_SET_PENDING3
rw 		SGI_SET_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_SET_PENDING1
rw 		SGI_SET_PENDING0
rw
Toggle fields

SGI_SET_PENDING0

Bits 0-1: SGI_SET_PENDING0.

SGI_SET_PENDING1

Bits 8-9: SGI_SET_PENDING1.

SGI_SET_PENDING2

Bits 16-17: SGI_SET_PENDING2.

SGI_SET_PENDING3

Bits 24-25: SGI_SET_PENDING3.

SPENDSGIR1

For SGI x*4 to SGI x*4+3

Offset: 0xf24, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_SET_PENDING3
rw 		SGI_SET_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_SET_PENDING1
rw 		SGI_SET_PENDING0
rw
Toggle fields

SGI_SET_PENDING0

Bits 0-1: SGI_SET_PENDING0.

SGI_SET_PENDING1

Bits 8-9: SGI_SET_PENDING1.

SGI_SET_PENDING2

Bits 16-17: SGI_SET_PENDING2.

SGI_SET_PENDING3

Bits 24-25: SGI_SET_PENDING3.

SPENDSGIR2

For SGI x*4 to SGI x*4+3

Offset: 0xf28, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_SET_PENDING3
rw 		SGI_SET_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_SET_PENDING1
rw 		SGI_SET_PENDING0
rw
Toggle fields

SGI_SET_PENDING0

Bits 0-1: SGI_SET_PENDING0.

SGI_SET_PENDING1

Bits 8-9: SGI_SET_PENDING1.

SGI_SET_PENDING2

Bits 16-17: SGI_SET_PENDING2.

SGI_SET_PENDING3

Bits 24-25: SGI_SET_PENDING3.

SPENDSGIR3

For SGI x*4 to SGI x*4+3

Offset: 0xf2c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SGI_SET_PENDING3
rw 		SGI_SET_PENDING2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SGI_SET_PENDING1
rw 		SGI_SET_PENDING0
rw
Toggle fields

SGI_SET_PENDING0

Bits 0-1: SGI_SET_PENDING0.

SGI_SET_PENDING1

Bits 8-9: SGI_SET_PENDING1.

SGI_SET_PENDING2

Bits 16-17: SGI_SET_PENDING2.

SGI_SET_PENDING3

Bits 24-25: SGI_SET_PENDING3.

PIDR4

GICD peripheral ID4 register

Offset: 0xfd0, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR4
r
Toggle fields

PIDR4

Bits 0-31: PIDR4.

PIDR5

GICD peripheral ID5 to ID7 register 5

Offset: 0xfd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR5
r
Toggle fields

PIDR5

Bits 0-31: PIDR5.

PIDR6

GICD peripheral ID5 to ID7 register 6

Offset: 0xfd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR6
r
Toggle fields

PIDR6

Bits 0-31: PIDR6.

PIDR7

GICD peripheral ID5 to ID7 register 7

Offset: 0xfdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR7
r
Toggle fields

PIDR7

Bits 0-31: PIDR7.

PIDR0

GICD peripheral ID0 register

Offset: 0xfe0, size: 32, reset: 0x00000090, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR0
r
Toggle fields

PIDR0

Bits 0-31: PIDR0.

PIDR1

GICD peripheral ID1 register

Offset: 0xfe4, size: 32, reset: 0x000000B4, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR1
r
Toggle fields

PIDR1

Bits 0-31: PIDR1.

PIDR2

GICD peripheral ID2 register

Offset: 0xfe8, size: 32, reset: 0x0000002B, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR2
r
Toggle fields

PIDR2

Bits 0-31: PIDR2.

PIDR3

GICD peripheral ID3 register

Offset: 0xfec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR3
r
Toggle fields

PIDR3

Bits 0-31: PIDR3.

CIDR0

GICD component ID0 register

Offset: 0xff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CIDR0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIDR0
r
Toggle fields

CIDR0

Bits 0-31: CIDR0.

CIDR1

GICD component ID1 register

Offset: 0xff4, size: 32, reset: 0x000000F0, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CIDR1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIDR1
r
Toggle fields

CIDR1

Bits 0-31: CIDR1.

CIDR2

GICD component ID2 register

Offset: 0xff8, size: 32, reset: 0x00000005, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CIDR2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIDR2
r
Toggle fields

CIDR2

Bits 0-31: CIDR2.

CIDR3

GICD component ID3 register

Offset: 0xffc, size: 32, reset: 0x000000B1, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CIDR3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIDR3
r
Toggle fields

CIDR3

Bits 0-31: CIDR3.

GICH

0xa0024000: GICH

13/56 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 HCR
0x4 VTR
0x8 VMCR
0x10 MISR
0x20 EISR0
0x30 ELSR0
0xf0 APR0
0x100 LR0
0x104 LR1
0x108 LR2
0x10c LR3
Toggle registers

HCR

GICH hypervisor control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EOICOUNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VGRP1DIE
rw 		VGRP1EIE
rw 		VGRP0DIE
rw 		VGRP0EIE
rw 		NPIE
rw 		LRENPIE
rw 		UIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

UIE

Bit 1: UIE.

LRENPIE

Bit 2: LRENPIE.

NPIE

Bit 3: NPIE.

VGRP0EIE

Bit 4: VGRP0EIE.

VGRP0DIE

Bit 5: VGRP0DIE.

VGRP1EIE

Bit 6: VGRP1EIE.

VGRP1DIE

Bit 7: VGRP1DIE.

EOICOUNT

Bits 27-31: EOICOUNT.

VTR

GICH VGIC type register

Offset: 0x4, size: 32, reset: 0x90000003, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIBITS
r 		PREBITS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LISTREGS
r
Toggle fields

LISTREGS

Bits 0-4: LISTREGS.

PREBITS

Bits 26-28: PREBITS.

PRIBITS

Bits 29-31: PRIBITS.

VMCR

GICH virtual machine control register

Offset: 0x8, size: 32, reset: 0x004D0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VMPRIMASK
rw 		VMBP
rw 		VMABP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VEM
rw 		VMCBPR
rw 		VMFIQEN
rw 		VMACKCTL
rw 		VMGRP1EN
rw 		VMGRP0EN
rw
Toggle fields

VMGRP0EN

Bit 0: VMGRP0EN.

VMGRP1EN

Bit 1: VMGRP1EN.

VMACKCTL

Bit 2: VMACKCTL.

VMFIQEN

Bit 3: VMFIQEN.

VMCBPR

Bit 4: VMCBPR.

VEM

Bit 9: VEM.

VMABP

Bits 18-20: VMABP.

VMBP

Bits 21-23: VMBP.

VMPRIMASK

Bits 27-31: VMPRIMASK.

MISR

GICH maintenance interrupt status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VGRP1D
r 		VGRP1E
r 		VGRP0D
r 		VGRP0E
r 		NP
r 		LRENP
r 		U
r 		EOI
r
Toggle fields

EOI

Bit 0: EOI.

U

Bit 1: U.

LRENP

Bit 2: LRENP.

NP

Bit 3: NP.

VGRP0E

Bit 4: VGRP0E.

VGRP0D

Bit 5: VGRP0D.

VGRP1E

Bit 6: VGRP1E.

VGRP1D

Bit 7: VGRP1D.

EISR0

GICH end of interrupt status register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EISR0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EISR0
r
Toggle fields

EISR0

Bits 0-31: EISR0.

ELSR0

GICH empty list status register

Offset: 0x30, size: 32, reset: 0x0000000F, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ELSR0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ELSR0
r
Toggle fields

ELSR0

Bits 0-31: ELSR0.

APR0

GICH active priority register

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APR0
rw
Toggle fields

APR0

Bits 0-31: APR0.

LR0

GICH list register 0

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW
rw 		GRP1
rw 		STATE
rw 		PRIORITY
rw 		PHYSICALID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSICALID
rw 		VIRTUALID
rw
Toggle fields

VIRTUALID

Bits 0-9: VIRTUALID.

PHYSICALID

Bits 10-19: PHYSICALID.

PRIORITY

Bits 23-27: PRIORITY.

STATE

Bits 28-29: STATE.

GRP1

Bit 30: GRP1.

HW

Bit 31: HW.

LR1

GICH list register 1

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW
rw 		GRP1
rw 		STATE
rw 		PRIORITY
rw 		PHYSICALID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSICALID
rw 		VIRTUALID
rw
Toggle fields

VIRTUALID

Bits 0-9: VIRTUALID.

PHYSICALID

Bits 10-19: PHYSICALID.

PRIORITY

Bits 23-27: PRIORITY.

STATE

Bits 28-29: STATE.

GRP1

Bit 30: GRP1.

HW

Bit 31: HW.

LR2

GICH list register 2

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW
rw 		GRP1
rw 		STATE
rw 		PRIORITY
rw 		PHYSICALID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSICALID
rw 		VIRTUALID
rw
Toggle fields

VIRTUALID

Bits 0-9: VIRTUALID.

PHYSICALID

Bits 10-19: PHYSICALID.

PRIORITY

Bits 23-27: PRIORITY.

STATE

Bits 28-29: STATE.

GRP1

Bit 30: GRP1.

HW

Bit 31: HW.

LR3

GICH list register 3

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW
rw 		GRP1
rw 		STATE
rw 		PRIORITY
rw 		PHYSICALID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYSICALID
rw 		VIRTUALID
rw
Toggle fields

VIRTUALID

Bits 0-9: VIRTUALID.

PHYSICALID

Bits 10-19: PHYSICALID.

PRIORITY

Bits 23-27: PRIORITY.

STATE

Bits 28-29: STATE.

GRP1

Bit 30: GRP1.

HW

Bit 31: HW.

GICV

0xa0026000: GICV

10/26 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTLR
0x4 PMR
0x8 BPR
0xc IAR
0x10 EOIR
0x14 RPR
0x18 HPPIR
0x1c ABPR
0x20 AIAR
0x24 AEOIR
0x28 AHPPIR
0xd0 APR0
0xfc IIDR
0x1000 DIR
Toggle registers

CTLR

GICV virtual machine control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOIMODE
rw 		CBPR
rw 		FIQEN
rw 		ACKCTL
rw 		ENABLEGRP1
rw 		ENABLEGRP0
rw
Toggle fields

ENABLEGRP0

Bit 0: ENABLEGRP0.

ENABLEGRP1

Bit 1: ENABLEGRP1.

ACKCTL

Bit 2: ACKCTL.

FIQEN

Bit 3: FIQEN.

CBPR

Bit 4: CBPR.

EOIMODE

Bit 9: EOIMODE.

PMR

GICV VM priority mask register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY
rw
Toggle fields

PRIORITY

Bits 3-7: PRIORITY.

BPR

GICV VM binary point register

Offset: 0x8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BINARY_POINT
rw
Toggle fields

BINARY_POINT

Bits 0-2: BINARY_POINT.

IAR

GICV VM interrupt acknowledge register

Offset: 0xc, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		INTERRUPT_ID
r
Toggle fields

INTERRUPT_ID

Bits 0-9: INTERRUPT_ID.

CPUID

Bit 10: CPUID.

EOIR

GICV VM end of interrupt register

Offset: 0x10, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
w 		EOIINTID
w
Toggle fields

EOIINTID

Bits 0-9: EOIINTID.

CPUID

Bit 10: CPUID.

RPR

GICV VM running priority register

Offset: 0x14, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRIORITY
r
Toggle fields

PRIORITY

Bits 3-7: PRIORITY.

HPPIR

GICV VM highest priority pending interrupt register

Offset: 0x18, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		PENDINTID
r
Toggle fields

PENDINTID

Bits 0-9: PENDINTID.

CPUID

Bit 10: CPUID.

ABPR

GICV VM aliased binary point register

Offset: 0x1c, size: 32, reset: 0x00000003, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BINARY_POINT
rw
Toggle fields

BINARY_POINT

Bits 0-2: BINARY_POINT.

AIAR

GICV VM aliased interrupt register

Offset: 0x20, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		INTERRUPT_ID
r
Toggle fields

INTERRUPT_ID

Bits 0-9: INTERRUPT_ID.

CPUID

Bit 10: CPUID.

AEOIR

GICV VM aliased end of interrupt register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
w 		EOIINTID
w
Toggle fields

EOIINTID

Bits 0-9: EOIINTID.

CPUID

Bit 10: CPUID.

AHPPIR

GICV VM aliased highest priority pending interrupt register

Offset: 0x28, size: 32, reset: 0x000003FF, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
r 		PENDINTID
r
Toggle fields

PENDINTID

Bits 0-9: PENDINTID.

CPUID

Bit 10: CPUID.

APR0

The GICV_APR0 is an alias of GICH_APR.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APR0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APR0
rw
Toggle fields

APR0

Bits 0-31: APR0.

IIDR

The GICV_IIDR is an alias of GICC_IIDR.

Offset: 0xfc, size: 32, reset: 0x0102143B, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IIDR
r
Toggle fields

IIDR

Bits 0-31: IIDR.

DIR

GICV VM deactivate interrupt register

Offset: 0x1000, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPUID
w 		INTERRUPT_ID
w
Toggle fields

INTERRUPT_ID

Bits 0-9: INTERRUPT_ID.

CPUID

Bit 10: CPUID.

GPIOA

0x50002000: GPIOA

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOB

0x50003000: GPIOB

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOC

0x50004000: GPIOC

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOD

0x50005000: GPIOD

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOE

0x50006000: GPIOE

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOF

0x50007000: GPIOF

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOG

0x50008000: GPIOG

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOH

0x50009000: GPIOH

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOI

0x5000a000: GPIOI

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOJ

0x5000b000: GPIOJ

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOK

0x5000c000: GPIOK

51/212 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

GPIOZ

0x54004000: GPIOZ

51/220 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 MODER
0x4 OTYPER
0x8 OSPEEDR
0xc PUPDR
0x10 IDR
0x14 ODR
0x18 BSRR
0x1c LCKR
0x20 AFRL
0x24 AFRH
0x28 BRR
0x30 SECCFGR
0x3c8 HWCFGR10
0x3cc HWCFGR9
0x3d0 HWCFGR8
0x3d4 HWCFGR7
0x3d8 HWCFGR6
0x3dc HWCFGR5
0x3e0 HWCFGR4
0x3e4 HWCFGR3
0x3e8 HWCFGR2
0x3ec HWCFGR1
0x3f0 HWCFGR0
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

MODER

GPIO port mode register

Offset: 0x0, size: 32, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER15
rw 		MODER14
rw 		MODER13
rw 		MODER12
rw 		MODER11
rw 		MODER10
rw 		MODER9
rw 		MODER8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER7
rw 		MODER6
rw 		MODER5
rw 		MODER4
rw 		MODER3
rw 		MODER2
rw 		MODER1
rw 		MODER0
rw
Toggle fields

MODER0

Bits 0-1: MODER0.

MODER1

Bits 2-3: MODER1.

MODER2

Bits 4-5: MODER2.

MODER3

Bits 6-7: MODER3.

MODER4

Bits 8-9: MODER4.

MODER5

Bits 10-11: MODER5.

MODER6

Bits 12-13: MODER6.

MODER7

Bits 14-15: MODER7.

MODER8

Bits 16-17: MODER8.

MODER9

Bits 18-19: MODER9.

MODER10

Bits 20-21: MODER10.

MODER11

Bits 22-23: MODER11.

MODER12

Bits 24-25: MODER12.

MODER13

Bits 26-27: MODER13.

MODER14

Bits 28-29: MODER14.

MODER15

Bits 30-31: MODER15.

OTYPER

GPIO port output type register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15
rw 		OT14
rw 		OT13
rw 		OT12
rw 		OT11
rw 		OT10
rw 		OT9
rw 		OT8
rw 		OT7
rw 		OT6
rw 		OT5
rw 		OT4
rw 		OT3
rw 		OT2
rw 		OT1
rw 		OT0
rw
Toggle fields

OT0

Bit 0: OT0.

OT1

Bit 1: OT1.

OT2

Bit 2: OT2.

OT3

Bit 3: OT3.

OT4

Bit 4: OT4.

OT5

Bit 5: OT5.

OT6

Bit 6: OT6.

OT7

Bit 7: OT7.

OT8

Bit 8: OT8.

OT9

Bit 9: OT9.

OT10

Bit 10: OT10.

OT11

Bit 11: OT11.

OT12

Bit 12: OT12.

OT13

Bit 13: OT13.

OT14

Bit 14: OT14.

OT15

Bit 15: OT15.

OSPEEDR

GPIO port output speed register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEEDR15
rw 		OSPEEDR14
rw 		OSPEEDR13
rw 		OSPEEDR12
rw 		OSPEEDR11
rw 		OSPEEDR10
rw 		OSPEEDR9
rw 		OSPEEDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEEDR7
rw 		OSPEEDR6
rw 		OSPEEDR5
rw 		OSPEEDR4
rw 		OSPEEDR3
rw 		OSPEEDR2
rw 		OSPEEDR1
rw 		OSPEEDR0
rw
Toggle fields

OSPEEDR0

Bits 0-1: OSPEEDR0.

OSPEEDR1

Bits 2-3: OSPEEDR1.

OSPEEDR2

Bits 4-5: OSPEEDR2.

OSPEEDR3

Bits 6-7: OSPEEDR3.

OSPEEDR4

Bits 8-9: OSPEEDR4.

OSPEEDR5

Bits 10-11: OSPEEDR5.

OSPEEDR6

Bits 12-13: OSPEEDR6.

OSPEEDR7

Bits 14-15: OSPEEDR7.

OSPEEDR8

Bits 16-17: OSPEEDR8.

OSPEEDR9

Bits 18-19: OSPEEDR9.

OSPEEDR10

Bits 20-21: OSPEEDR10.

OSPEEDR11

Bits 22-23: OSPEEDR11.

OSPEEDR12

Bits 24-25: OSPEEDR12.

OSPEEDR13

Bits 26-27: OSPEEDR13.

OSPEEDR14

Bits 28-29: OSPEEDR14.

OSPEEDR15

Bits 30-31: OSPEEDR15.

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR15
rw 		PUPDR14
rw 		PUPDR13
rw 		PUPDR12
rw 		PUPDR11
rw 		PUPDR10
rw 		PUPDR9
rw 		PUPDR8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR7
rw 		PUPDR6
rw 		PUPDR5
rw 		PUPDR4
rw 		PUPDR3
rw 		PUPDR2
rw 		PUPDR1
rw 		PUPDR0
rw
Toggle fields

PUPDR0

Bits 0-1: PUPDR0.

PUPDR1

Bits 2-3: PUPDR1.

PUPDR2

Bits 4-5: PUPDR2.

PUPDR3

Bits 6-7: PUPDR3.

PUPDR4

Bits 8-9: PUPDR4.

PUPDR5

Bits 10-11: PUPDR5.

PUPDR6

Bits 12-13: PUPDR6.

PUPDR7

Bits 14-15: PUPDR7.

PUPDR8

Bits 16-17: PUPDR8.

PUPDR9

Bits 18-19: PUPDR9.

PUPDR10

Bits 20-21: PUPDR10.

PUPDR11

Bits 22-23: PUPDR11.

PUPDR12

Bits 24-25: PUPDR12.

PUPDR13

Bits 26-27: PUPDR13.

PUPDR14

Bits 28-29: PUPDR14.

PUPDR15

Bits 30-31: PUPDR15.

IDR

GPIO port input data register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

16/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDR15
r 		IDR14
r 		IDR13
r 		IDR12
r 		IDR11
r 		IDR10
r 		IDR9
r 		IDR8
r 		IDR7
r 		IDR6
r 		IDR5
r 		IDR4
r 		IDR3
r 		IDR2
r 		IDR1
r 		IDR0
r
Toggle fields

IDR0

Bit 0: IDR0.

IDR1

Bit 1: IDR1.

IDR2

Bit 2: IDR2.

IDR3

Bit 3: IDR3.

IDR4

Bit 4: IDR4.

IDR5

Bit 5: IDR5.

IDR6

Bit 6: IDR6.

IDR7

Bit 7: IDR7.

IDR8

Bit 8: IDR8.

IDR9

Bit 9: IDR9.

IDR10

Bit 10: IDR10.

IDR11

Bit 11: IDR11.

IDR12

Bit 12: IDR12.

IDR13

Bit 13: IDR13.

IDR14

Bit 14: IDR14.

IDR15

Bit 15: IDR15.

ODR

GPIO port output data register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR15
rw 		ODR14
rw 		ODR13
rw 		ODR12
rw 		ODR11
rw 		ODR10
rw 		ODR9
rw 		ODR8
rw 		ODR7
rw 		ODR6
rw 		ODR5
rw 		ODR4
rw 		ODR3
rw 		ODR2
rw 		ODR1
rw 		ODR0
rw
Toggle fields

ODR0

Bit 0: ODR0.

ODR1

Bit 1: ODR1.

ODR2

Bit 2: ODR2.

ODR3

Bit 3: ODR3.

ODR4

Bit 4: ODR4.

ODR5

Bit 5: ODR5.

ODR6

Bit 6: ODR6.

ODR7

Bit 7: ODR7.

ODR8

Bit 8: ODR8.

ODR9

Bit 9: ODR9.

ODR10

Bit 10: ODR10.

ODR11

Bit 11: ODR11.

ODR12

Bit 12: ODR12.

ODR13

Bit 13: ODR13.

ODR14

Bit 14: ODR14.

ODR15

Bit 15: ODR15.

BSRR

GPIO port bit set/reset register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15
w 		BS14
w 		BS13
w 		BS12
w 		BS11
w 		BS10
w 		BS9
w 		BS8
w 		BS7
w 		BS6
w 		BS5
w 		BS4
w 		BS3
w 		BS2
w 		BS1
w 		BS0
w
Toggle fields

BS0

Bit 0: BS0.

BS1

Bit 1: BS1.

BS2

Bit 2: BS2.

BS3

Bit 3: BS3.

BS4

Bit 4: BS4.

BS5

Bit 5: BS5.

BS6

Bit 6: BS6.

BS7

Bit 7: BS7.

BS8

Bit 8: BS8.

BS9

Bit 9: BS9.

BS10

Bit 10: BS10.

BS11

Bit 11: BS11.

BS12

Bit 12: BS12.

BS13

Bit 13: BS13.

BS14

Bit 14: BS14.

BS15

Bit 15: BS15.

BR0

Bit 16: BR0.

BR1

Bit 17: BR1.

BR2

Bit 18: BR2.

BR3

Bit 19: BR3.

BR4

Bit 20: BR4.

BR5

Bit 21: BR5.

BR6

Bit 22: BR6.

BR7

Bit 23: BR7.

BR8

Bit 24: BR8.

BR9

Bit 25: BR9.

BR10

Bit 26: BR10.

BR11

Bit 27: BR11.

BR12

Bit 28: BR12.

BR13

Bit 29: BR13.

BR14

Bit 30: BR14.

BR15

Bit 31: BR15.

LCKR

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers).

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15
rw 		LCK14
rw 		LCK13
rw 		LCK12
rw 		LCK11
rw 		LCK10
rw 		LCK9
rw 		LCK8
rw 		LCK7
rw 		LCK6
rw 		LCK5
rw 		LCK4
rw 		LCK3
rw 		LCK2
rw 		LCK1
rw 		LCK0
rw
Toggle fields

LCK0

Bit 0: LCK0.

LCK1

Bit 1: LCK1.

LCK2

Bit 2: LCK2.

LCK3

Bit 3: LCK3.

LCK4

Bit 4: LCK4.

LCK5

Bit 5: LCK5.

LCK6

Bit 6: LCK6.

LCK7

Bit 7: LCK7.

LCK8

Bit 8: LCK8.

LCK9

Bit 9: LCK9.

LCK10

Bit 10: LCK10.

LCK11

Bit 11: LCK11.

LCK12

Bit 12: LCK12.

LCK13

Bit 13: LCK13.

LCK14

Bit 14: LCK14.

LCK15

Bit 15: LCK15.

LCKK

Bit 16: LCKK.

AFRL

GPIO alternate function low register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR7
rw 		AFR6
rw 		AFR5
rw 		AFR4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR3
rw 		AFR2
rw 		AFR1
rw 		AFR0
rw
Toggle fields

AFR0

Bits 0-3: AFR0.

AFR1

Bits 4-7: AFR1.

AFR2

Bits 8-11: AFR2.

AFR3

Bits 12-15: AFR3.

AFR4

Bits 16-19: AFR4.

AFR5

Bits 20-23: AFR5.

AFR6

Bits 24-27: AFR6.

AFR7

Bits 28-31: AFR7.

AFRH

GPIO alternate function high register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFR15
rw 		AFR14
rw 		AFR13
rw 		AFR12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFR11
rw 		AFR10
rw 		AFR9
rw 		AFR8
rw
Toggle fields

AFR8

Bits 0-3: AFR8.

AFR9

Bits 4-7: AFR9.

AFR10

Bits 8-11: AFR10.

AFR11

Bits 12-15: AFR11.

AFR12

Bits 16-19: AFR12.

AFR13

Bits 20-23: AFR13.

AFR14

Bits 24-27: AFR14.

AFR15

Bits 28-31: AFR15.

BRR

GPIO port bit reset register

Offset: 0x28, size: 32, reset: 0x00000000, access: write-only

0/16 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15
w 		BR14
w 		BR13
w 		BR12
w 		BR11
w 		BR10
w 		BR9
w 		BR8
w 		BR7
w 		BR6
w 		BR5
w 		BR4
w 		BR3
w 		BR2
w 		BR1
w 		BR0
w
Toggle fields

BR0

Bit 0: BR0.

BR1

Bit 1: BR1.

BR2

Bit 2: BR2.

BR3

Bit 3: BR3.

BR4

Bit 4: BR4.

BR5

Bit 5: BR5.

BR6

Bit 6: BR6.

BR7

Bit 7: BR7.

BR8

Bit 8: BR8.

BR9

Bit 9: BR9.

BR10

Bit 10: BR10.

BR11

Bit 11: BR11.

BR12

Bit 12: BR12.

BR13

Bit 13: BR13.

BR14

Bit 14: BR14.

BR15

Bit 15: BR15.

SECCFGR

This register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A non-secure write access to this register is discarded.

Offset: 0x30, size: 32, reset: 0x000000FF, access: write-only

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC7
w 		SEC6
w 		SEC5
w 		SEC4
w 		SEC3
w 		SEC2
w 		SEC1
w 		SEC0
w
Toggle fields

SEC0

Bit 0: SEC0.

SEC1

Bit 1: SEC1.

SEC2

Bit 2: SEC2.

SEC3

Bit 3: SEC3.

SEC4

Bit 4: SEC4.

SEC5

Bit 5: SEC5.

SEC6

Bit 6: SEC6.

SEC7

Bit 7: SEC7.

HWCFGR10

For GPIOA, B, C, D, E, F, G, H, I, J and GPIOK: For GPIOZ:

Offset: 0x3c8, size: 32, reset: 0x00011240, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OR_CFG
r 		SEC_CFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CFG
r 		SPEED_CFG
r 		AF_SIZE
r 		AHB_IOP
r
Toggle fields

AHB_IOP

Bits 0-3: AHB_IOP.

AF_SIZE

Bits 4-7: AF_SIZE.

SPEED_CFG

Bits 8-11: SPEED_CFG.

LOCK_CFG

Bits 12-15: LOCK_CFG.

SEC_CFG

Bits 16-19: SEC_CFG.

OR_CFG

Bits 20-23: OR_CFG.

HWCFGR9

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3cc, size: 32, reset: 0x000000FF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_IO
r
Toggle fields

EN_IO

Bits 0-15: EN_IO.

HWCFGR8

For GPIOA, B, C, D, E, F, G, H, I, and GPIOJ: For GPIOK and GPIOZ:

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO15
r 		AF_PRIO14
r 		AF_PRIO13
r 		AF_PRIO12
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO11
r 		AF_PRIO10
r 		AF_PRIO9
r 		AF_PRIO8
r
Toggle fields

AF_PRIO8

Bits 0-3: AF_PRIO8.

AF_PRIO9

Bits 4-7: AF_PRIO9.

AF_PRIO10

Bits 8-11: AF_PRIO10.

AF_PRIO11

Bits 12-15: AF_PRIO11.

AF_PRIO12

Bits 16-19: AF_PRIO12.

AF_PRIO13

Bits 20-23: AF_PRIO13.

AF_PRIO14

Bits 24-27: AF_PRIO14.

AF_PRIO15

Bits 28-31: AF_PRIO15.

HWCFGR7

GPIO hardware configuration register 7

Offset: 0x3d4, size: 32, reset: 0xFFFFFFFF, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AF_PRIO7
r 		AF_PRIO6
r 		AF_PRIO5
r 		AF_PRIO4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AF_PRIO3
r 		AF_PRIO2
r 		AF_PRIO1
r 		AF_PRIO0
r
Toggle fields

AF_PRIO0

Bits 0-3: AF_PRIO0.

AF_PRIO1

Bits 4-7: AF_PRIO1.

AF_PRIO2

Bits 8-11: AF_PRIO2.

AF_PRIO3

Bits 12-15: AF_PRIO3.

AF_PRIO4

Bits 16-19: AF_PRIO4.

AF_PRIO5

Bits 20-23: AF_PRIO5.

AF_PRIO6

Bits 24-27: AF_PRIO6.

AF_PRIO7

Bits 28-31: AF_PRIO7.

HWCFGR6

GPIO hardware configuration register 6

Offset: 0x3d8, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MODER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MODER_RES
r
Toggle fields

MODER_RES

Bits 0-31: MODER_RES.

HWCFGR5

GPIO hardware configuration register 5

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPDR_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPDR_RES
r
Toggle fields

PUPDR_RES

Bits 0-31: PUPDR_RES.

HWCFGR4

GPIO hardware configuration register 4

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED_RES
r
Toggle fields

OSPEED_RES

Bits 0-31: OSPEED_RES.

HWCFGR3

GPIO hardware configuration register 3

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTYPER_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ODR_RES
r
Toggle fields

ODR_RES

Bits 0-15: ODR_RES.

OTYPER_RES

Bits 16-31: OTYPER_RES.

HWCFGR2

GPIO hardware configuration register 2

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRL_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRL_RES
r
Toggle fields

AFRL_RES

Bits 0-31: AFRL_RES.

HWCFGR1

GPIO hardware configuration register 1

Offset: 0x3ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFRH_RES
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFRH_RES
r
Toggle fields

AFRH_RES

Bits 0-31: AFRH_RES.

HWCFGR0

GPIO hardware configuration register 0

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OR_RES
r
Toggle fields

OR_RES

Bits 0-15: OR_RES.

VERR

GPIO version register

Offset: 0x3f4, size: 32, reset: 0x00000040, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

GPIO identification register

Offset: 0x3f8, size: 32, reset: 0x000F0002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPIDR
r
Toggle fields

IPIDR

Bits 0-31: IPIDR.

SIDR

GPIO size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIDR
r
Toggle fields

SIDR

Bits 0-31: SIDR.

HASH1

0x54002000: HASH register block

16/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HR0
0x10 HR1
0x14 HR2
0x18 HR3
0x1c HR4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x324 HR5
0x328 HR6
0x32c HR7
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc MID
Toggle registers

CR

HASH control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw 		LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAA
w 		MDMAT
rw 		DINNE
r 		NBW
r 		ALGO0
rw 		MODE
rw 		DATATYPE
rw 		DMAE
rw 		INIT
w
Toggle fields

INIT

Bit 2: INIT.

DMAE

Bit 3: DMAE.

DATATYPE

Bits 4-5: DATATYPE.

MODE

Bit 6: MODE.

ALGO0

Bit 7: ALGO0.

NBW

Bits 8-11: NBW.

DINNE

Bit 12: DINNE.

MDMAT

Bit 13: MDMAT.

DMAA

Bit 14: DMAA.

LKEY

Bit 16: LKEY.

ALGO1

Bit 18: ALGO1.

DIN

HASH_DIN is the data input register.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: DATAIN.

STR

The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
w 		NBLW
rw
Toggle fields

NBLW

Bits 0-4: NBLW.

DCAL

Bit 8: DCAL.

HR0

HASH digest register 0

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

HASH digest register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

HASH digest register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

HASH digest register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

HASH digest register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

HASH interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw 		DINIE
rw
Toggle fields

DINIE

Bit 0: DINIE.

DCIE

Bit 1: DCIE.

SR

HASH status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		DMAS
r 		DCIS
rw 		DINIS
rw
Toggle fields

DINIS

Bit 0: DINIS.

DCIS

Bit 1: DCIS.

DMAS

Bit 2: DMAS.

BUSY

Bit 3: BUSY.

CSR0

These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers.

Offset: 0xf8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS0
rw
Toggle fields

CS0

Bits 0-31: CS0.

CSR1

HASH context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS1
rw
Toggle fields

CS1

Bits 0-31: CS1.

CSR2

HASH context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS2
rw
Toggle fields

CS2

Bits 0-31: CS2.

CSR3

HASH context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS3
rw
Toggle fields

CS3

Bits 0-31: CS3.

CSR4

HASH context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS4
rw
Toggle fields

CS4

Bits 0-31: CS4.

CSR5

HASH context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS5
rw
Toggle fields

CS5

Bits 0-31: CS5.

CSR6

HASH context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS6
rw
Toggle fields

CS6

Bits 0-31: CS6.

CSR7

HASH context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS7
rw
Toggle fields

CS7

Bits 0-31: CS7.

CSR8

HASH context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS8
rw
Toggle fields

CS8

Bits 0-31: CS8.

CSR9

HASH context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS9
rw
Toggle fields

CS9

Bits 0-31: CS9.

CSR10

HASH context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS10
rw
Toggle fields

CS10

Bits 0-31: CS10.

CSR11

HASH context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS11
rw
Toggle fields

CS11

Bits 0-31: CS11.

CSR12

HASH context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS12
rw
Toggle fields

CS12

Bits 0-31: CS12.

CSR13

HASH context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS13
rw
Toggle fields

CS13

Bits 0-31: CS13.

CSR14

HASH context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS14
rw
Toggle fields

CS14

Bits 0-31: CS14.

CSR15

HASH context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS15
rw
Toggle fields

CS15

Bits 0-31: CS15.

CSR16

HASH context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS16
rw
Toggle fields

CS16

Bits 0-31: CS16.

CSR17

HASH context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS17
rw
Toggle fields

CS17

Bits 0-31: CS17.

CSR18

HASH context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS18
rw
Toggle fields

CS18

Bits 0-31: CS18.

CSR19

HASH context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS19
rw
Toggle fields

CS19

Bits 0-31: CS19.

CSR20

HASH context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS20
rw
Toggle fields

CS20

Bits 0-31: CS20.

CSR21

HASH context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS21
rw
Toggle fields

CS21

Bits 0-31: CS21.

CSR22

HASH context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS22
rw
Toggle fields

CS22

Bits 0-31: CS22.

CSR23

HASH context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS23
rw
Toggle fields

CS23

Bits 0-31: CS23.

CSR24

HASH context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS24
rw
Toggle fields

CS24

Bits 0-31: CS24.

CSR25

HASH context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS25
rw
Toggle fields

CS25

Bits 0-31: CS25.

CSR26

HASH context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS26
rw
Toggle fields

CS26

Bits 0-31: CS26.

CSR27

HASH context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS27
rw
Toggle fields

CS27

Bits 0-31: CS27.

CSR28

HASH context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS28
rw
Toggle fields

CS28

Bits 0-31: CS28.

CSR29

HASH context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS29
rw
Toggle fields

CS29

Bits 0-31: CS29.

CSR30

HASH context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS30
rw
Toggle fields

CS30

Bits 0-31: CS30.

CSR31

HASH context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS31
rw
Toggle fields

CS31

Bits 0-31: CS31.

CSR32

HASH context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS32
rw
Toggle fields

CS32

Bits 0-31: CS32.

CSR33

HASH context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS33
rw
Toggle fields

CS33

Bits 0-31: CS33.

CSR34

HASH context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS34
rw
Toggle fields

CS34

Bits 0-31: CS34.

CSR35

HASH context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS35
rw
Toggle fields

CS35

Bits 0-31: CS35.

CSR36

HASH context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS36
rw
Toggle fields

CS36

Bits 0-31: CS36.

CSR37

HASH context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS37
rw
Toggle fields

CS37

Bits 0-31: CS37.

CSR38

HASH context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS38
rw
Toggle fields

CS38

Bits 0-31: CS38.

CSR39

HASH context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS39
rw
Toggle fields

CS39

Bits 0-31: CS39.

CSR40

HASH context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS40
rw
Toggle fields

CS40

Bits 0-31: CS40.

CSR41

HASH context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS41
rw
Toggle fields

CS41

Bits 0-31: CS41.

CSR42

HASH context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS42
rw
Toggle fields

CS42

Bits 0-31: CS42.

CSR43

HASH context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS43
rw
Toggle fields

CS43

Bits 0-31: CS43.

CSR44

HASH context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS44
rw
Toggle fields

CS44

Bits 0-31: CS44.

CSR45

HASH context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS45
rw
Toggle fields

CS45

Bits 0-31: CS45.

CSR46

HASH context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS46
rw
Toggle fields

CS46

Bits 0-31: CS46.

CSR47

HASH context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS47
rw
Toggle fields

CS47

Bits 0-31: CS47.

CSR48

HASH context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS48
rw
Toggle fields

CS48

Bits 0-31: CS48.

CSR49

HASH context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS49
rw
Toggle fields

CS49

Bits 0-31: CS49.

CSR50

HASH context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS50
rw
Toggle fields

CS50

Bits 0-31: CS50.

CSR51

HASH context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS51
rw
Toggle fields

CS51

Bits 0-31: CS51.

CSR52

HASH context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS52
rw
Toggle fields

CS52

Bits 0-31: CS52.

CSR53

HASH context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS53
rw
Toggle fields

CS53

Bits 0-31: CS53.

HR5

HASH digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HR6

HASH digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HR7

HASH digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

HWCFGR

HASH Hardware Configuration Register

Offset: 0x3f0, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

VERR

HASH Version Register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VER
r
Toggle fields

VER

Bits 0-7: VER.

IPIDR

HASH Identification

Offset: 0x3f8, size: 32, reset: 0x00170031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

MID

HASH Hardware Magic ID

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MID
r
Toggle fields

MID

Bits 0-31: MID.

HASH2

0x4c002000: HASH register block

16/86 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DIN
0x8 STR
0xc HR0
0x10 HR1
0x14 HR2
0x18 HR3
0x1c HR4
0x20 IMR
0x24 SR
0xf8 CSR0
0xfc CSR1
0x100 CSR2
0x104 CSR3
0x108 CSR4
0x10c CSR5
0x110 CSR6
0x114 CSR7
0x118 CSR8
0x11c CSR9
0x120 CSR10
0x124 CSR11
0x128 CSR12
0x12c CSR13
0x130 CSR14
0x134 CSR15
0x138 CSR16
0x13c CSR17
0x140 CSR18
0x144 CSR19
0x148 CSR20
0x14c CSR21
0x150 CSR22
0x154 CSR23
0x158 CSR24
0x15c CSR25
0x160 CSR26
0x164 CSR27
0x168 CSR28
0x16c CSR29
0x170 CSR30
0x174 CSR31
0x178 CSR32
0x17c CSR33
0x180 CSR34
0x184 CSR35
0x188 CSR36
0x18c CSR37
0x190 CSR38
0x194 CSR39
0x198 CSR40
0x19c CSR41
0x1a0 CSR42
0x1a4 CSR43
0x1a8 CSR44
0x1ac CSR45
0x1b0 CSR46
0x1b4 CSR47
0x1b8 CSR48
0x1bc CSR49
0x1c0 CSR50
0x1c4 CSR51
0x1c8 CSR52
0x1cc CSR53
0x324 HR5
0x328 HR6
0x32c HR7
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc MID
Toggle registers

CR

HASH control register

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

2/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALGO1
rw 		LKEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAA
w 		MDMAT
rw 		DINNE
r 		NBW
r 		ALGO0
rw 		MODE
rw 		DATATYPE
rw 		DMAE
rw 		INIT
w
Toggle fields

INIT

Bit 2: INIT.

DMAE

Bit 3: DMAE.

DATATYPE

Bits 4-5: DATATYPE.

MODE

Bit 6: MODE.

ALGO0

Bit 7: ALGO0.

NBW

Bits 8-11: NBW.

DINNE

Bit 12: DINNE.

MDMAT

Bit 13: MDMAT.

DMAA

Bit 14: DMAA.

LKEY

Bit 16: LKEY.

ALGO1

Bit 18: ALGO1.

DIN

HASH_DIN is the data input register.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN
rw
Toggle fields

DATAIN

Bits 0-31: DATAIN.

STR

The HASH_STR register has two functions: It is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written to the HASH_DIN register) It is used to start the processing of the last block in the message by writing the DCAL bit to 1

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCAL
w 		NBLW
rw
Toggle fields

NBLW

Bits 0-4: NBLW.

DCAL

Bit 8: DCAL.

HR0

HASH digest register 0

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H0
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H0
r
Toggle fields

H0

Bits 0-31: H0.

HR1

HASH digest register 1

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H1
r
Toggle fields

H1

Bits 0-31: H1.

HR2

HASH digest register 2

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H2
r
Toggle fields

H2

Bits 0-31: H2.

HR3

HASH digest register 3

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H3
r
Toggle fields

H3

Bits 0-31: H3.

HR4

HASH digest register 4

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H4
r
Toggle fields

H4

Bits 0-31: H4.

IMR

HASH interrupt enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCIE
rw 		DINIE
rw
Toggle fields

DINIE

Bit 0: DINIE.

DCIE

Bit 1: DCIE.

SR

HASH status register

Offset: 0x24, size: 32, reset: 0x00000001, access: Unspecified

2/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		DMAS
r 		DCIS
rw 		DINIS
rw
Toggle fields

DINIS

Bit 0: DINIS.

DCIS

Bit 1: DCIS.

DMAS

Bit 2: DMAS.

BUSY

Bit 3: BUSY.

CSR0

These registers contain the complete internal register states of the hash processor. They are useful when a context swap has to be done because a high-priority task needs to use the hash processor while it is already used by another task. When such an event occurs, the HASH_CSRx registers have to be read and the read values have to be saved in the system memory space. Then the hash processor can be used by the preemptive task, and when the hash computation is complete, the saved context can be read from memory and written back into the HASH_CSRx registers.

Offset: 0xf8, size: 32, reset: 0x00000002, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS0
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS0
rw
Toggle fields

CS0

Bits 0-31: CS0.

CSR1

HASH context swap registers

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS1
rw
Toggle fields

CS1

Bits 0-31: CS1.

CSR2

HASH context swap registers

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS2
rw
Toggle fields

CS2

Bits 0-31: CS2.

CSR3

HASH context swap registers

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS3
rw
Toggle fields

CS3

Bits 0-31: CS3.

CSR4

HASH context swap registers

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS4
rw
Toggle fields

CS4

Bits 0-31: CS4.

CSR5

HASH context swap registers

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS5
rw
Toggle fields

CS5

Bits 0-31: CS5.

CSR6

HASH context swap registers

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS6
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS6
rw
Toggle fields

CS6

Bits 0-31: CS6.

CSR7

HASH context swap registers

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS7
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS7
rw
Toggle fields

CS7

Bits 0-31: CS7.

CSR8

HASH context swap registers

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS8
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS8
rw
Toggle fields

CS8

Bits 0-31: CS8.

CSR9

HASH context swap registers

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS9
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS9
rw
Toggle fields

CS9

Bits 0-31: CS9.

CSR10

HASH context swap registers

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS10
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS10
rw
Toggle fields

CS10

Bits 0-31: CS10.

CSR11

HASH context swap registers

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS11
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS11
rw
Toggle fields

CS11

Bits 0-31: CS11.

CSR12

HASH context swap registers

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS12
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS12
rw
Toggle fields

CS12

Bits 0-31: CS12.

CSR13

HASH context swap registers

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS13
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS13
rw
Toggle fields

CS13

Bits 0-31: CS13.

CSR14

HASH context swap registers

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS14
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS14
rw
Toggle fields

CS14

Bits 0-31: CS14.

CSR15

HASH context swap registers

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS15
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS15
rw
Toggle fields

CS15

Bits 0-31: CS15.

CSR16

HASH context swap registers

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS16
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS16
rw
Toggle fields

CS16

Bits 0-31: CS16.

CSR17

HASH context swap registers

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS17
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS17
rw
Toggle fields

CS17

Bits 0-31: CS17.

CSR18

HASH context swap registers

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS18
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS18
rw
Toggle fields

CS18

Bits 0-31: CS18.

CSR19

HASH context swap registers

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS19
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS19
rw
Toggle fields

CS19

Bits 0-31: CS19.

CSR20

HASH context swap registers

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS20
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS20
rw
Toggle fields

CS20

Bits 0-31: CS20.

CSR21

HASH context swap registers

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS21
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS21
rw
Toggle fields

CS21

Bits 0-31: CS21.

CSR22

HASH context swap registers

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS22
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS22
rw
Toggle fields

CS22

Bits 0-31: CS22.

CSR23

HASH context swap registers

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS23
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS23
rw
Toggle fields

CS23

Bits 0-31: CS23.

CSR24

HASH context swap registers

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS24
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS24
rw
Toggle fields

CS24

Bits 0-31: CS24.

CSR25

HASH context swap registers

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS25
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS25
rw
Toggle fields

CS25

Bits 0-31: CS25.

CSR26

HASH context swap registers

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS26
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS26
rw
Toggle fields

CS26

Bits 0-31: CS26.

CSR27

HASH context swap registers

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS27
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS27
rw
Toggle fields

CS27

Bits 0-31: CS27.

CSR28

HASH context swap registers

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS28
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS28
rw
Toggle fields

CS28

Bits 0-31: CS28.

CSR29

HASH context swap registers

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS29
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS29
rw
Toggle fields

CS29

Bits 0-31: CS29.

CSR30

HASH context swap registers

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS30
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS30
rw
Toggle fields

CS30

Bits 0-31: CS30.

CSR31

HASH context swap registers

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS31
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS31
rw
Toggle fields

CS31

Bits 0-31: CS31.

CSR32

HASH context swap registers

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS32
rw
Toggle fields

CS32

Bits 0-31: CS32.

CSR33

HASH context swap registers

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS33
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS33
rw
Toggle fields

CS33

Bits 0-31: CS33.

CSR34

HASH context swap registers

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS34
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS34
rw
Toggle fields

CS34

Bits 0-31: CS34.

CSR35

HASH context swap registers

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS35
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS35
rw
Toggle fields

CS35

Bits 0-31: CS35.

CSR36

HASH context swap registers

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS36
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS36
rw
Toggle fields

CS36

Bits 0-31: CS36.

CSR37

HASH context swap registers

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS37
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS37
rw
Toggle fields

CS37

Bits 0-31: CS37.

CSR38

HASH context swap registers

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS38
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS38
rw
Toggle fields

CS38

Bits 0-31: CS38.

CSR39

HASH context swap registers

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS39
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS39
rw
Toggle fields

CS39

Bits 0-31: CS39.

CSR40

HASH context swap registers

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS40
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS40
rw
Toggle fields

CS40

Bits 0-31: CS40.

CSR41

HASH context swap registers

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS41
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS41
rw
Toggle fields

CS41

Bits 0-31: CS41.

CSR42

HASH context swap registers

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS42
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS42
rw
Toggle fields

CS42

Bits 0-31: CS42.

CSR43

HASH context swap registers

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS43
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS43
rw
Toggle fields

CS43

Bits 0-31: CS43.

CSR44

HASH context swap registers

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS44
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS44
rw
Toggle fields

CS44

Bits 0-31: CS44.

CSR45

HASH context swap registers

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS45
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS45
rw
Toggle fields

CS45

Bits 0-31: CS45.

CSR46

HASH context swap registers

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS46
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS46
rw
Toggle fields

CS46

Bits 0-31: CS46.

CSR47

HASH context swap registers

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS47
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS47
rw
Toggle fields

CS47

Bits 0-31: CS47.

CSR48

HASH context swap registers

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS48
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS48
rw
Toggle fields

CS48

Bits 0-31: CS48.

CSR49

HASH context swap registers

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS49
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS49
rw
Toggle fields

CS49

Bits 0-31: CS49.

CSR50

HASH context swap registers

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS50
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS50
rw
Toggle fields

CS50

Bits 0-31: CS50.

CSR51

HASH context swap registers

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS51
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS51
rw
Toggle fields

CS51

Bits 0-31: CS51.

CSR52

HASH context swap registers

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS52
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS52
rw
Toggle fields

CS52

Bits 0-31: CS52.

CSR53

HASH context swap registers

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS53
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS53
rw
Toggle fields

CS53

Bits 0-31: CS53.

HR5

HASH digest register 5

Offset: 0x324, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H5
r
Toggle fields

H5

Bits 0-31: H5.

HR6

HASH digest register 6

Offset: 0x328, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H6
r
Toggle fields

H6

Bits 0-31: H6.

HR7

HASH digest register 7

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
H7
r
Toggle fields

H7

Bits 0-31: H7.

HWCFGR

HASH Hardware Configuration Register

Offset: 0x3f0, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

VERR

HASH Version Register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VER
r
Toggle fields

VER

Bits 0-7: VER.

IPIDR

HASH Identification

Offset: 0x3f8, size: 32, reset: 0x00170031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

MID

HASH Hardware Magic ID

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MID
r
Toggle fields

MID

Bits 0-31: MID.

HDMI_CEC

0x40016000: HDMI_CEC

1/40 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 CFGR
0x8 TXDR
0xc RXDR
0x10 ISR
0x14 IER
Toggle registers

CR

CEC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXEOM
rw 		TXSOM
rw 		CECEN
rw
Toggle fields

CECEN

Bit 0: CECEN.

TXSOM

Bit 1: TXSOM.

TXEOM

Bit 2: TXEOM.

CFGR

This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LSTN
rw 		OAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFTOP
rw 		BRDNOGEN
rw 		LBPEGEN
rw 		BREGEN
rw 		BRESTP
rw 		RXTOL
rw 		SFT
rw
Toggle fields

SFT

Bits 0-2: SFT.

RXTOL

Bit 3: RXTOL.

BRESTP

Bit 4: BRESTP.

BREGEN

Bit 5: BREGEN.

LBPEGEN

Bit 6: LBPEGEN.

BRDNOGEN

Bit 7: BRDNOGEN.

SFTOP

Bit 8: SFTOP.

OAR

Bits 16-30: OAR.

LSTN

Bit 31: LSTN.

TXDR

CEC Tx data register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXD
w
Toggle fields

TXD

Bits 0-7: TXD.

RXDR

CEC Rx data register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXD
r
Toggle fields

RXD

Bits 0-7: RXD.

ISR

CEC Interrupt and Status Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACKE
rw 		TXERR
rw 		TXUDR
rw 		TXEND
rw 		TXBR
rw 		ARBLST
rw 		RXACKE
rw 		LBPE
rw 		SBPE
rw 		BRE
rw 		RXOVR
rw 		RXEND
rw 		RXBR
rw
Toggle fields

RXBR

Bit 0: RXBR.

RXEND

Bit 1: RXEND.

RXOVR

Bit 2: RXOVR.

BRE

Bit 3: BRE.

SBPE

Bit 4: SBPE.

LBPE

Bit 5: LBPE.

RXACKE

Bit 6: RXACKE.

ARBLST

Bit 7: ARBLST.

TXBR

Bit 8: TXBR.

TXEND

Bit 9: TXEND.

TXUDR

Bit 10: TXUDR.

TXERR

Bit 11: TXERR.

TXACKE

Bit 12: TXACKE.

IER

CEC interrupt enable register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXACKIE
rw 		TXERRIE
rw 		TXUDRIE
rw 		TXENDIE
rw 		TXBRIE
rw 		ARBLSTIE
rw 		RXACKIE
rw 		LBPEIE
rw 		SBPEIE
rw 		BREIE
rw 		RXOVRIE
rw 		RXENDIE
rw 		RXBRIE
rw
Toggle fields

RXBRIE

Bit 0: RXBRIE.

RXENDIE

Bit 1: RXENDIE.

RXOVRIE

Bit 2: RXOVRIE.

BREIE

Bit 3: BREIE.

SBPEIE

Bit 4: SBPEIE.

LBPEIE

Bit 5: LBPEIE.

RXACKIE

Bit 6: RXACKIE.

ARBLSTIE

Bit 7: ARBLSTIE.

TXBRIE

Bit 8: TXBRIE.

TXENDIE

Bit 9: TXENDIE.

TXUDRIE

Bit 10: TXUDRIE.

TXERRIE

Bit 11: TXERRIE.

TXACKIE

Bit 12: TXACKIE.

HDP

0x5002a000: HDP

5/17 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CTRL
0x4 MUX
0x10 VAL
0x14 GPOSET
0x18 GPOCLR
0x1c GPOVAL
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CTRL

HDP Control

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN
rw
Toggle fields

EN

Bit 0: EN.

MUX

HDP multiplexing

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MUX7
rw 		MUX6
rw 		MUX5
rw 		MUX4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MUX3
rw 		MUX2
rw 		MUX1
rw 		MUX0
rw
Toggle fields

MUX0

Bits 0-3: MUX0.

MUX1

Bits 4-7: MUX1.

MUX2

Bits 8-11: MUX2.

MUX3

Bits 12-15: MUX3.

MUX4

Bits 16-19: MUX4.

MUX5

Bits 20-23: MUX5.

MUX6

Bits 24-27: MUX6.

MUX7

Bits 28-31: MUX7.

VAL

HDP value

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDPVAL
r
Toggle fields

HDPVAL

Bits 0-7: HDPVAL.

GPOSET

HDP GPO set

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDPGPOSET
w
Toggle fields

HDPGPOSET

Bits 0-7: HDPGPOSET.

GPOCLR

HDP GPO clear

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDPGPOCLR
w
Toggle fields

HDPGPOCLR

Bits 0-7: HDPGPOCLR.

GPOVAL

HDP GPO value

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDPGPOVAL
rw
Toggle fields

HDPGPOVAL

Bits 0-7: HDPGPOVAL.

VERR

HDP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

HDP IP identification register

Offset: 0x3f8, size: 32, reset: 0x00030002, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

HDP size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

HSEM

0x4c000000: HSEM

110/213 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 R0
0x4 R1
0x8 R2
0xc R3
0x10 R4
0x14 R5
0x18 R6
0x1c R7
0x20 R8
0x24 R9
0x28 R10
0x2c R11
0x30 R12
0x34 R13
0x38 R14
0x3c R15
0x40 R16
0x44 R17
0x48 R18
0x4c R19
0x50 R20
0x54 R21
0x58 R22
0x5c R23
0x60 R24
0x64 R25
0x68 R26
0x6c R27
0x70 R28
0x74 R29
0x78 R30
0x7c R31
0x80 RLR0
0x84 RLR1
0x88 RLR2
0x8c RLR3
0x90 RLR4
0x94 RLR5
0x98 RLR6
0x9c RLR7
0xa0 RLR8
0xa4 RLR9
0xa8 RLR10
0xac RLR11
0xb0 RLR12
0xb4 RLR13
0xb8 RLR14
0xbc RLR15
0xc0 RLR16
0xc4 RLR17
0xc8 RLR18
0xcc RLR19
0xd0 RLR20
0xd4 RLR21
0xd8 RLR22
0xdc RLR23
0xe0 RLR24
0xe4 RLR25
0xe8 RLR26
0xec RLR27
0xf0 RLR28
0xf4 RLR29
0xf8 RLR30
0xfc RLR31
0x100 C1IER
0x104 C1ICR
0x108 C1ISR
0x10c C1MISR
0x110 C2IER
0x114 C2ICR
0x118 C2ISR
0x11c C2MISR
0x140 CR
0x144 KEYR
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

R0

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R1

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R2

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R3

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R4

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R5

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R6

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R7

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R8

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R9

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R10

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R11

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R12

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R13

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R14

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R15

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R16

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R17

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R18

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R19

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R20

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R21

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R22

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R23

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R24

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R25

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R26

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R27

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x6c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R28

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R29

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R30

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x78, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

R31

The HSEM_Rx shall be used to perform a 2-step Write lock and Read back. Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x7c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
rw 		PROCID
rw
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR0

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR1

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR2

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR3

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR4

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR5

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR6

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x98, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR7

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR8

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR9

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR10

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR11

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR12

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR13

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR14

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR15

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR16

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR17

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR18

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR19

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR20

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR21

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR22

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR23

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR24

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR25

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR26

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR27

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xec, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR28

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR29

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR30

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xf8, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

RLR31

Accesses the same physical bits as HSEM_Rx. The HSEM_RLRx shall be used to perform a 1-step Read lock. Only Read accesses with authorized AHB bus master IDs are granted. Read accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0xfc, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
r 		PROCID
r
Toggle fields

PROCID

Bits 0-7: PROCID.

COREID

Bits 8-11: COREID.

LOCK

Bit 31: LOCK.

C1IER

HSEM i1terrupt enable register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISE
rw
Toggle fields

ISE

Bits 0-31: ISE.

C1ICR

HSEM i1terrupt clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISC
rw
Toggle fields

ISC

Bits 0-31: ISC.

C1ISR

HSEM i1terrupt status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISF
r
Toggle fields

ISF

Bits 0-31: ISF.

C1MISR

HSEM i1terrupt status register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISF
r
Toggle fields

MISF

Bits 0-31: MISF.

C2IER

HSEM i2terrupt enable register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISE
rw
Toggle fields

ISE

Bits 0-31: ISE.

C2ICR

HSEM i2terrupt clear register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISC
rw
Toggle fields

ISC

Bits 0-31: ISC.

C2ISR

HSEM i2terrupt status register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ISF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISF
r
Toggle fields

ISF

Bits 0-31: ISF.

C2MISR

HSEM i2terrupt status register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MISF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISF
r
Toggle fields

MISF

Bits 0-31: MISF.

CR

Only Write accesses with authorized AHB bus master IDs are granted. Write accesses with unauthorized AHB bus master IDs are discarded.

Offset: 0x140, size: 32, reset: 0x00000000, access: write-only

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COREID
w
Toggle fields

COREID

Bits 8-11: COREID.

KEY

Bits 16-31: KEY.

KEYR

HSEM interrupt clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

KEY

Bits 16-31: KEY.

HWCFGR2

HSEM hardware configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000021, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASTERID4
r 		MASTERID3
r 		MASTERID2
r 		MASTERID1
r
Toggle fields

MASTERID1

Bits 0-3: MASTERID1.

MASTERID2

Bits 4-7: MASTERID2.

MASTERID3

Bits 8-11: MASTERID3.

MASTERID4

Bits 12-15: MASTERID4.

HWCFGR1

HSEM hardware configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000220, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBINT
r 		NBSEM
r
Toggle fields

NBSEM

Bits 0-7: NBSEM.

NBINT

Bits 8-11: NBINT.

VERR

HSEM IP version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

HSEM IP identification register

Offset: 0x3f8, size: 32, reset: 0x00100072, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IPID.

SIDR

HSEM size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

I2C1

0x40012000: I2C1

24/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: PE.

TXIE

Bit 1: TXIE.

RXIE

Bit 2: RXIE.

ADDRIE

Bit 3: ADDRIE.

NACKIE

Bit 4: NACKIE.

STOPIE

Bit 5: STOPIE.

TCIE

Bit 6: TCIE.

ERRIE

Bit 7: ERRIE.

DNF

Bits 8-11: DNF.

ANFOFF

Bit 12: ANFOFF.

TXDMAEN

Bit 14: TXDMAEN.

RXDMAEN

Bit 15: RXDMAEN.

SBC

Bit 16: SBC.

NOSTRETCH

Bit 17: NOSTRETCH.

WUPEN

Bit 18: WUPEN.

GCEN

Bit 19: GCEN.

SMBHEN

Bit 20: SMBHEN.

SMBDEN

Bit 21: SMBDEN.

ALERTEN

Bit 22: ALERTEN.

PECEN

Bit 23: PECEN.

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: SADD.

RD_WRN

Bit 10: RD_WRN.

ADD10

Bit 11: ADD10.

HEAD10R

Bit 12: HEAD10R.

START

Bit 13: START.

STOP

Bit 14: STOP.

NACK

Bit 15: NACK.

NBYTES

Bits 16-23: NBYTES.

RELOAD

Bit 24: RELOAD.

AUTOEND

Bit 25: AUTOEND.

PECBYTE

Bit 26: PECBYTE.

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: OA1.

OA1MODE

Bit 10: OA1MODE.

OA1EN

Bit 15: OA1EN.

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: OA2.

OA2MSK

Bits 8-10: OA2MSK.

OA2EN

Bit 15: OA2EN.

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCLL.

SCLH

Bits 8-15: SCLH.

SDADEL

Bits 16-19: SDADEL.

SCLDEL

Bits 20-23: SCLDEL.

PRESC

Bits 28-31: PRESC.

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: TIMEOUTA.

TIDLE

Bit 12: TIDLE.

TIMOUTEN

Bit 15: TIMOUTEN.

TIMEOUTB

Bits 16-27: TIMEOUTB.

TEXTEN

Bit 31: TEXTEN.

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: TXE.

TXIS

Bit 1: TXIS.

RXNE

Bit 2: RXNE.

ADDR

Bit 3: ADDR.

NACKF

Bit 4: NACKF.

STOPF

Bit 5: STOPF.

TC

Bit 6: TC.

TCR

Bit 7: TCR.

BERR

Bit 8: BERR.

ARLO

Bit 9: ARLO.

OVR

Bit 10: OVR.

PECERR

Bit 11: PECERR.

TIMEOUT

Bit 12: TIMEOUT.

ALERT

Bit 13: ALERT.

BUSY

Bit 15: BUSY.

DIR

Bit 16: DIR.

ADDCODE

Bits 17-23: ADDCODE.

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: ADDRCF.

NACKCF

Bit 4: NACKCF.

STOPCF

Bit 5: STOPCF.

BERRCF

Bit 8: BERRCF.

ARLOCF

Bit 9: ARLOCF.

OVRCF

Bit 10: OVRCF.

PECCF

Bit 11: PECCF.

TIMOUTCF

Bit 12: TIMOUTCF.

ALERTCF

Bit 13: ALERTCF.

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: PEC.

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

HWCFGR

I2C hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000111, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKP
r 		ASYN
r 		SMBUS
r
Toggle fields

SMBUS

Bits 0-3: SMBUS.

ASYN

Bits 4-7: ASYN.

WKP

Bits 8-11: WKP.

VERR

I2C version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

I2C identification register

Offset: 0x3f8, size: 32, reset: 0x00130012, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

I2C size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

I2C2

0x40013000: I2C1

24/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: PE.

TXIE

Bit 1: TXIE.

RXIE

Bit 2: RXIE.

ADDRIE

Bit 3: ADDRIE.

NACKIE

Bit 4: NACKIE.

STOPIE

Bit 5: STOPIE.

TCIE

Bit 6: TCIE.

ERRIE

Bit 7: ERRIE.

DNF

Bits 8-11: DNF.

ANFOFF

Bit 12: ANFOFF.

TXDMAEN

Bit 14: TXDMAEN.

RXDMAEN

Bit 15: RXDMAEN.

SBC

Bit 16: SBC.

NOSTRETCH

Bit 17: NOSTRETCH.

WUPEN

Bit 18: WUPEN.

GCEN

Bit 19: GCEN.

SMBHEN

Bit 20: SMBHEN.

SMBDEN

Bit 21: SMBDEN.

ALERTEN

Bit 22: ALERTEN.

PECEN

Bit 23: PECEN.

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: SADD.

RD_WRN

Bit 10: RD_WRN.

ADD10

Bit 11: ADD10.

HEAD10R

Bit 12: HEAD10R.

START

Bit 13: START.

STOP

Bit 14: STOP.

NACK

Bit 15: NACK.

NBYTES

Bits 16-23: NBYTES.

RELOAD

Bit 24: RELOAD.

AUTOEND

Bit 25: AUTOEND.

PECBYTE

Bit 26: PECBYTE.

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: OA1.

OA1MODE

Bit 10: OA1MODE.

OA1EN

Bit 15: OA1EN.

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: OA2.

OA2MSK

Bits 8-10: OA2MSK.

OA2EN

Bit 15: OA2EN.

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCLL.

SCLH

Bits 8-15: SCLH.

SDADEL

Bits 16-19: SDADEL.

SCLDEL

Bits 20-23: SCLDEL.

PRESC

Bits 28-31: PRESC.

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: TIMEOUTA.

TIDLE

Bit 12: TIDLE.

TIMOUTEN

Bit 15: TIMOUTEN.

TIMEOUTB

Bits 16-27: TIMEOUTB.

TEXTEN

Bit 31: TEXTEN.

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: TXE.

TXIS

Bit 1: TXIS.

RXNE

Bit 2: RXNE.

ADDR

Bit 3: ADDR.

NACKF

Bit 4: NACKF.

STOPF

Bit 5: STOPF.

TC

Bit 6: TC.

TCR

Bit 7: TCR.

BERR

Bit 8: BERR.

ARLO

Bit 9: ARLO.

OVR

Bit 10: OVR.

PECERR

Bit 11: PECERR.

TIMEOUT

Bit 12: TIMEOUT.

ALERT

Bit 13: ALERT.

BUSY

Bit 15: BUSY.

DIR

Bit 16: DIR.

ADDCODE

Bits 17-23: ADDCODE.

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: ADDRCF.

NACKCF

Bit 4: NACKCF.

STOPCF

Bit 5: STOPCF.

BERRCF

Bit 8: BERRCF.

ARLOCF

Bit 9: ARLOCF.

OVRCF

Bit 10: OVRCF.

PECCF

Bit 11: PECCF.

TIMOUTCF

Bit 12: TIMOUTCF.

ALERTCF

Bit 13: ALERTCF.

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: PEC.

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

HWCFGR

I2C hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000111, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKP
r 		ASYN
r 		SMBUS
r
Toggle fields

SMBUS

Bits 0-3: SMBUS.

ASYN

Bits 4-7: ASYN.

WKP

Bits 8-11: WKP.

VERR

I2C version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

I2C identification register

Offset: 0x3f8, size: 32, reset: 0x00130012, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

I2C size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

I2C3

0x40014000: I2C1

24/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: PE.

TXIE

Bit 1: TXIE.

RXIE

Bit 2: RXIE.

ADDRIE

Bit 3: ADDRIE.

NACKIE

Bit 4: NACKIE.

STOPIE

Bit 5: STOPIE.

TCIE

Bit 6: TCIE.

ERRIE

Bit 7: ERRIE.

DNF

Bits 8-11: DNF.

ANFOFF

Bit 12: ANFOFF.

TXDMAEN

Bit 14: TXDMAEN.

RXDMAEN

Bit 15: RXDMAEN.

SBC

Bit 16: SBC.

NOSTRETCH

Bit 17: NOSTRETCH.

WUPEN

Bit 18: WUPEN.

GCEN

Bit 19: GCEN.

SMBHEN

Bit 20: SMBHEN.

SMBDEN

Bit 21: SMBDEN.

ALERTEN

Bit 22: ALERTEN.

PECEN

Bit 23: PECEN.

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: SADD.

RD_WRN

Bit 10: RD_WRN.

ADD10

Bit 11: ADD10.

HEAD10R

Bit 12: HEAD10R.

START

Bit 13: START.

STOP

Bit 14: STOP.

NACK

Bit 15: NACK.

NBYTES

Bits 16-23: NBYTES.

RELOAD

Bit 24: RELOAD.

AUTOEND

Bit 25: AUTOEND.

PECBYTE

Bit 26: PECBYTE.

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: OA1.

OA1MODE

Bit 10: OA1MODE.

OA1EN

Bit 15: OA1EN.

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: OA2.

OA2MSK

Bits 8-10: OA2MSK.

OA2EN

Bit 15: OA2EN.

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCLL.

SCLH

Bits 8-15: SCLH.

SDADEL

Bits 16-19: SDADEL.

SCLDEL

Bits 20-23: SCLDEL.

PRESC

Bits 28-31: PRESC.

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: TIMEOUTA.

TIDLE

Bit 12: TIDLE.

TIMOUTEN

Bit 15: TIMOUTEN.

TIMEOUTB

Bits 16-27: TIMEOUTB.

TEXTEN

Bit 31: TEXTEN.

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: TXE.

TXIS

Bit 1: TXIS.

RXNE

Bit 2: RXNE.

ADDR

Bit 3: ADDR.

NACKF

Bit 4: NACKF.

STOPF

Bit 5: STOPF.

TC

Bit 6: TC.

TCR

Bit 7: TCR.

BERR

Bit 8: BERR.

ARLO

Bit 9: ARLO.

OVR

Bit 10: OVR.

PECERR

Bit 11: PECERR.

TIMEOUT

Bit 12: TIMEOUT.

ALERT

Bit 13: ALERT.

BUSY

Bit 15: BUSY.

DIR

Bit 16: DIR.

ADDCODE

Bits 17-23: ADDCODE.

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: ADDRCF.

NACKCF

Bit 4: NACKCF.

STOPCF

Bit 5: STOPCF.

BERRCF

Bit 8: BERRCF.

ARLOCF

Bit 9: ARLOCF.

OVRCF

Bit 10: OVRCF.

PECCF

Bit 11: PECCF.

TIMOUTCF

Bit 12: TIMOUTCF.

ALERTCF

Bit 13: ALERTCF.

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: PEC.

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

HWCFGR

I2C hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000111, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKP
r 		ASYN
r 		SMBUS
r
Toggle fields

SMBUS

Bits 0-3: SMBUS.

ASYN

Bits 4-7: ASYN.

WKP

Bits 8-11: WKP.

VERR

I2C version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

I2C identification register

Offset: 0x3f8, size: 32, reset: 0x00130012, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

I2C size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

I2C4

0x5c002000: I2C1

24/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: PE.

TXIE

Bit 1: TXIE.

RXIE

Bit 2: RXIE.

ADDRIE

Bit 3: ADDRIE.

NACKIE

Bit 4: NACKIE.

STOPIE

Bit 5: STOPIE.

TCIE

Bit 6: TCIE.

ERRIE

Bit 7: ERRIE.

DNF

Bits 8-11: DNF.

ANFOFF

Bit 12: ANFOFF.

TXDMAEN

Bit 14: TXDMAEN.

RXDMAEN

Bit 15: RXDMAEN.

SBC

Bit 16: SBC.

NOSTRETCH

Bit 17: NOSTRETCH.

WUPEN

Bit 18: WUPEN.

GCEN

Bit 19: GCEN.

SMBHEN

Bit 20: SMBHEN.

SMBDEN

Bit 21: SMBDEN.

ALERTEN

Bit 22: ALERTEN.

PECEN

Bit 23: PECEN.

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: SADD.

RD_WRN

Bit 10: RD_WRN.

ADD10

Bit 11: ADD10.

HEAD10R

Bit 12: HEAD10R.

START

Bit 13: START.

STOP

Bit 14: STOP.

NACK

Bit 15: NACK.

NBYTES

Bits 16-23: NBYTES.

RELOAD

Bit 24: RELOAD.

AUTOEND

Bit 25: AUTOEND.

PECBYTE

Bit 26: PECBYTE.

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: OA1.

OA1MODE

Bit 10: OA1MODE.

OA1EN

Bit 15: OA1EN.

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: OA2.

OA2MSK

Bits 8-10: OA2MSK.

OA2EN

Bit 15: OA2EN.

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCLL.

SCLH

Bits 8-15: SCLH.

SDADEL

Bits 16-19: SDADEL.

SCLDEL

Bits 20-23: SCLDEL.

PRESC

Bits 28-31: PRESC.

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: TIMEOUTA.

TIDLE

Bit 12: TIDLE.

TIMOUTEN

Bit 15: TIMOUTEN.

TIMEOUTB

Bits 16-27: TIMEOUTB.

TEXTEN

Bit 31: TEXTEN.

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: TXE.

TXIS

Bit 1: TXIS.

RXNE

Bit 2: RXNE.

ADDR

Bit 3: ADDR.

NACKF

Bit 4: NACKF.

STOPF

Bit 5: STOPF.

TC

Bit 6: TC.

TCR

Bit 7: TCR.

BERR

Bit 8: BERR.

ARLO

Bit 9: ARLO.

OVR

Bit 10: OVR.

PECERR

Bit 11: PECERR.

TIMEOUT

Bit 12: TIMEOUT.

ALERT

Bit 13: ALERT.

BUSY

Bit 15: BUSY.

DIR

Bit 16: DIR.

ADDCODE

Bits 17-23: ADDCODE.

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: ADDRCF.

NACKCF

Bit 4: NACKCF.

STOPCF

Bit 5: STOPCF.

BERRCF

Bit 8: BERRCF.

ARLOCF

Bit 9: ARLOCF.

OVRCF

Bit 10: OVRCF.

PECCF

Bit 11: PECCF.

TIMOUTCF

Bit 12: TIMOUTCF.

ALERTCF

Bit 13: ALERTCF.

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: PEC.

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

HWCFGR

I2C hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000111, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKP
r 		ASYN
r 		SMBUS
r
Toggle fields

SMBUS

Bits 0-3: SMBUS.

ASYN

Bits 4-7: ASYN.

WKP

Bits 8-11: WKP.

VERR

I2C version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

I2C identification register

Offset: 0x3f8, size: 32, reset: 0x00130012, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

I2C size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

I2C5

0x40015000: I2C1

24/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: PE.

TXIE

Bit 1: TXIE.

RXIE

Bit 2: RXIE.

ADDRIE

Bit 3: ADDRIE.

NACKIE

Bit 4: NACKIE.

STOPIE

Bit 5: STOPIE.

TCIE

Bit 6: TCIE.

ERRIE

Bit 7: ERRIE.

DNF

Bits 8-11: DNF.

ANFOFF

Bit 12: ANFOFF.

TXDMAEN

Bit 14: TXDMAEN.

RXDMAEN

Bit 15: RXDMAEN.

SBC

Bit 16: SBC.

NOSTRETCH

Bit 17: NOSTRETCH.

WUPEN

Bit 18: WUPEN.

GCEN

Bit 19: GCEN.

SMBHEN

Bit 20: SMBHEN.

SMBDEN

Bit 21: SMBDEN.

ALERTEN

Bit 22: ALERTEN.

PECEN

Bit 23: PECEN.

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: SADD.

RD_WRN

Bit 10: RD_WRN.

ADD10

Bit 11: ADD10.

HEAD10R

Bit 12: HEAD10R.

START

Bit 13: START.

STOP

Bit 14: STOP.

NACK

Bit 15: NACK.

NBYTES

Bits 16-23: NBYTES.

RELOAD

Bit 24: RELOAD.

AUTOEND

Bit 25: AUTOEND.

PECBYTE

Bit 26: PECBYTE.

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: OA1.

OA1MODE

Bit 10: OA1MODE.

OA1EN

Bit 15: OA1EN.

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: OA2.

OA2MSK

Bits 8-10: OA2MSK.

OA2EN

Bit 15: OA2EN.

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCLL.

SCLH

Bits 8-15: SCLH.

SDADEL

Bits 16-19: SDADEL.

SCLDEL

Bits 20-23: SCLDEL.

PRESC

Bits 28-31: PRESC.

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: TIMEOUTA.

TIDLE

Bit 12: TIDLE.

TIMOUTEN

Bit 15: TIMOUTEN.

TIMEOUTB

Bits 16-27: TIMEOUTB.

TEXTEN

Bit 31: TEXTEN.

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: TXE.

TXIS

Bit 1: TXIS.

RXNE

Bit 2: RXNE.

ADDR

Bit 3: ADDR.

NACKF

Bit 4: NACKF.

STOPF

Bit 5: STOPF.

TC

Bit 6: TC.

TCR

Bit 7: TCR.

BERR

Bit 8: BERR.

ARLO

Bit 9: ARLO.

OVR

Bit 10: OVR.

PECERR

Bit 11: PECERR.

TIMEOUT

Bit 12: TIMEOUT.

ALERT

Bit 13: ALERT.

BUSY

Bit 15: BUSY.

DIR

Bit 16: DIR.

ADDCODE

Bits 17-23: ADDCODE.

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: ADDRCF.

NACKCF

Bit 4: NACKCF.

STOPCF

Bit 5: STOPCF.

BERRCF

Bit 8: BERRCF.

ARLOCF

Bit 9: ARLOCF.

OVRCF

Bit 10: OVRCF.

PECCF

Bit 11: PECCF.

TIMOUTCF

Bit 12: TIMOUTCF.

ALERTCF

Bit 13: ALERTCF.

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: PEC.

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

HWCFGR

I2C hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000111, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKP
r 		ASYN
r 		SMBUS
r
Toggle fields

SMBUS

Bits 0-3: SMBUS.

ASYN

Bits 4-7: ASYN.

WKP

Bits 8-11: WKP.

VERR

I2C version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

I2C identification register

Offset: 0x3f8, size: 32, reset: 0x00130012, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

I2C size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

I2C6

0x5c009000: I2C1

24/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 OAR1
0xc OAR2
0x10 TIMINGR
0x14 TIMEOUTR
0x18 ISR
0x1c ICR
0x20 PECR
0x24 RXDR
0x28 TXDR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2xi2c_pclk+6xi2c_ker_ck.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECEN
rw 		ALERTEN
rw 		SMBDEN
rw 		SMBHEN
rw 		GCEN
rw 		WUPEN
rw 		NOSTRETCH
rw 		SBC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMAEN
rw 		TXDMAEN
rw 		ANFOFF
rw 		DNF
rw 		ERRIE
rw 		TCIE
rw 		STOPIE
rw 		NACKIE
rw 		ADDRIE
rw 		RXIE
rw 		TXIE
rw 		PE
rw
Toggle fields

PE

Bit 0: PE.

TXIE

Bit 1: TXIE.

RXIE

Bit 2: RXIE.

ADDRIE

Bit 3: ADDRIE.

NACKIE

Bit 4: NACKIE.

STOPIE

Bit 5: STOPIE.

TCIE

Bit 6: TCIE.

ERRIE

Bit 7: ERRIE.

DNF

Bits 8-11: DNF.

ANFOFF

Bit 12: ANFOFF.

TXDMAEN

Bit 14: TXDMAEN.

RXDMAEN

Bit 15: RXDMAEN.

SBC

Bit 16: SBC.

NOSTRETCH

Bit 17: NOSTRETCH.

WUPEN

Bit 18: WUPEN.

GCEN

Bit 19: GCEN.

SMBHEN

Bit 20: SMBHEN.

SMBDEN

Bit 21: SMBDEN.

ALERTEN

Bit 22: ALERTEN.

PECEN

Bit 23: PECEN.

CR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PECBYTE
rw 		AUTOEND
rw 		RELOAD
rw 		NBYTES
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NACK
rw 		STOP
rw 		START
rw 		HEAD10R
rw 		ADD10
rw 		RD_WRN
rw 		SADD
rw
Toggle fields

SADD

Bits 0-9: SADD.

RD_WRN

Bit 10: RD_WRN.

ADD10

Bit 11: ADD10.

HEAD10R

Bit 12: HEAD10R.

START

Bit 13: START.

STOP

Bit 14: STOP.

NACK

Bit 15: NACK.

NBYTES

Bits 16-23: NBYTES.

RELOAD

Bit 24: RELOAD.

AUTOEND

Bit 25: AUTOEND.

PECBYTE

Bit 26: PECBYTE.

OAR1

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1EN
rw 		OA1MODE
rw 		OA1
rw
Toggle fields

OA1

Bits 0-9: OA1.

OA1MODE

Bit 10: OA1MODE.

OA1EN

Bit 15: OA1EN.

OAR2

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN
rw 		OA2MSK
rw 		OA2
rw
Toggle fields

OA2

Bits 1-7: OA2.

OA2MSK

Bits 8-10: OA2MSK.

OA2EN

Bit 15: OA2EN.

TIMINGR

Access: No wait states

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESC
rw 		SCLDEL
rw 		SDADEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH
rw 		SCLL
rw
Toggle fields

SCLL

Bits 0-7: SCLL.

SCLH

Bits 8-15: SCLH.

SDADEL

Bits 16-19: SDADEL.

SCLDEL

Bits 20-23: SCLDEL.

PRESC

Bits 28-31: PRESC.

TIMEOUTR

Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x i2c_pclk + 6 x i2c_ker_ck.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN
rw 		TIMEOUTB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN
rw 		TIDLE
rw 		TIMEOUTA
rw
Toggle fields

TIMEOUTA

Bits 0-11: TIMEOUTA.

TIDLE

Bit 12: TIDLE.

TIMOUTEN

Bit 15: TIMOUTEN.

TIMEOUTB

Bits 16-27: TIMEOUTB.

TEXTEN

Bit 31: TEXTEN.

ISR

Access: No wait states

Offset: 0x18, size: 32, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDCODE
r 		DIR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
r 		ALERT
r 		TIMEOUT
r 		PECERR
r 		OVR
r 		ARLO
r 		BERR
r 		TCR
r 		TC
r 		STOPF
r 		NACKF
r 		ADDR
r 		RXNE
r 		TXIS
rw 		TXE
rw
Toggle fields

TXE

Bit 0: TXE.

TXIS

Bit 1: TXIS.

RXNE

Bit 2: RXNE.

ADDR

Bit 3: ADDR.

NACKF

Bit 4: NACKF.

STOPF

Bit 5: STOPF.

TC

Bit 6: TC.

TCR

Bit 7: TCR.

BERR

Bit 8: BERR.

ARLO

Bit 9: ARLO.

OVR

Bit 10: OVR.

PECERR

Bit 11: PECERR.

TIMEOUT

Bit 12: TIMEOUT.

ALERT

Bit 13: ALERT.

BUSY

Bit 15: BUSY.

DIR

Bit 16: DIR.

ADDCODE

Bits 17-23: ADDCODE.

ICR

Access: No wait states

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERTCF
w 		TIMOUTCF
w 		PECCF
w 		OVRCF
w 		ARLOCF
w 		BERRCF
w 		STOPCF
w 		NACKCF
w 		ADDRCF
w
Toggle fields

ADDRCF

Bit 3: ADDRCF.

NACKCF

Bit 4: NACKCF.

STOPCF

Bit 5: STOPCF.

BERRCF

Bit 8: BERRCF.

ARLOCF

Bit 9: ARLOCF.

OVRCF

Bit 10: OVRCF.

PECCF

Bit 11: PECCF.

TIMOUTCF

Bit 12: TIMOUTCF.

ALERTCF

Bit 13: ALERTCF.

PECR

Access: No wait states

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEC
r
Toggle fields

PEC

Bits 0-7: PEC.

RXDR

Access: No wait states

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDATA
r
Toggle fields

RXDATA

Bits 0-7: RXDATA.

TXDR

Access: No wait states

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATA
rw
Toggle fields

TXDATA

Bits 0-7: TXDATA.

HWCFGR

I2C hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000111, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKP
r 		ASYN
r 		SMBUS
r
Toggle fields

SMBUS

Bits 0-3: SMBUS.

ASYN

Bits 4-7: ASYN.

WKP

Bits 8-11: WKP.

VERR

I2C version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

I2C identification register

Offset: 0x3f8, size: 32, reset: 0x00130012, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

I2C size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

IPCC

0x4c001000: IPCC

7/19 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 C1CR
0x4 C1MR
0x8 C1SCR
0xc C1TOC2SR
0x10 C2CR
0x14 C2MR
0x18 C2SCR
0x1c C2TOC1SR
0x3f0 HWCFGR
0x3f4 VER
0x3f8 ID
0x3fc SID
Toggle registers

C1CR

IPCC Processor 1 control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXOIE
rw
Toggle fields

RXOIE

Bit 0: RXOIE.

TXFIE

Bit 16: TXFIE.

C1MR

IPCC Processor 1 mask register

Offset: 0x4, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHxFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHxOM
rw
Toggle fields

CHxOM

Bits 0-5: CHxOM.

CHxFM

Bits 16-21: CHxFM.

C1SCR

Reading this register will always return 0x0000 0000.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHxS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHxC
rw
Toggle fields

CHxC

Bits 0-5: CHxC.

CHxS

Bits 16-21: CHxS.

C1TOC2SR

IPCC processor 1 to processor 2 status register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHxF
r
Toggle fields

CHxF

Bits 0-5: CHxF.

C2CR

IPCC Processor 2 control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXOIE
rw
Toggle fields

RXOIE

Bit 0: RXOIE.

TXFIE

Bit 16: TXFIE.

C2MR

IPCC Processor 2 mask register

Offset: 0x14, size: 32, reset: 0xFFFFFFFF, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHxFM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHxOM
rw
Toggle fields

CHxOM

Bits 0-5: CHxOM.

CHxFM

Bits 16-21: CHxFM.

C2SCR

Reading this register will always return 0x0000 0000.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHxS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHxC
rw
Toggle fields

CHxC

Bits 0-5: CHxC.

CHxS

Bits 16-21: CHxS.

C2TOC1SR

IPCC processor 2 to processor 1 status register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHxF
r
Toggle fields

CHxF

Bits 0-5: CHxF.

HWCFGR

IPCC Hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000002, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHANNELS
r
Toggle fields

CHANNELS

Bits 0-7: CHANNELS.

VER

IPCC IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

ID

IPCC IP Identification register

Offset: 0x3f8, size: 32, reset: 0x00100071, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IPID.

SID

IPCC Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

IWDG1

0x5c003000: IWDG1

9/16 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) KR
0x4 (16-bit) PR
0x8 (16-bit) RLR
0xc (16-bit) SR
0x10 (16-bit) WINR
0x14 EWCR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IDR
0x3fc SIDR
Toggle registers

KR

Key register

Offset: 0x0, size: 16, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: KEY.

PR

Prescaler register

Offset: 0x4, size: 16, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: PR.

RLR

Reload register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: RL.

SR

Status register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: PVU.

RVU

Bit 1: RVU.

WVU

Bit 2: WVU.

WINR

Window register

Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: WIN.

EWCR

IWDG early wake-up interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		EWIC
rw 		EWIT
rw
Toggle fields

EWIT

Bits 0-11: EWIT.

EWIC

Bit 14: EWIC.

EWIE

Bit 15: EWIE.

HWCFGR

IWDG hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000071, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR_DEFAULT
r 		WINDOW
r
Toggle fields

WINDOW

Bits 0-3: WINDOW.

PR_DEFAULT

Bits 4-7: PR_DEFAULT.

VERR

IWDG version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IDR

IWDG identification register

Offset: 0x3f8, size: 32, reset: 0x00120041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

IWDG size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

IWDG2

0x5a002000: IWDG1

9/16 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) KR
0x4 (16-bit) PR
0x8 (16-bit) RLR
0xc (16-bit) SR
0x10 (16-bit) WINR
0x14 EWCR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IDR
0x3fc SIDR
Toggle registers

KR

Key register

Offset: 0x0, size: 16, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-15: KEY.

PR

Prescaler register

Offset: 0x4, size: 16, reset: 0x00000007, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR
rw
Toggle fields

PR

Bits 0-2: PR.

RLR

Reload register

Offset: 0x8, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RL
rw
Toggle fields

RL

Bits 0-11: RL.

SR

Status register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVU
r 		RVU
r 		PVU
r
Toggle fields

PVU

Bit 0: PVU.

RVU

Bit 1: RVU.

WVU

Bit 2: WVU.

WINR

Window register

Offset: 0x10, size: 16, reset: 0x00000FFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIN
rw
Toggle fields

WIN

Bits 0-11: WIN.

EWCR

IWDG early wake-up interrupt register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIE
rw 		EWIC
rw 		EWIT
rw
Toggle fields

EWIT

Bits 0-11: EWIT.

EWIC

Bit 14: EWIC.

EWIE

Bit 15: EWIE.

HWCFGR

IWDG hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000071, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PR_DEFAULT
r 		WINDOW
r
Toggle fields

WINDOW

Bits 0-3: WINDOW.

PR_DEFAULT

Bits 4-7: PR_DEFAULT.

VERR

IWDG version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IDR

IWDG identification register

Offset: 0x3f8, size: 32, reset: 0x00120041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

IWDG size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

LPTIM1

0x40009000: LPTIM1

16/52 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
0x3f0 LPTIM1_HWCFGR
0x3f4 VERR
0x3f8 PIDR
0x3fc SIDR
Toggle registers

ISR

LPTIM interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: CMPM.

ARRM

Bit 1: ARRM.

EXTTRIG

Bit 2: EXTTRIG.

CMPOK

Bit 3: CMPOK.

ARROK

Bit 4: ARROK.

UP

Bit 5: UP.

DOWN

Bit 6: DOWN.

ICR

LPTIM interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: CMPMCF.

ARRMCF

Bit 1: ARRMCF.

EXTTRIGCF

Bit 2: EXTTRIGCF.

CMPOKCF

Bit 3: CMPOKCF.

ARROKCF

Bit 4: ARROKCF.

UPCF

Bit 5: UPCF.

DOWNCF

Bit 6: DOWNCF.

IER

LPTIM interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: CMPMIE.

ARRMIE

Bit 1: ARRMIE.

EXTTRIGIE

Bit 2: EXTTRIGIE.

CMPOKIE

Bit 3: CMPOKIE.

ARROKIE

Bit 4: ARROKIE.

UPIE

Bit 5: UPIE.

DOWNIE

Bit 6: DOWNIE.

CFGR

LPTIM configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

LPTIM control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

LPTIM compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

ARR

LPTIM autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

CNT

LPTIM counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: CNT.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw 		IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: IN1SEL.

IN2SEL

Bits 4-5: IN2SEL.

LPTIM1_HWCFGR

LPTIM 1 peripheral hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00010804, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG4
r 		CFG3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-7: CFG1.

CFG2

Bits 8-15: CFG2.

CFG3

Bits 16-19: CFG3.

CFG4

Bits 24-31: CFG4.

VERR

LPTIM peripheral version identification register

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

PIDR

LPTIM peripheral type identification register

Offset: 0x3f8, size: 32, reset: 0x00120011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P_ID
r
Toggle fields

P_ID

Bits 0-31: P_ID.

SIDR

LPTIM registers map size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S_ID
r
Toggle fields

S_ID

Bits 0-31: S_ID.

LPTIM2

0x50021000: LPTIM1

16/52 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
0x3f0 LPTIM1_HWCFGR
0x3f4 VERR
0x3f8 PIDR
0x3fc SIDR
Toggle registers

ISR

LPTIM interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: CMPM.

ARRM

Bit 1: ARRM.

EXTTRIG

Bit 2: EXTTRIG.

CMPOK

Bit 3: CMPOK.

ARROK

Bit 4: ARROK.

UP

Bit 5: UP.

DOWN

Bit 6: DOWN.

ICR

LPTIM interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: CMPMCF.

ARRMCF

Bit 1: ARRMCF.

EXTTRIGCF

Bit 2: EXTTRIGCF.

CMPOKCF

Bit 3: CMPOKCF.

ARROKCF

Bit 4: ARROKCF.

UPCF

Bit 5: UPCF.

DOWNCF

Bit 6: DOWNCF.

IER

LPTIM interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: CMPMIE.

ARRMIE

Bit 1: ARRMIE.

EXTTRIGIE

Bit 2: EXTTRIGIE.

CMPOKIE

Bit 3: CMPOKIE.

ARROKIE

Bit 4: ARROKIE.

UPIE

Bit 5: UPIE.

DOWNIE

Bit 6: DOWNIE.

CFGR

LPTIM configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

LPTIM control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

LPTIM compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

ARR

LPTIM autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

CNT

LPTIM counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: CNT.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw 		IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: IN1SEL.

IN2SEL

Bits 4-5: IN2SEL.

LPTIM1_HWCFGR

LPTIM 1 peripheral hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00010804, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG4
r 		CFG3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-7: CFG1.

CFG2

Bits 8-15: CFG2.

CFG3

Bits 16-19: CFG3.

CFG4

Bits 24-31: CFG4.

VERR

LPTIM peripheral version identification register

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

PIDR

LPTIM peripheral type identification register

Offset: 0x3f8, size: 32, reset: 0x00120011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P_ID
r
Toggle fields

P_ID

Bits 0-31: P_ID.

SIDR

LPTIM registers map size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S_ID
r
Toggle fields

S_ID

Bits 0-31: S_ID.

LPTIM3

0x50022000: LPTIM1

16/52 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
0x3f0 LPTIM1_HWCFGR
0x3f4 VERR
0x3f8 PIDR
0x3fc SIDR
Toggle registers

ISR

LPTIM interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: CMPM.

ARRM

Bit 1: ARRM.

EXTTRIG

Bit 2: EXTTRIG.

CMPOK

Bit 3: CMPOK.

ARROK

Bit 4: ARROK.

UP

Bit 5: UP.

DOWN

Bit 6: DOWN.

ICR

LPTIM interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: CMPMCF.

ARRMCF

Bit 1: ARRMCF.

EXTTRIGCF

Bit 2: EXTTRIGCF.

CMPOKCF

Bit 3: CMPOKCF.

ARROKCF

Bit 4: ARROKCF.

UPCF

Bit 5: UPCF.

DOWNCF

Bit 6: DOWNCF.

IER

LPTIM interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: CMPMIE.

ARRMIE

Bit 1: ARRMIE.

EXTTRIGIE

Bit 2: EXTTRIGIE.

CMPOKIE

Bit 3: CMPOKIE.

ARROKIE

Bit 4: ARROKIE.

UPIE

Bit 5: UPIE.

DOWNIE

Bit 6: DOWNIE.

CFGR

LPTIM configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

LPTIM control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

LPTIM compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

ARR

LPTIM autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

CNT

LPTIM counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: CNT.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw 		IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: IN1SEL.

IN2SEL

Bits 4-5: IN2SEL.

LPTIM1_HWCFGR

LPTIM 1 peripheral hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00010804, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG4
r 		CFG3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-7: CFG1.

CFG2

Bits 8-15: CFG2.

CFG3

Bits 16-19: CFG3.

CFG4

Bits 24-31: CFG4.

VERR

LPTIM peripheral version identification register

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

PIDR

LPTIM peripheral type identification register

Offset: 0x3f8, size: 32, reset: 0x00120011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P_ID
r
Toggle fields

P_ID

Bits 0-31: P_ID.

SIDR

LPTIM registers map size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S_ID
r
Toggle fields

S_ID

Bits 0-31: S_ID.

LPTIM4

0x50023000: LPTIM1

16/52 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
0x3f0 LPTIM1_HWCFGR
0x3f4 VERR
0x3f8 PIDR
0x3fc SIDR
Toggle registers

ISR

LPTIM interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: CMPM.

ARRM

Bit 1: ARRM.

EXTTRIG

Bit 2: EXTTRIG.

CMPOK

Bit 3: CMPOK.

ARROK

Bit 4: ARROK.

UP

Bit 5: UP.

DOWN

Bit 6: DOWN.

ICR

LPTIM interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: CMPMCF.

ARRMCF

Bit 1: ARRMCF.

EXTTRIGCF

Bit 2: EXTTRIGCF.

CMPOKCF

Bit 3: CMPOKCF.

ARROKCF

Bit 4: ARROKCF.

UPCF

Bit 5: UPCF.

DOWNCF

Bit 6: DOWNCF.

IER

LPTIM interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: CMPMIE.

ARRMIE

Bit 1: ARRMIE.

EXTTRIGIE

Bit 2: EXTTRIGIE.

CMPOKIE

Bit 3: CMPOKIE.

ARROKIE

Bit 4: ARROKIE.

UPIE

Bit 5: UPIE.

DOWNIE

Bit 6: DOWNIE.

CFGR

LPTIM configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

LPTIM control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

LPTIM compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

ARR

LPTIM autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

CNT

LPTIM counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: CNT.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw 		IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: IN1SEL.

IN2SEL

Bits 4-5: IN2SEL.

LPTIM1_HWCFGR

LPTIM 1 peripheral hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00010804, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG4
r 		CFG3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-7: CFG1.

CFG2

Bits 8-15: CFG2.

CFG3

Bits 16-19: CFG3.

CFG4

Bits 24-31: CFG4.

VERR

LPTIM peripheral version identification register

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

PIDR

LPTIM peripheral type identification register

Offset: 0x3f8, size: 32, reset: 0x00120011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P_ID
r
Toggle fields

P_ID

Bits 0-31: P_ID.

SIDR

LPTIM registers map size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S_ID
r
Toggle fields

S_ID

Bits 0-31: S_ID.

LPTIM5

0x50024000: LPTIM1

16/52 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISR
0x4 ICR
0x8 IER
0xc CFGR
0x10 CR
0x14 CMP
0x18 ARR
0x1c CNT
0x24 CFGR2
0x3f0 LPTIM1_HWCFGR
0x3f4 VERR
0x3f8 PIDR
0x3fc SIDR
Toggle registers

ISR

LPTIM interrupt and status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN
r 		UP
r 		ARROK
r 		CMPOK
r 		EXTTRIG
r 		ARRM
r 		CMPM
r
Toggle fields

CMPM

Bit 0: CMPM.

ARRM

Bit 1: ARRM.

EXTTRIG

Bit 2: EXTTRIG.

CMPOK

Bit 3: CMPOK.

ARROK

Bit 4: ARROK.

UP

Bit 5: UP.

DOWN

Bit 6: DOWN.

ICR

LPTIM interrupt clear register

Offset: 0x4, size: 32, reset: 0x00000000, access: write-only

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNCF
w 		UPCF
w 		ARROKCF
w 		CMPOKCF
w 		EXTTRIGCF
w 		ARRMCF
w 		CMPMCF
w
Toggle fields

CMPMCF

Bit 0: CMPMCF.

ARRMCF

Bit 1: ARRMCF.

EXTTRIGCF

Bit 2: EXTTRIGCF.

CMPOKCF

Bit 3: CMPOKCF.

ARROKCF

Bit 4: ARROKCF.

UPCF

Bit 5: UPCF.

DOWNCF

Bit 6: DOWNCF.

IER

LPTIM interrupt enable register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNIE
rw 		UPIE
rw 		ARROKIE
rw 		CMPOKIE
rw 		EXTTRIGIE
rw 		ARRMIE
rw 		CMPMIE
rw
Toggle fields

CMPMIE

Bit 0: CMPMIE.

ARRMIE

Bit 1: ARRMIE.

EXTTRIGIE

Bit 2: EXTTRIGIE.

CMPOKIE

Bit 3: CMPOKIE.

ARROKIE

Bit 4: ARROKIE.

UPIE

Bit 5: UPIE.

DOWNIE

Bit 6: DOWNIE.

CFGR

LPTIM configuration register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENC
rw 		COUNTMODE
rw 		PRELOAD
rw 		WAVPOL
rw 		WAVE
rw 		TIMOUT
rw 		TRIGEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL
rw 		PRESC
rw 		TRGFLT
rw 		CKFLT
rw 		CKPOL
rw 		CKSEL
rw
Toggle fields

CKSEL

Bit 0: CKSEL.

CKPOL

Bits 1-2: CKPOL.

CKFLT

Bits 3-4: CKFLT.

TRGFLT

Bits 6-7: TRGFLT.

PRESC

Bits 9-11: PRESC.

TRIGSEL

Bits 13-15: TRIGSEL.

TRIGEN

Bits 17-18: TRIGEN.

TIMOUT

Bit 19: TIMOUT.

WAVE

Bit 20: WAVE.

WAVPOL

Bit 21: WAVPOL.

PRELOAD

Bit 22: PRELOAD.

COUNTMODE

Bit 23: COUNTMODE.

ENC

Bit 24: ENC.

CR

LPTIM control register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTARE
rw 		COUNTRST
rw 		CNTSTRT
rw 		SNGSTRT
rw 		ENABLE
rw
Toggle fields

ENABLE

Bit 0: ENABLE.

SNGSTRT

Bit 1: SNGSTRT.

CNTSTRT

Bit 2: CNTSTRT.

COUNTRST

Bit 3: COUNTRST.

RSTARE

Bit 4: RSTARE.

CMP

LPTIM compare register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP
rw
Toggle fields

CMP

Bits 0-15: CMP.

ARR

LPTIM autoreload register

Offset: 0x18, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

CNT

LPTIM counter register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
r
Toggle fields

CNT

Bits 0-15: CNT.

CFGR2

LPTIM configuration register 2

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IN2SEL
rw 		IN1SEL
rw
Toggle fields

IN1SEL

Bits 0-1: IN1SEL.

IN2SEL

Bits 4-5: IN2SEL.

LPTIM1_HWCFGR

LPTIM 1 peripheral hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00010804, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG4
r 		CFG3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-7: CFG1.

CFG2

Bits 8-15: CFG2.

CFG3

Bits 16-19: CFG3.

CFG4

Bits 24-31: CFG4.

VERR

LPTIM peripheral version identification register

Offset: 0x3f4, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

PIDR

LPTIM peripheral type identification register

Offset: 0x3f8, size: 32, reset: 0x00120011, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P_ID
r
Toggle fields

P_ID

Bits 0-31: P_ID.

SIDR

LPTIM registers map size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S_ID
r
Toggle fields

S_ID

Bits 0-31: S_ID.

LTDC

0x5a001000: LTDC

39/119 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 IDR
0x4 LCR
0x8 SSCR
0xc BPCR
0x10 AWCR
0x14 TWCR
0x18 GCR
0x1c GC1R
0x20 GC2R
0x24 SRCR
0x2c BCCR
0x34 IER
0x38 ISR
0x3c ICR
0x40 LIPCR
0x44 CPSR
0x48 CDSR
0x84 L1CR
0x88 L1WHPCR
0x8c L1WVPCR
0x90 L1CKCR
0x94 L1PFCR
0x98 L1CACR
0x9c L1DCCR
0xa0 L1BFCR
0xac L1CFBAR
0xb0 L1CFBLR
0xb4 L1CFBLNR
0xc4 L1CLUTWR
0x104 L2CR
0x108 L2WHPCR
0x10c L2WVPCR
0x110 L2CKCR
0x114 L2PFCR
0x118 L2CACR
0x11c L2DCCR
0x120 L2BFCR
0x12c L2CFBAR
0x130 L2CFBLR
0x134 L2CFBLNR
0x144 L2CLUTWR
Toggle registers

IDR

LTDC identification register

Offset: 0x0, size: 32, reset: 0x00010300, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAJVER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MINVER
r 		REV
r
Toggle fields

REV

Bits 0-7: REV.

MINVER

Bits 8-15: MINVER.

MAJVER

Bits 16-23: MAJVER.

LCR

LDTC layer count register

Offset: 0x4, size: 32, reset: 0x00000002, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LNBR
r
Toggle fields

LNBR

Bits 0-7: LNBR.

SSCR

This register defines the number of horizontal synchronization pixels minus 1 and the number of vertical synchronization lines minus 1. Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSH
rw
Toggle fields

VSH

Bits 0-11: VSH.

HSW

Bits 16-27: HSW.

BPCR

This register defines the accumulated number of horizontal synchronization and back porch pixels minus 1 (HSYNCwidth+HBP-1) and the accumulated number of vertical synchronization and back porch lines minus 1 (VSYNCheight+VBP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AVBP
rw
Toggle fields

AVBP

Bits 0-11: AVBP.

AHBP

Bits 16-27: AHBP.

AWCR

This register defines the accumulated number of horizontal synchronization, back porch and active pixels minus 1 (HSYNC width+HBP+activewidth-1) and the accumulated number of vertical synchronization, back porch lines and active lines minus 1 (VSYNCheight+BVBP+activeheight-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AAW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AAH
rw
Toggle fields

AAH

Bits 0-11: AAH.

AAW

Bits 16-27: AAW.

TWCR

This register defines the accumulated number of horizontal synchronization, back porch, active and front porch pixels minus 1 (HSYNCwidth+HBP+activewidth+HFP-1) and the accumulated number of vertical synchronization, back porch lines, active and front lines minus 1 (VSYNCheight+BVBP+activeheight+VFP-1). Refer to Figure274 and Section36.4: LTDC programmable parameters for an example of configuration.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOTALW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOTALH
rw
Toggle fields

TOTALH

Bits 0-11: TOTALH.

TOTALW

Bits 16-27: TOTALW.

GCR

This register defines the global configuration of the LCD-TFT controller.

Offset: 0x18, size: 32, reset: 0x00002220, access: Unspecified

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSPOL
rw 		VSPOL
rw 		DEPOL
rw 		PCPOL
rw 		DEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRW
r 		DGW
r 		DBW
r 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LTDCEN.

DBW

Bits 4-6: DBW.

DGW

Bits 8-10: DGW.

DRW

Bits 12-14: DRW.

DEN

Bit 16: DEN.

PCPOL

Bit 28: PCPOL.

DEPOL

Bit 29: DEPOL.

VSPOL

Bit 30: VSPOL.

HSPOL

Bit 31: HSPOL.

GC1R

LTDC global configuration 1 register

Offset: 0x1c, size: 32, reset: 0x6BE2D888, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BMEN
r 		STREN
r 		DWP
r 		SPP
r 		IPP
r 		TP
r 		LNIP
r 		BBEN
r 		BCP
r 		SHREN
r 		GCT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DT
r 		PRBEN
r 		WRCH
r 		WGCH
r 		WBCH
r
Toggle fields

WBCH

Bits 0-3: WBCH.

WGCH

Bits 4-7: WGCH.

WRCH

Bits 8-11: WRCH.

PRBEN

Bit 12: PRBEN.

DT

Bits 14-15: DT.

GCT

Bits 17-19: GCT.

SHREN

Bit 21: SHREN.

BCP

Bit 22: BCP.

BBEN

Bit 23: BBEN.

LNIP

Bit 24: LNIP.

TP

Bit 25: TP.

IPP

Bit 26: IPP.

SPP

Bit 27: SPP.

DWP

Bit 28: DWP.

STREN

Bit 29: STREN.

BMEN

Bit 31: BMEN.

GC2R

LTDC global configuration 2 register

Offset: 0x20, size: 32, reset: 0x00000030, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EDCA
r 		BW
r 		DPAEN
r 		DVAEN
r 		STSAEN
r 		EDCEN
r
Toggle fields

EDCEN

Bit 0: EDCEN.

STSAEN

Bit 1: STSAEN.

DVAEN

Bit 2: DVAEN.

DPAEN

Bit 3: DPAEN.

BW

Bits 4-6: BW.

EDCA

Bit 7: EDCA.

SRCR

This register allows to reload either immediately or during the vertical blanking period, the shadow registers values to the active registers. The shadow registers are all Layer1 and Layer2 registers except the LTDC_L1CLUTWR and the LTDC_L2CLUTWR.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBR
rw 		IMR
rw
Toggle fields

IMR

Bit 0: IMR.

VBR

Bit 1: VBR.

BCCR

This register defines the background color (RGB888).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCGREEN
rw 		BCBLUE
rw
Toggle fields

BCBLUE

Bits 0-7: BCBLUE.

BCGREEN

Bits 8-15: BCGREEN.

BCRED

Bits 16-23: BCRED.

IER

This register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIE
rw 		TERRIE
rw 		FUIE
rw 		LIE
rw
Toggle fields

LIE

Bit 0: LIE.

FUIE

Bit 1: FUIE.

TERRIE

Bit 2: TERRIE.

RRIE

Bit 3: RRIE.

ISR

This register returns the interrupt status flag.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRIF
r 		TERRIF
r 		FUIF
r 		LIF
r
Toggle fields

LIF

Bit 0: LIF.

FUIF

Bit 1: FUIF.

TERRIF

Bit 2: TERRIF.

RRIF

Bit 3: RRIF.

ICR

LTDC Interrupt Clear Register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRRIF
w 		CTERRIF
w 		CFUIF
w 		CLIF
w
Toggle fields

CLIF

Bit 0: CLIF.

CFUIF

Bit 1: CFUIF.

CTERRIF

Bit 2: CTERRIF.

CRRIF

Bit 3: CRRIF.

LIPCR

This register defines the position of the line interrupt. The line value to be programmed depends on the timings parameters. Refer to Figure274.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LIPOS
rw
Toggle fields

LIPOS

Bits 0-11: LIPOS.

CPSR

LTDC current position status register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CXPOS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYPOS
r
Toggle fields

CYPOS

Bits 0-15: CYPOS.

CXPOS

Bits 16-31: CXPOS.

CDSR

This register returns the status of the current display phase which is controlled by the HSYNC, VSYNC, and horizontal/vertical DE signals. Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set (active high). If the current display phase is the horizontal synchronization, the HSYNCS bit is active high.

Offset: 0x48, size: 32, reset: 0x0000000F, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSYNCS
r 		VSYNCS
r 		HDES
r 		VDES
r
Toggle fields

VDES

Bit 0: VDES.

HDES

Bit 1: HDES.

VSYNCS

Bit 2: VSYNCS.

HSYNCS

Bit 3: HSYNCS.

L1CR

LTDC layer 1 control register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw 		COLKEN
rw 		LEN
rw
Toggle fields

LEN

Bit 0: LEN.

COLKEN

Bit 1: COLKEN.

CLUTEN

Bit 4: CLUTEN.

L1WHPCR

This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: WHSTPOS.

WHSPPOS

Bits 16-27: WHSPPOS.

L1WVPCR

This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-11: WVSTPOS.

WVSPPOS

Bits 16-27: WVSPPOS.

L1CKCR

This register defines the color key value (RGB), that is used by the color keying.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw 		CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: CKBLUE.

CKGREEN

Bits 8-15: CKGREEN.

CKRED

Bits 16-23: CKRED.

L1PFCR

This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: PF.

L1CACR

This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.

Offset: 0x98, size: 32, reset: 0x000000FF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: CONSTA.

L1DCCR

This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw 		DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw 		DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: DCBLUE.

DCGREEN

Bits 8-15: DCGREEN.

DCRED

Bits 16-23: DCRED.

DCALPHA

Bits 24-31: DCALPHA.

L1BFCR

This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color

Offset: 0xa0, size: 32, reset: 0x00000607, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw 		BF2
rw
Toggle fields

BF2

Bits 0-2: BF2.

BF1

Bits 8-10: BF1.

L1CFBAR

This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: CFBADD.

L1CFBLR

This register defines the color frame buffer line length and pitch.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-13: CFBLL.

CFBP

Bits 16-29: CFBP.

L1CFBLNR

This register defines the number of lines in the color frame buffer.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-11: CFBLNBR.

L1CLUTWR

This register defines the CLUT address and the RGB value.

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w 		RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w 		BLUE
w
Toggle fields

BLUE

Bits 0-7: BLUE.

GREEN

Bits 8-15: GREEN.

RED

Bits 16-23: RED.

CLUTADD

Bits 24-31: CLUTADD.

L2CR

LTDC layer 2 control register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLUTEN
rw 		COLKEN
rw 		LEN
rw
Toggle fields

LEN

Bit 0: LEN.

COLKEN

Bit 1: COLKEN.

CLUTEN

Bit 4: CLUTEN.

L2WHPCR

This register defines the horizontal position (first and last pixel) of the layer 1 or 2 window. The first visible pixel of a line is the programmed value of AHBP[11:0] bits + 1 in the LTDC_BPCR register. The last visible pixel of a line is the programmed value of AAW[11:0] bits in the LTDC_AWCR register.

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WHSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WHSTPOS
rw
Toggle fields

WHSTPOS

Bits 0-11: WHSTPOS.

WHSPPOS

Bits 16-27: WHSPPOS.

L2WVPCR

This register defines the vertical position (first and last line) of the layer1 or 2 window. The first visible line of a frame is the programmed value of AVBP[11:0] bits + 1 in the register LTDC_BPCR register. The last visible line of a frame is the programmed value of AAH[11:0] bits in the LTDC_AWCR register.

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WVSPPOS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WVSTPOS
rw
Toggle fields

WVSTPOS

Bits 0-11: WVSTPOS.

WVSPPOS

Bits 16-27: WVSPPOS.

L2CKCR

This register defines the color key value (RGB), that is used by the color keying.

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKGREEN
rw 		CKBLUE
rw
Toggle fields

CKBLUE

Bits 0-7: CKBLUE.

CKGREEN

Bits 8-15: CKGREEN.

CKRED

Bits 16-23: CKRED.

L2PFCR

This register defines the pixel format that is used for the stored data in the frame buffer of a layer. The pixel data is read from the frame buffer and then transformed to the internal format 8888 (ARGB).

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF
rw
Toggle fields

PF

Bits 0-2: PF.

L2CACR

This register defines the constant alpha value (divided by 255 by hardware), that is used in the alpha blending. Refer to LTDC_LxBFCR register.

Offset: 0x118, size: 32, reset: 0x000000FF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONSTA
rw
Toggle fields

CONSTA

Bits 0-7: CONSTA.

L2DCCR

This register defines the default color of a layer in the format ARGB. The default color is used outside the defined layer window or when a layer is disabled. The reset value of 0x00000000 defines a transparent black color.

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DCALPHA
rw 		DCRED
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCGREEN
rw 		DCBLUE
rw
Toggle fields

DCBLUE

Bits 0-7: DCBLUE.

DCGREEN

Bits 8-15: DCGREEN.

DCRED

Bits 16-23: DCRED.

DCALPHA

Bits 24-31: DCALPHA.

L2BFCR

This register defines the blending factors F1 and F2. The general blending formula is: BC = BF1 x C + BF2 x Cs BC = blended color BF1 = blend factor 1 C = current layer color BF2 = blend factor 2 Cs = subjacent layers blended color

Offset: 0x120, size: 32, reset: 0x00000607, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BF1
rw 		BF2
rw
Toggle fields

BF2

Bits 0-2: BF2.

BF1

Bits 8-10: BF1.

L2CFBAR

This register defines the color frame buffer start address which has to point to the address where the pixel data of the top left pixel of a layer is stored in the frame buffer.

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBADD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBADD
rw
Toggle fields

CFBADD

Bits 0-31: CFBADD.

L2CFBLR

This register defines the color frame buffer line length and pitch.

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFBP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLL
rw
Toggle fields

CFBLL

Bits 0-13: CFBLL.

CFBP

Bits 16-29: CFBP.

L2CFBLNR

This register defines the number of lines in the color frame buffer.

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFBLNBR
rw
Toggle fields

CFBLNBR

Bits 0-11: CFBLNBR.

L2CLUTWR

This register defines the CLUT address and the RGB value.

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLUTADD
w 		RED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GREEN
w 		BLUE
w
Toggle fields

BLUE

Bits 0-7: BLUE.

GREEN

Bits 8-15: GREEN.

RED

Bits 16-23: RED.

CLUTADD

Bits 24-31: CLUTADD.

MDIOS

0x4001c000: MDIOS

74/85 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 WRFR
0x8 CWRFR
0xc RDFR
0x10 CRDFR
0x14 SR
0x18 CLRFR
0x100 DINR0
0x104 DINR1
0x108 DINR2
0x10c DINR3
0x110 DINR4
0x114 DINR5
0x118 DINR6
0x11c DINR7
0x120 DINR8
0x124 DINR9
0x128 DINR10
0x12c DINR11
0x130 DINR12
0x134 DINR13
0x138 DINR14
0x13c DINR15
0x140 DINR16
0x144 DINR17
0x148 DINR18
0x14c DINR19
0x150 DINR20
0x154 DINR21
0x158 DINR22
0x15c DINR23
0x160 DINR24
0x164 DINR25
0x168 DINR26
0x16c DINR27
0x170 DINR28
0x174 DINR29
0x178 DINR30
0x17c DINR31
0x180 DOUTR0
0x184 DOUTR1
0x188 DOUTR2
0x18c DOUTR3
0x190 DOUTR4
0x194 DOUTR5
0x198 DOUTR6
0x19c DOUTR7
0x1a0 DOUTR8
0x1a4 DOUTR9
0x1a8 DOUTR10
0x1ac DOUTR11
0x1b0 DOUTR12
0x1b4 DOUTR13
0x1b8 DOUTR14
0x1bc DOUTR15
0x1c0 DOUTR16
0x1c4 DOUTR17
0x1c8 DOUTR18
0x1cc DOUTR19
0x1d0 DOUTR20
0x1d4 DOUTR21
0x1d8 DOUTR22
0x1dc DOUTR23
0x1e0 DOUTR24
0x1e4 DOUTR25
0x1e8 DOUTR26
0x1ec DOUTR27
0x1f0 DOUTR28
0x1f4 DOUTR29
0x1f8 DOUTR30
0x1fc DOUTR31
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

MDIOS configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT_ADDRESS
rw 		DPC
rw 		EIE
rw 		RDIE
rw 		WRIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

WRIE

Bit 1: WRIE.

RDIE

Bit 2: RDIE.

EIE

Bit 3: EIE.

DPC

Bit 7: DPC.

PORT_ADDRESS

Bits 8-12: PORT_ADDRESS.

WRFR

MDIOS write flag register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRF
r
Toggle fields

WRF

Bits 0-31: WRF.

CWRFR

MDIOS clear write flag register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CWRF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CWRF
rw
Toggle fields

CWRF

Bits 0-31: CWRF.

RDFR

MDIOS read flag register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDF
r
Toggle fields

RDF

Bits 0-31: RDF.

CRDFR

MDIOS clear read flag register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRDF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRDF
rw
Toggle fields

CRDF

Bits 0-31: CRDF.

SR

MDIOS status register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERF
r 		SERF
r 		PERF
r
Toggle fields

PERF

Bit 0: PERF.

SERF

Bit 1: SERF.

TERF

Bit 2: TERF.

CLRFR

MDIOS clear flag register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTERF
rw 		CSERF
rw 		CPERF
rw
Toggle fields

CPERF

Bit 0: CPERF.

CSERF

Bit 1: CSERF.

CTERF

Bit 2: CTERF.

DINR0

MDIOS input data register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR1

MDIOS input data register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR2

MDIOS input data register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR3

MDIOS input data register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR4

MDIOS input data register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR5

MDIOS input data register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR6

MDIOS input data register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR7

MDIOS input data register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR8

MDIOS input data register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR9

MDIOS input data register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR10

MDIOS input data register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR11

MDIOS input data register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR12

MDIOS input data register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR13

MDIOS input data register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR14

MDIOS input data register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR15

MDIOS input data register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR16

MDIOS input data register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR17

MDIOS input data register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR18

MDIOS input data register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR19

MDIOS input data register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR20

MDIOS input data register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR21

MDIOS input data register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR22

MDIOS input data register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR23

MDIOS input data register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR24

MDIOS input data register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR25

MDIOS input data register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR26

MDIOS input data register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR27

MDIOS input data register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR28

MDIOS input data register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR29

MDIOS input data register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR30

MDIOS input data register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DINR31

MDIOS input data register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN
r
Toggle fields

DIN

Bits 0-15: DIN.

DOUTR0

MDIOS input data register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR1

MDIOS input data register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR2

MDIOS output data register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR3

MDIOS output data register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR4

MDIOS output data register

Offset: 0x190, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR5

MDIOS output data register

Offset: 0x194, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR6

MDIOS output data register

Offset: 0x198, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR7

MDIOS output data register

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR8

MDIOS output data register

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR9

MDIOS output data register

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR10

MDIOS output data register

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR11

MDIOS output data register

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR12

MDIOS output data register

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR13

MDIOS output data register

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR14

MDIOS output data register

Offset: 0x1b8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR15

MDIOS output data register

Offset: 0x1bc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR16

MDIOS output data register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR17

MDIOS output data register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR18

MDIOS output data register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR19

MDIOS output data register

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR20

MDIOS output data register

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR21

MDIOS output data register

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR22

MDIOS output data register

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR23

MDIOS output data register

Offset: 0x1dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR24

MDIOS output data register

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR25

MDIOS output data register

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR26

MDIOS output data register

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR27

MDIOS output data register

Offset: 0x1ec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR28

MDIOS output data register

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR29

MDIOS output data register

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR30

MDIOS output data register

Offset: 0x1f8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

DOUTR31

MDIOS output data register

Offset: 0x1fc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT
r
Toggle fields

DOUT

Bits 0-15: DOUT.

HWCFGR

MDIOS HW configuration register

Offset: 0x3f0, size: 32, reset: 0x00000020, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBREG
r
Toggle fields

NBREG

Bits 0-7: NBREG.

VERR

MDIOS version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

MDIOS identification register

Offset: 0x3f8, size: 32, reset: 0x00180001, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

MDIOS size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

MDMA

0x58000000: MDMA1

448/1856 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GISR0
0x8 SGISR0
0x40 C0ISR
0x44 C0IFCR
0x48 C0ESR
0x4c C0CR
0x50 C0TCR
0x54 C0BNDTR
0x58 C0SAR
0x5c C0DAR
0x60 C0BRUR
0x64 C0LAR
0x68 C0TBR
0x70 C0MAR
0x74 C0MDR
0x80 C1ISR
0x84 C1IFCR
0x88 C1ESR
0x8c C1CR
0x90 C1TCR
0x94 C1BNDTR
0x98 C1SAR
0x9c C1DAR
0xa0 C1BRUR
0xa4 C1LAR
0xa8 C1TBR
0xb0 C1MAR
0xb4 C1MDR
0xc0 C2ISR
0xc4 C2IFCR
0xc8 C2ESR
0xcc C2CR
0xd0 C2TCR
0xd4 C2BNDTR
0xd8 C2SAR
0xdc C2DAR
0xe0 C2BRUR
0xe4 C2LAR
0xe8 C2TBR
0xf0 C2MAR
0xf4 C2MDR
0x100 C3ISR
0x104 C3IFCR
0x108 C3ESR
0x10c C3CR
0x110 C3TCR
0x114 C3BNDTR
0x118 C3SAR
0x11c C3DAR
0x120 C3BRUR
0x124 C3LAR
0x128 C3TBR
0x130 C3MAR
0x134 C3MDR
0x140 C4ISR
0x144 C4IFCR
0x148 C4ESR
0x14c C4CR
0x150 C4TCR
0x154 C4BNDTR
0x158 C4SAR
0x15c C4DAR
0x160 C4BRUR
0x164 C4LAR
0x168 C4TBR
0x170 C4MAR
0x174 C4MDR
0x180 C5ISR
0x184 C5IFCR
0x188 C5ESR
0x18c C5CR
0x190 C5TCR
0x194 C5BNDTR
0x198 C5SAR
0x19c C5DAR
0x1a0 C5BRUR
0x1a4 C5LAR
0x1a8 C5TBR
0x1b0 C5MAR
0x1b4 C5MDR
0x1c0 C6ISR
0x1c4 C6IFCR
0x1c8 C6ESR
0x1cc C6CR
0x1d0 C6TCR
0x1d4 C6BNDTR
0x1d8 C6SAR
0x1dc C6DAR
0x1e0 C6BRUR
0x1e4 C6LAR
0x1e8 C6TBR
0x1f0 C6MAR
0x1f4 C6MDR
0x200 C7ISR
0x204 C7IFCR
0x208 C7ESR
0x20c C7CR
0x210 C7TCR
0x214 C7BNDTR
0x218 C7SAR
0x21c C7DAR
0x220 C7BRUR
0x224 C7LAR
0x228 C7TBR
0x230 C7MAR
0x234 C7MDR
0x240 C8ISR
0x244 C8IFCR
0x248 C8ESR
0x24c C8CR
0x250 C8TCR
0x254 C8BNDTR
0x258 C8SAR
0x25c C8DAR
0x260 C8BRUR
0x264 C8LAR
0x268 C8TBR
0x270 C8MAR
0x274 C8MDR
0x280 C9ISR
0x284 C9IFCR
0x288 C9ESR
0x28c C9CR
0x290 C9TCR
0x294 C9BNDTR
0x298 C9SAR
0x29c C9DAR
0x2a0 C9BRUR
0x2a4 C9LAR
0x2a8 C9TBR
0x2b0 C9MAR
0x2b4 C9MDR
0x2c0 C10ISR
0x2c4 C10IFCR
0x2c8 C10ESR
0x2cc C10CR
0x2d0 C10TCR
0x2d4 C10BNDTR
0x2d8 C10SAR
0x2dc C10DAR
0x2e0 C10BRUR
0x2e4 C10LAR
0x2e8 C10TBR
0x2f0 C10MAR
0x2f4 C10MDR
0x300 C11ISR
0x304 C11IFCR
0x308 C11ESR
0x30c C11CR
0x310 C11TCR
0x314 C11BNDTR
0x318 C11SAR
0x31c C11DAR
0x320 C11BRUR
0x324 C11LAR
0x328 C11TBR
0x330 C11MAR
0x334 C11MDR
0x340 C12ISR
0x344 C12IFCR
0x348 C12ESR
0x34c C12CR
0x350 C12TCR
0x354 C12BNDTR
0x358 C12SAR
0x35c C12DAR
0x360 C12BRUR
0x364 C12LAR
0x368 C12TBR
0x370 C12MAR
0x374 C12MDR
0x380 C13ISR
0x384 C13IFCR
0x388 C13ESR
0x38c C13CR
0x390 C13TCR
0x394 C13BNDTR
0x398 C13SAR
0x39c C13DAR
0x3a0 C13BRUR
0x3a4 C13LAR
0x3a8 C13TBR
0x3b0 C13MAR
0x3b4 C13MDR
0x3c0 C14ISR
0x3c4 C14IFCR
0x3c8 C14ESR
0x3cc C14CR
0x3d0 C14TCR
0x3d4 C14BNDTR
0x3d8 C14SAR
0x3dc C14DAR
0x3e0 C14BRUR
0x3e4 C14LAR
0x3e8 C14TBR
0x3f0 C14MAR
0x3f4 C14MDR
0x400 C15ISR
0x404 C15IFCR
0x408 C15ESR
0x40c C15CR
0x410 C15TCR
0x414 C15BNDTR
0x418 C15SAR
0x41c C15DAR
0x420 C15BRUR
0x424 C15LAR
0x428 C15TBR
0x430 C15MAR
0x434 C15MDR
0x440 C16ISR
0x444 C16IFCR
0x448 C16ESR
0x44c C16CR
0x450 C16TCR
0x454 C16BNDTR
0x458 C16SAR
0x45c C16DAR
0x460 C16BRUR
0x464 C16LAR
0x468 C16TBR
0x470 C16MAR
0x474 C16MDR
0x480 C17ISR
0x484 C17IFCR
0x488 C17ESR
0x48c C17CR
0x490 C17TCR
0x494 C17BNDTR
0x498 C17SAR
0x49c C17DAR
0x4a0 C17BRUR
0x4a4 C17LAR
0x4a8 C17TBR
0x4b0 C17MAR
0x4b4 C17MDR
0x4c0 C18ISR
0x4c4 C18IFCR
0x4c8 C18ESR
0x4cc C18CR
0x4d0 C18TCR
0x4d4 C18BNDTR
0x4d8 C18SAR
0x4dc C18DAR
0x4e0 C18BRUR
0x4e4 C18LAR
0x4e8 C18TBR
0x4f0 C18MAR
0x4f4 C18MDR
0x500 C19ISR
0x504 C19IFCR
0x508 C19ESR
0x50c C19CR
0x510 C19TCR
0x514 C19BNDTR
0x518 C19SAR
0x51c C19DAR
0x520 C19BRUR
0x524 C19LAR
0x528 C19TBR
0x530 C19MAR
0x534 C19MDR
0x540 C20ISR
0x544 C20IFCR
0x548 C20ESR
0x54c C20CR
0x550 C20TCR
0x554 C20BNDTR
0x558 C20SAR
0x55c C20DAR
0x560 C20BRUR
0x564 C20LAR
0x568 C20TBR
0x570 C20MAR
0x574 C20MDR
0x580 C21ISR
0x584 C21IFCR
0x588 C21ESR
0x58c C21CR
0x590 C21TCR
0x594 C21BNDTR
0x598 C21SAR
0x59c C21DAR
0x5a0 C21BRUR
0x5a4 C21LAR
0x5a8 C21TBR
0x5b0 C21MAR
0x5b4 C21MDR
0x5c0 C22ISR
0x5c4 C22IFCR
0x5c8 C22ESR
0x5cc C22CR
0x5d0 C22TCR
0x5d4 C22BNDTR
0x5d8 C22SAR
0x5dc C22DAR
0x5e0 C22BRUR
0x5e4 C22LAR
0x5e8 C22TBR
0x5f0 C22MAR
0x5f4 C22MDR
0x600 C23ISR
0x604 C23IFCR
0x608 C23ESR
0x60c C23CR
0x610 C23TCR
0x614 C23BNDTR
0x618 C23SAR
0x61c C23DAR
0x620 C23BRUR
0x624 C23LAR
0x628 C23TBR
0x630 C23MAR
0x634 C23MDR
0x640 C24ISR
0x644 C24IFCR
0x648 C24ESR
0x64c C24CR
0x650 C24TCR
0x654 C24BNDTR
0x658 C24SAR
0x65c C24DAR
0x660 C24BRUR
0x664 C24LAR
0x668 C24TBR
0x670 C24MAR
0x674 C24MDR
0x680 C25ISR
0x684 C25IFCR
0x688 C25ESR
0x68c C25CR
0x690 C25TCR
0x694 C25BNDTR
0x698 C25SAR
0x69c C25DAR
0x6a0 C25BRUR
0x6a4 C25LAR
0x6a8 C25TBR
0x6b0 C25MAR
0x6b4 C25MDR
0x6c0 C26ISR
0x6c4 C26IFCR
0x6c8 C26ESR
0x6cc C26CR
0x6d0 C26TCR
0x6d4 C26BNDTR
0x6d8 C26SAR
0x6dc C26DAR
0x6e0 C26BRUR
0x6e4 C26LAR
0x6e8 C26TBR
0x6f0 C26MAR
0x6f4 C26MDR
0x700 C27ISR
0x704 C27IFCR
0x708 C27ESR
0x70c C27CR
0x710 C27TCR
0x714 C27BNDTR
0x718 C27SAR
0x71c C27DAR
0x720 C27BRUR
0x724 C27LAR
0x728 C27TBR
0x730 C27MAR
0x734 C27MDR
0x740 C28ISR
0x744 C28IFCR
0x748 C28ESR
0x74c C28CR
0x750 C28TCR
0x754 C28BNDTR
0x758 C28SAR
0x75c C28DAR
0x760 C28BRUR
0x764 C28LAR
0x768 C28TBR
0x770 C28MAR
0x774 C28MDR
0x780 C29ISR
0x784 C29IFCR
0x788 C29ESR
0x78c C29CR
0x790 C29TCR
0x794 C29BNDTR
0x798 C29SAR
0x79c C29DAR
0x7a0 C29BRUR
0x7a4 C29LAR
0x7a8 C29TBR
0x7b0 C29MAR
0x7b4 C29MDR
0x7c0 C30ISR
0x7c4 C30IFCR
0x7c8 C30ESR
0x7cc C30CR
0x7d0 C30TCR
0x7d4 C30BNDTR
0x7d8 C30SAR
0x7dc C30DAR
0x7e0 C30BRUR
0x7e4 C30LAR
0x7e8 C30TBR
0x7f0 C30MAR
0x7f4 C30MDR
0x800 C31ISR
0x804 C31IFCR
0x808 C31ESR
0x80c C31CR
0x810 C31TCR
0x814 C31BNDTR
0x818 C31SAR
0x81c C31DAR
0x820 C31BRUR
0x824 C31LAR
0x828 C31TBR
0x830 C31MAR
0x834 C31MDR
Toggle registers

GISR0

MDMA global interrupt/status register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GIF31
r 		GIF30
r 		GIF29
r 		GIF28
r 		GIF27
r 		GIF26
r 		GIF25
r 		GIF24
r 		GIF23
r 		GIF22
r 		GIF21
r 		GIF20
r 		GIF19
r 		GIF18
r 		GIF17
r 		GIF16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GIF15
r 		GIF14
r 		GIF13
r 		GIF12
r 		GIF11
r 		GIF10
r 		GIF9
r 		GIF8
r 		GIF7
r 		GIF6
r 		GIF5
r 		GIF4
r 		GIF3
r 		GIF2
r 		GIF1
r 		GIF0
r
Toggle fields

GIF0

Bit 0: GIF0.

GIF1

Bit 1: GIF1.

GIF2

Bit 2: GIF2.

GIF3

Bit 3: GIF3.

GIF4

Bit 4: GIF4.

GIF5

Bit 5: GIF5.

GIF6

Bit 6: GIF6.

GIF7

Bit 7: GIF7.

GIF8

Bit 8: GIF8.

GIF9

Bit 9: GIF9.

GIF10

Bit 10: GIF10.

GIF11

Bit 11: GIF11.

GIF12

Bit 12: GIF12.

GIF13

Bit 13: GIF13.

GIF14

Bit 14: GIF14.

GIF15

Bit 15: GIF15.

GIF16

Bit 16: GIF16.

GIF17

Bit 17: GIF17.

GIF18

Bit 18: GIF18.

GIF19

Bit 19: GIF19.

GIF20

Bit 20: GIF20.

GIF21

Bit 21: GIF21.

GIF22

Bit 22: GIF22.

GIF23

Bit 23: GIF23.

GIF24

Bit 24: GIF24.

GIF25

Bit 25: GIF25.

GIF26

Bit 26: GIF26.

GIF27

Bit 27: GIF27.

GIF28

Bit 28: GIF28.

GIF29

Bit 29: GIF29.

GIF30

Bit 30: GIF30.

GIF31

Bit 31: GIF31.

SGISR0

MDMA secure global interrupt/status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

32/32 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GIF31
r 		GIF30
r 		GIF29
r 		GIF28
r 		GIF27
r 		GIF26
r 		GIF25
r 		GIF24
r 		GIF23
r 		GIF22
r 		GIF21
r 		GIF20
r 		GIF19
r 		GIF18
r 		GIF17
r 		GIF16
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GIF15
r 		GIF14
r 		GIF13
r 		GIF12
r 		GIF11
r 		GIF10
r 		GIF9
r 		GIF8
r 		GIF7
r 		GIF6
r 		GIF5
r 		GIF4
r 		GIF3
r 		GIF2
r 		GIF1
r 		GIF0
r
Toggle fields

GIF0

Bit 0: GIF0.

GIF1

Bit 1: GIF1.

GIF2

Bit 2: GIF2.

GIF3

Bit 3: GIF3.

GIF4

Bit 4: GIF4.

GIF5

Bit 5: GIF5.

GIF6

Bit 6: GIF6.

GIF7

Bit 7: GIF7.

GIF8

Bit 8: GIF8.

GIF9

Bit 9: GIF9.

GIF10

Bit 10: GIF10.

GIF11

Bit 11: GIF11.

GIF12

Bit 12: GIF12.

GIF13

Bit 13: GIF13.

GIF14

Bit 14: GIF14.

GIF15

Bit 15: GIF15.

GIF16

Bit 16: GIF16.

GIF17

Bit 17: GIF17.

GIF18

Bit 18: GIF18.

GIF19

Bit 19: GIF19.

GIF20

Bit 20: GIF20.

GIF21

Bit 21: GIF21.

GIF22

Bit 22: GIF22.

GIF23

Bit 23: GIF23.

GIF24

Bit 24: GIF24.

GIF25

Bit 25: GIF25.

GIF26

Bit 26: GIF26.

GIF27

Bit 27: GIF27.

GIF28

Bit 28: GIF28.

GIF29

Bit 29: GIF29.

GIF30

Bit 30: GIF30.

GIF31

Bit 31: GIF31.

C0ISR

MDMA channel 0 interrupt/status register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C0IFCR

MDMA channel 0 interrupt flag clear register

Offset: 0x44, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C0ESR

MDMA channel 0 error status register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C0CR

This register is used to control the concerned channel.

Offset: 0x4c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C0TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C0BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C0SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C0DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x5c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C0BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C0LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C0TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C0MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x70, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C0MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C1ISR

MDMA channel 1 interrupt/status register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C1IFCR

MDMA channel 1 interrupt flag clear register

Offset: 0x84, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C1ESR

MDMA channel 1 error status register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C1CR

This register is used to control the concerned channel.

Offset: 0x8c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C1TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C1BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C1SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C1DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C1BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C1LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C1TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C1MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C1MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C2ISR

MDMA channel 2 interrupt/status register

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C2IFCR

MDMA channel 2 interrupt flag clear register

Offset: 0xc4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C2ESR

MDMA channel 2 error status register

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C2CR

This register is used to control the concerned channel.

Offset: 0xcc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C2TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C2BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C2SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0xd8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C2DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0xdc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C2BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0xe0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C2LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0xe4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C2TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0xe8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C2MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0xf0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C2MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0xf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C3ISR

MDMA channel 3 interrupt/status register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C3IFCR

MDMA channel 3 interrupt flag clear register

Offset: 0x104, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C3ESR

MDMA channel 3 error status register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C3CR

This register is used to control the concerned channel.

Offset: 0x10c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C3TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C3BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C3SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C3DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C3BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C3LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C3TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C3MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C3MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C4ISR

MDMA channel 4 interrupt/status register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C4IFCR

MDMA channel 4 interrupt flag clear register

Offset: 0x144, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C4ESR

MDMA channel 4 error status register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C4CR

This register is used to control the concerned channel.

Offset: 0x14c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C4TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C4BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C4SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C4DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C4BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C4LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C4TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C4MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C4MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C5ISR

MDMA channel 5 interrupt/status register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C5IFCR

MDMA channel 5 interrupt flag clear register

Offset: 0x184, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C5ESR

MDMA channel 5 error status register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C5CR

This register is used to control the concerned channel.

Offset: 0x18c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C5TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C5BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C5SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C5DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C5BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C5LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C5TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x1a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C5MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C5MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C6ISR

MDMA channel 6 interrupt/status register

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C6IFCR

MDMA channel 6 interrupt flag clear register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C6ESR

MDMA channel 6 error status register

Offset: 0x1c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C6CR

This register is used to control the concerned channel.

Offset: 0x1cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C6TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C6BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C6SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x1d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C6DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x1dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C6BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x1e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C6LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x1e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C6TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x1e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C6MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C6MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x1f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C7ISR

MDMA channel 7 interrupt/status register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C7IFCR

MDMA channel 7 interrupt flag clear register

Offset: 0x204, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C7ESR

MDMA channel 7 error status register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C7CR

This register is used to control the concerned channel.

Offset: 0x20c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C7TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C7BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x214, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C7SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C7DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C7BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C7LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C7TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x228, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C7MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x230, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C7MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x234, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C8ISR

MDMA channel 8 interrupt/status register

Offset: 0x240, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C8IFCR

MDMA channel 8 interrupt flag clear register

Offset: 0x244, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C8ESR

MDMA channel 8 error status register

Offset: 0x248, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C8CR

This register is used to control the concerned channel.

Offset: 0x24c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C8TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x250, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C8BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x254, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C8SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x258, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C8DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x25c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C8BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x260, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C8LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x264, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C8TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x268, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C8MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x270, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C8MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x274, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C9ISR

MDMA channel 9 interrupt/status register

Offset: 0x280, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C9IFCR

MDMA channel 9 interrupt flag clear register

Offset: 0x284, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C9ESR

MDMA channel 9 error status register

Offset: 0x288, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C9CR

This register is used to control the concerned channel.

Offset: 0x28c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C9TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C9BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C9SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C9DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C9BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x2a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C9LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x2a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C9TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x2a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C9MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x2b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C9MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x2b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C10ISR

MDMA channel 10 interrupt/status register

Offset: 0x2c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C10IFCR

MDMA channel 10 interrupt flag clear register

Offset: 0x2c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C10ESR

MDMA channel 10 error status register

Offset: 0x2c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C10CR

This register is used to control the concerned channel.

Offset: 0x2cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C10TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x2d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C10BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x2d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C10SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x2d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C10DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x2dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C10BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C10LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C10TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x2e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C10MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x2f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C10MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C11ISR

MDMA channel 11 interrupt/status register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C11IFCR

MDMA channel 11 interrupt flag clear register

Offset: 0x304, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C11ESR

MDMA channel 11 error status register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C11CR

This register is used to control the concerned channel.

Offset: 0x30c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C11TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C11BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C11SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C11DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C11BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C11LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C11TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C11MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C11MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C12ISR

MDMA channel 12 interrupt/status register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C12IFCR

MDMA channel 12 interrupt flag clear register

Offset: 0x344, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C12ESR

MDMA channel 12 error status register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C12CR

This register is used to control the concerned channel.

Offset: 0x34c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C12TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C12BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C12SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x358, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C12DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x35c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C12BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x360, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C12LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C12TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C12MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C12MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C13ISR

MDMA channel 13 interrupt/status register

Offset: 0x380, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C13IFCR

MDMA channel 13 interrupt flag clear register

Offset: 0x384, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C13ESR

MDMA channel 13 error status register

Offset: 0x388, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C13CR

This register is used to control the concerned channel.

Offset: 0x38c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C13TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C13BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C13SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C13DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x39c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C13BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x3a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C13LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x3a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C13TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x3a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C13MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x3b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C13MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x3b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C14ISR

MDMA channel 14 interrupt/status register

Offset: 0x3c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C14IFCR

MDMA channel 14 interrupt flag clear register

Offset: 0x3c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C14ESR

MDMA channel 14 error status register

Offset: 0x3c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C14CR

This register is used to control the concerned channel.

Offset: 0x3cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C14TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x3d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C14BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x3d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C14SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x3d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C14DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x3dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C14BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x3e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C14LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x3e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C14TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x3e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C14MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C14MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x3f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C15ISR

MDMA channel 15 interrupt/status register

Offset: 0x400, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C15IFCR

MDMA channel 15 interrupt flag clear register

Offset: 0x404, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C15ESR

MDMA channel 15 error status register

Offset: 0x408, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C15CR

This register is used to control the concerned channel.

Offset: 0x40c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C15TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C15BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C15SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C15DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C15BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C15LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x424, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C15TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x428, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C15MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x430, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C15MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x434, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C16ISR

MDMA channel 16 interrupt/status register

Offset: 0x440, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C16IFCR

MDMA channel 16 interrupt flag clear register

Offset: 0x444, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C16ESR

MDMA channel 16 error status register

Offset: 0x448, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C16CR

This register is used to control the concerned channel.

Offset: 0x44c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C16TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x450, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C16BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x454, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C16SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x458, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C16DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x45c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C16BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x460, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C16LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x464, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C16TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x468, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C16MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x470, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C16MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x474, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C17ISR

MDMA channel 17 interrupt/status register

Offset: 0x480, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C17IFCR

MDMA channel 17 interrupt flag clear register

Offset: 0x484, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C17ESR

MDMA channel 17 error status register

Offset: 0x488, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C17CR

This register is used to control the concerned channel.

Offset: 0x48c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C17TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x490, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C17BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x494, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C17SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x498, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C17DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x49c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C17BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x4a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C17LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x4a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C17TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x4a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C17MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x4b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C17MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x4b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C18ISR

MDMA channel 18 interrupt/status register

Offset: 0x4c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C18IFCR

MDMA channel 18 interrupt flag clear register

Offset: 0x4c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C18ESR

MDMA channel 18 error status register

Offset: 0x4c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C18CR

This register is used to control the concerned channel.

Offset: 0x4cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C18TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x4d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C18BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x4d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C18SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x4d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C18DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x4dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C18BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x4e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C18LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x4e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C18TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x4e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C18MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x4f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C18MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x4f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C19ISR

MDMA channel 19 interrupt/status register

Offset: 0x500, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C19IFCR

MDMA channel 19 interrupt flag clear register

Offset: 0x504, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C19ESR

MDMA channel 19 error status register

Offset: 0x508, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C19CR

This register is used to control the concerned channel.

Offset: 0x50c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C19TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x510, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C19BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x514, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C19SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x518, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C19DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x51c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C19BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x520, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C19LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x524, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C19TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x528, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C19MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x530, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C19MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x534, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C20ISR

MDMA channel 20 interrupt/status register

Offset: 0x540, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C20IFCR

MDMA channel 20 interrupt flag clear register

Offset: 0x544, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C20ESR

MDMA channel 20 error status register

Offset: 0x548, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C20CR

This register is used to control the concerned channel.

Offset: 0x54c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C20TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x550, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C20BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x554, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C20SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x558, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C20DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x55c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C20BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x560, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C20LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x564, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C20TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x568, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C20MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x570, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C20MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x574, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C21ISR

MDMA channel 21 interrupt/status register

Offset: 0x580, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C21IFCR

MDMA channel 21 interrupt flag clear register

Offset: 0x584, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C21ESR

MDMA channel 21 error status register

Offset: 0x588, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C21CR

This register is used to control the concerned channel.

Offset: 0x58c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C21TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x590, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C21BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x594, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C21SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x598, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C21DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x59c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C21BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x5a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C21LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x5a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C21TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x5a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C21MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x5b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C21MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x5b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C22ISR

MDMA channel 22 interrupt/status register

Offset: 0x5c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C22IFCR

MDMA channel 22 interrupt flag clear register

Offset: 0x5c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C22ESR

MDMA channel 22 error status register

Offset: 0x5c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C22CR

This register is used to control the concerned channel.

Offset: 0x5cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C22TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x5d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C22BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x5d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C22SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x5d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C22DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x5dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C22BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x5e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C22LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x5e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C22TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x5e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C22MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x5f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C22MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x5f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C23ISR

MDMA channel 23 interrupt/status register

Offset: 0x600, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C23IFCR

MDMA channel 23 interrupt flag clear register

Offset: 0x604, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C23ESR

MDMA channel 23 error status register

Offset: 0x608, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C23CR

This register is used to control the concerned channel.

Offset: 0x60c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C23TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x610, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C23BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x614, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C23SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x618, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C23DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x61c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C23BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x620, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C23LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x624, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C23TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x628, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C23MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x630, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C23MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x634, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C24ISR

MDMA channel 24 interrupt/status register

Offset: 0x640, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C24IFCR

MDMA channel 24 interrupt flag clear register

Offset: 0x644, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C24ESR

MDMA channel 24 error status register

Offset: 0x648, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C24CR

This register is used to control the concerned channel.

Offset: 0x64c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C24TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x650, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C24BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x654, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C24SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x658, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C24DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x65c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C24BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x660, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C24LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x664, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C24TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x668, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C24MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x670, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C24MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x674, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C25ISR

MDMA channel 25 interrupt/status register

Offset: 0x680, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C25IFCR

MDMA channel 25 interrupt flag clear register

Offset: 0x684, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C25ESR

MDMA channel 25 error status register

Offset: 0x688, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C25CR

This register is used to control the concerned channel.

Offset: 0x68c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C25TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x690, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C25BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x694, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C25SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x698, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C25DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x69c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C25BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x6a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C25LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x6a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C25TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x6a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C25MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x6b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C25MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x6b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C26ISR

MDMA channel 26 interrupt/status register

Offset: 0x6c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C26IFCR

MDMA channel 26 interrupt flag clear register

Offset: 0x6c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C26ESR

MDMA channel 26 error status register

Offset: 0x6c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C26CR

This register is used to control the concerned channel.

Offset: 0x6cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C26TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x6d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C26BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x6d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C26SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x6d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C26DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x6dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C26BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x6e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C26LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x6e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C26TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x6e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C26MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x6f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C26MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x6f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C27ISR

MDMA channel 27 interrupt/status register

Offset: 0x700, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C27IFCR

MDMA channel 27 interrupt flag clear register

Offset: 0x704, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C27ESR

MDMA channel 27 error status register

Offset: 0x708, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C27CR

This register is used to control the concerned channel.

Offset: 0x70c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C27TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x710, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C27BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x714, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C27SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x718, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C27DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x71c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C27BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x720, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C27LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x724, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C27TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x728, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C27MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x730, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C27MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x734, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C28ISR

MDMA channel 28 interrupt/status register

Offset: 0x740, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C28IFCR

MDMA channel 28 interrupt flag clear register

Offset: 0x744, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C28ESR

MDMA channel 28 error status register

Offset: 0x748, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C28CR

This register is used to control the concerned channel.

Offset: 0x74c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C28TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x750, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C28BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x754, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C28SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x758, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C28DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x75c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C28BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x760, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C28LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x764, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C28TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x768, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C28MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x770, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C28MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x774, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C29ISR

MDMA channel 29 interrupt/status register

Offset: 0x780, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C29IFCR

MDMA channel 29 interrupt flag clear register

Offset: 0x784, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C29ESR

MDMA channel 29 error status register

Offset: 0x788, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C29CR

This register is used to control the concerned channel.

Offset: 0x78c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C29TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x790, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C29BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x794, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C29SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x798, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C29DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x79c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C29BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x7a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C29LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x7a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C29TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x7a8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C29MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x7b0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C29MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x7b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C30ISR

MDMA channel 30 interrupt/status register

Offset: 0x7c0, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C30IFCR

MDMA channel 30 interrupt flag clear register

Offset: 0x7c4, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C30ESR

MDMA channel 30 error status register

Offset: 0x7c8, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C30CR

This register is used to control the concerned channel.

Offset: 0x7cc, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C30TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x7d0, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C30BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x7d4, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C30SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x7d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C30DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x7dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C30BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x7e0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C30LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x7e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C30TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x7e8, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C30MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x7f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C30MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x7f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

C31ISR

MDMA channel 31 interrupt/status register

Offset: 0x800, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRQA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCIF
r 		BTIF
r 		BRTIF
r 		CTCIF
r 		TEIF
r
Toggle fields

TEIF

Bit 0: TEIF.

CTCIF

Bit 1: CTCIF.

BRTIF

Bit 2: BRTIF.

BTIF

Bit 3: BTIF.

TCIF

Bit 4: TCIF.

CRQA

Bit 16: CRQA.

C31IFCR

MDMA channel 31 interrupt flag clear register

Offset: 0x804, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLTCIF
w 		CBTIF
w 		CBRTIF
w 		CCTCIF
w 		CTEIF
w
Toggle fields

CTEIF

Bit 0: CTEIF.

CCTCIF

Bit 1: CCTCIF.

CBRTIF

Bit 2: CBRTIF.

CBTIF

Bit 3: CBTIF.

CLTCIF

Bit 4: CLTCIF.

C31ESR

MDMA channel 31 error status register

Offset: 0x808, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSE
r 		ASE
r 		TEMD
r 		TELD
r 		TED
r 		TEA
r
Toggle fields

TEA

Bits 0-6: TEA.

TED

Bit 7: TED.

TELD

Bit 8: TELD.

TEMD

Bit 9: TEMD.

ASE

Bit 10: ASE.

BSE

Bit 11: BSE.

C31CR

This register is used to control the concerned channel.

Offset: 0x80c, size: 32, reset: 0x00000000, access: Unspecified

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRQ
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WEX
rw 		HEX
rw 		BEX
rw 		PL
rw 		TCIE
rw 		BTIE
rw 		BRTIE
rw 		CTCIE
rw 		TEIE
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

TEIE

Bit 1: TEIE.

CTCIE

Bit 2: CTCIE.

BRTIE

Bit 3: BRTIE.

BTIE

Bit 4: BTIE.

TCIE

Bit 5: TCIE.

PL

Bits 6-7: PL.

BEX

Bit 12: BEX.

HEX

Bit 13: HEX.

WEX

Bit 14: WEX.

SWRQ

Bit 16: SWRQ.

C31TCR

This register is used to configure the concerned channel. In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00).

Offset: 0x810, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BWM
rw 		SWRM
rw 		TRGM
rw 		PAM
rw 		PKE
rw 		TLEN
rw 		DBURST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBURST
rw 		SBURST
rw 		DINCOS
rw 		SINCOS
rw 		DSIZE
rw 		SSIZE
rw 		DINC
rw 		SINC
rw
Toggle fields

SINC

Bits 0-1: SINC.

DINC

Bits 2-3: DINC.

SSIZE

Bits 4-5: SSIZE.

DSIZE

Bits 6-7: DSIZE.

SINCOS

Bits 8-9: SINCOS.

DINCOS

Bits 10-11: DINCOS.

SBURST

Bits 12-14: SBURST.

DBURST

Bits 15-17: DBURST.

TLEN

Bits 18-24: TLEN.

PKE

Bit 25: PKE.

PAM

Bits 26-27: PAM.

TRGM

Bits 28-29: TRGM.

SWRM

Bit 30: SWRM.

BWM

Bit 31: BWM.

C31BNDTR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x04).

Offset: 0x814, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BRC
rw 		BRDUM
rw 		BRSUM
rw 		BNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BNDT
rw
Toggle fields

BNDT

Bits 0-16: BNDT.

BRSUM

Bit 18: BRSUM.

BRDUM

Bit 19: BRDUM.

BRC

Bits 20-31: BRC.

C31SAR

In Linked List mode, at the end of a Block (single or last Block in repeated Block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x08).

Offset: 0x818, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAR
rw
Toggle fields

SAR

Bits 0-31: SAR.

C31DAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x0C). M

Offset: 0x81c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAR
rw
Toggle fields

DAR

Bits 0-31: DAR.

C31BRUR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x10).

Offset: 0x820, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DUV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUV
rw
Toggle fields

SUV

Bits 0-15: SUV.

DUV

Bits 16-31: DUV.

C31LAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x14). The new value is only taken into account after all registers are updated, for the next end of block.

Offset: 0x824, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR
rw
Toggle fields

LAR

Bits 0-31: LAR.

C31TBR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x18).

Offset: 0x828, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBUS
rw 		SBUS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSEL
rw
Toggle fields

TSEL

Bits 0-5: TSEL.

SBUS

Bit 16: SBUS.

DBUS

Bit 17: DBUS.

C31MAR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x20).

Offset: 0x830, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR
rw
Toggle fields

MAR

Bits 0-31: MAR.

C31MDR

In Linked List mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x24).

Offset: 0x834, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDR
rw
Toggle fields

MDR

Bits 0-31: MDR.

NVIC

0xe000e100: Nested Vectored Interrupt Controller

4/176 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 ISER0
0x4 ISER1
0x8 ISER2
0xc ISER3
0x10 ISER4
0x80 ICER0
0x84 ICER1
0x88 ICER2
0x8c ICER3
0x90 ICER4
0x100 ISPR0
0x104 ISPR1
0x108 ISPR2
0x10c ISPR3
0x110 ISPR4
0x180 ICPR0
0x184 ICPR1
0x188 ICPR2
0x18c ICPR3
0x1c4 ICPR4
0x200 IABR0
0x204 IABR1
0x208 IABR2
0x20c IABR3
0x210 IABR4
0x300 IPR0
0x304 IPR1
0x308 IPR2
0x30c IPR3
0x310 IPR4
0x314 IPR5
0x318 IPR6
0x31c IPR7
0x320 IPR8
0x324 IPR9
0x328 IPR10
0x32c IPR11
0x330 IPR12
0x334 IPR13
0x338 IPR14
0x33c IPR15
0x340 IPR16
0x344 IPR17
0x348 IPR18
0x34c IPR19
0x350 IPR20
0x354 IPR21
0x358 IPR22
0x35c IPR23
0x360 IPR24
0x364 IPR25
0x368 IPR26
0x36c IPR27
0x370 IPR28
0x374 IPR29
0x378 IPR30
0x37c IPR31
0x380 IPR32
0x384 IPR33
0x388 IPR34
0x38c IPR35
0x390 IPR36
0x394 IPR37
0x398 IPR38
Toggle registers

ISER0

Interrupt Set-Enable Register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER2

Interrupt Set-Enable Register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER3

Interrupt Set-Enable Register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETENA
rw
Toggle fields

SETENA

Bits 0-31: SETENA.

ISER4

Interrupt Set-Enable Register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

Toggle fields

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER2

Interrupt Clear-Enable Register

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER3

Interrupt Clear-Enable Register

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRENA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRENA
rw
Toggle fields

CLRENA

Bits 0-31: CLRENA.

ICER4

Interrupt Clear-Enable Register

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

Toggle fields

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR2

Interrupt Set-Pending Register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR3

Interrupt Set-Pending Register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SETPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SETPEND
rw
Toggle fields

SETPEND

Bits 0-31: SETPEND.

ISPR4

Interrupt Set-Pending Register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

Toggle fields

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR2

Interrupt Clear-Pending Register

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR3

Interrupt Clear-Pending Register

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLRPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRPEND
rw
Toggle fields

CLRPEND

Bits 0-31: CLRPEND.

ICPR4

Interrupt Clear-Pending Register

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IABR0

Interrupt Active Bit Register

Offset: 0x200, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR2

Interrupt Active Bit Register

Offset: 0x208, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR3

Interrupt Active Bit Register

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE
r
Toggle fields

ACTIVE

Bits 0-31: ACTIVE.

IABR4

Interrupt Active Bit Register

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

Toggle fields

IPR0

Interrupt Priority Register

Offset: 0x300, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR18

Interrupt Priority Register

Offset: 0x348, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR19

Interrupt Priority Register

Offset: 0x34c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR20

Interrupt Priority Register

Offset: 0x350, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR21

Interrupt Priority Register

Offset: 0x354, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR22

Interrupt Priority Register

Offset: 0x358, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR23

Interrupt Priority Register

Offset: 0x35c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR24

Interrupt Priority Register

Offset: 0x360, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR25

Interrupt Priority Register

Offset: 0x364, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR26

Interrupt Priority Register

Offset: 0x368, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR27

Interrupt Priority Register

Offset: 0x36c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR28

Interrupt Priority Register

Offset: 0x370, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR29

Interrupt Priority Register

Offset: 0x374, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR30

Interrupt Priority Register

Offset: 0x378, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR31

Interrupt Priority Register

Offset: 0x37c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR32

Interrupt Priority Register

Offset: 0x380, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR33

Interrupt Priority Register

Offset: 0x384, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR34

Interrupt Priority Register

Offset: 0x388, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR35

Interrupt Priority Register

Offset: 0x38c, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR36

Interrupt Priority Register

Offset: 0x390, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR37

Interrupt Priority Register

Offset: 0x394, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR38

Interrupt Priority Register

Offset: 0x398, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPR_N3
rw 		IPR_N2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPR_N1
rw 		IPR_N0
rw
Toggle fields

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

OTG

0x49000000: OTG

150/1549 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GOTGCTL
0x4 GOTGINT
0x8 GAHBCFG
0xc GUSBCFG
0x10 GRSTCTL
0x14 GINTSTS
0x18 GINTMSK
0x1c GRXSTSR
0x20 GRXSTSP
0x24 GRXFSIZ
0x28 HNPTXFSIZ
0x2c HNPTXSTS
0x38 GCCFG
0x3c CID
0x54 GLPMCFG
0x100 HPTXFSIZ
0x104 DIEPTXF1
0x108 DIEPTXF2
0x10c DIEPTXF3
0x110 DIEPTXF4
0x114 DIEPTXF5
0x118 DIEPTXF6
0x11c DIEPTXF7
0x120 DIEPTXF8
0x400 HCFG
0x404 HFIR
0x408 HFNUM
0x410 HPTXSTS
0x414 HAINT
0x418 HAINTMSK
0x41c HFLBADDR
0x440 HPRT
0x500 HCCHAR0
0x504 HCSPLT0
0x508 HCINT0
0x50c HCINTMSK0
0x510 HCTSIZ0
0x514 HCDMA0
0x51c HCDMAB0
0x520 HCCHAR1
0x524 HCSPLT1
0x528 HCINT1
0x52c HCINTMSK1
0x530 HCTSIZ1
0x534 HCDMA1
0x53c HCDMAB1
0x540 HCCHAR2
0x544 HCSPLT2
0x548 HCINT2
0x54c HCINTMSK2
0x550 HCTSIZ2
0x554 HCDMA2
0x55c HCDMAB2
0x560 HCCHAR3
0x564 HCSPLT3
0x568 HCINT3
0x56c HCINTMSK3
0x570 HCTSIZ3
0x574 HCDMA3
0x57c HCDMAB3
0x580 HCCHAR4
0x584 HCSPLT4
0x588 HCINT4
0x58c HCINTMSK4
0x590 HCTSIZ4
0x594 HCDMA4
0x59c HCDMAB4
0x5a0 HCCHAR5
0x5a4 HCSPLT5
0x5a8 HCINT5
0x5ac HCINTMSK5
0x5b0 HCTSIZ5
0x5b4 HCDMA5
0x5bc HCDMAB5
0x5c0 HCCHAR6
0x5c4 HCSPLT6
0x5c8 HCINT6
0x5cc HCINTMSK6
0x5d0 HCTSIZ6
0x5d4 HCDMA6
0x5dc HCDMAB6
0x5e0 HCCHAR7
0x5e4 HCSPLT7
0x5e8 HCINT7
0x5ec HCINTMSK7
0x5f0 HCTSIZ7
0x5f4 HCDMA7
0x5fc HCDMAB7
0x600 HCCHAR8
0x604 HCSPLT8
0x608 HCINT8
0x60c HCINTMSK8
0x610 HCTSIZ8
0x614 HCDMA8
0x61c HCDMAB8
0x620 HCCHAR9
0x624 HCSPLT9
0x628 HCINT9
0x62c HCINTMSK9
0x630 HCTSIZ9
0x634 HCDMA9
0x63c HCDMAB9
0x640 HCCHAR10
0x644 HCSPLT10
0x648 HCINT10
0x64c HCINTMSK10
0x650 HCTSIZ10
0x654 HCDMA10
0x65c HCDMAB10
0x660 HCCHAR11
0x664 HCSPLT11
0x668 HCINT11
0x66c HCINTMSK11
0x670 HCTSIZ11
0x674 HCDMA11
0x67c HCDMAB11
0x680 HCCHAR12
0x684 HCSPLT12
0x688 HCINT12
0x68c HCINTMSK12
0x690 HCTSIZ12
0x694 HCDMA12
0x69c HCDMAB12
0x6a0 HCCHAR13
0x6a4 HCSPLT13
0x6a8 HCINT13
0x6ac HCINTMSK13
0x6b0 HCTSIZ13
0x6b4 HCDMA13
0x6bc HCDMAB13
0x6c0 HCCHAR14
0x6c4 HCSPLT14
0x6c8 HCINT14
0x6cc HCINTMSK14
0x6d0 HCTSIZ14
0x6d4 HCDMA14
0x6dc HCDMAB14
0x6e0 HCCHAR15
0x6e4 HCSPLT15
0x6e8 HCINT15
0x6ec HCINTMSK15
0x6f0 HCTSIZ15
0x6f4 HCDMA15
0x6fc HCDMAB15
0x800 DCFG
0x804 DCTL
0x808 DSTS
0x810 DIEPMSK
0x814 DOEPMSK
0x818 DAINT
0x81c DAINTMSK
0x828 DVBUSDIS
0x82c DVBUSPULSE
0x830 DTHRCTL
0x834 DIEPEMPMSK
0x838 DEACHINT
0x83c DEACHINTMSK
0x844 HS_DIEPEACHMSK1
0x884 HS_DOEPEACHMSK1
0x900 DIEPCTL0
0x908 DIEPINT0
0x910 DIEPTSIZ0
0x914 DIEPDMA0
0x918 DTXFSTS0
0x920 DIEPCTL1
0x928 DIEPINT1
0x930 DIEPTSIZ1
0x934 DIEPDMA1
0x938 DTXFSTS1
0x940 DIEPCTL2
0x948 DIEPINT2
0x950 DIEPTSIZ2
0x954 DIEPDMA2
0x958 DTXFSTS2
0x960 DIEPCTL3
0x968 DIEPINT3
0x970 DIEPTSIZ3
0x974 DIEPDMA3
0x978 DTXFSTS3
0x980 DIEPCTL4
0x988 DIEPINT4
0x990 DIEPTSIZ4
0x994 DIEPDMA4
0x998 DTXFSTS4
0x9a0 DIEPCTL5
0x9a8 DIEPINT5
0x9b0 DIEPTSIZ5
0x9b4 DIEPDMA5
0x9b8 DTXFSTS5
0x9c0 DIEPCTL6
0x9c8 DIEPINT6
0x9d0 DIEPTSIZ6
0x9d4 DIEPDMA6
0x9d8 DTXFSTS6
0x9e0 DIEPCTL7
0x9e8 DIEPINT7
0x9f0 DIEPTSIZ7
0x9f4 DIEPDMA7
0x9f8 DTXFSTS7
0xa00 DIEPCTL8
0xa08 DIEPINT8
0xa10 DIEPTSIZ8
0xa14 DIEPDMA8
0xa18 DTXFSTS8
0xb00 DOEPCTL0
0xb08 DOEPINT0
0xb10 DOEPTSIZ0
0xb14 DOEPDMA0
0xb20 DOEPCTL1
0xb28 DOEPINT1
0xb30 DOEPTSIZ1
0xb34 DOEPDMA1
0xb40 DOEPCTL2
0xb48 DOEPINT2
0xb50 DOEPTSIZ2
0xb54 DOEPDMA2
0xb60 DOEPCTL3
0xb68 DOEPINT3
0xb70 DOEPTSIZ3
0xb74 DOEPDMA3
0xb80 DOEPCTL4
0xb88 DOEPINT4
0xb90 DOEPTSIZ4
0xb94 DOEPDMA4
0xba0 DOEPCTL5
0xba8 DOEPINT5
0xbb0 DOEPTSIZ5
0xbb4 DOEPDMA5
0xbc0 DOEPCTL6
0xbc8 DOEPINT6
0xbd0 DOEPTSIZ6
0xbd4 DOEPDMA6
0xbe0 DOEPCTL7
0xbe8 DOEPINT7
0xbf0 DOEPTSIZ7
0xbf4 DOEPDMA7
0xc00 DOEPCTL8
0xc08 DOEPINT8
0xc10 DOEPTSIZ8
0xc14 DOEPDMA8
0xe00 PCGCCTL
Toggle registers

GOTGCTL

The OTG_GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.

Offset: 0x0, size: 32, reset: 0x00010000, access: Unspecified

7/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURMOD
r 		OTGVER
rw 		BSVLD
r 		ASVLD
r 		DBCT
r 		CIDSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EHEN
rw 		DHNPEN
rw 		HSHNPEN
rw 		HNPRQ
rw 		HNGSCS
r 		BVALOVAL
rw 		BVALOEN
rw 		AVALOVAL
rw 		AVALOEN
rw 		VBVALOVAL
rw 		VBVALOEN
rw 		SRQ
rw 		SRQSCS
r
Toggle fields

SRQSCS

Bit 0: SRQSCS.

SRQ

Bit 1: SRQ.

VBVALOEN

Bit 2: VBVALOEN.

VBVALOVAL

Bit 3: VBVALOVAL.

AVALOEN

Bit 4: AVALOEN.

AVALOVAL

Bit 5: AVALOVAL.

BVALOEN

Bit 6: BVALOEN.

BVALOVAL

Bit 7: BVALOVAL.

HNGSCS

Bit 8: HNGSCS.

HNPRQ

Bit 9: HNPRQ.

HSHNPEN

Bit 10: HSHNPEN.

DHNPEN

Bit 11: DHNPEN.

EHEN

Bit 12: EHEN.

CIDSTS

Bit 16: CIDSTS.

DBCT

Bit 17: DBCT.

ASVLD

Bit 18: ASVLD.

BSVLD

Bit 19: BSVLD.

OTGVER

Bit 20: OTGVER.

CURMOD

Bit 21: CURMOD.

GOTGINT

The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDCHNG
rw 		DBCDNE
rw 		ADTOCHG
rw 		HNGDET
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HNSSCHG
rw 		SRSSCHG
rw 		SEDET
rw
Toggle fields

SEDET

Bit 2: SEDET.

SRSSCHG

Bit 8: SRSSCHG.

HNSSCHG

Bit 9: HNSSCHG.

HNGDET

Bit 17: HNGDET.

ADTOCHG

Bit 18: ADTOCHG.

DBCDNE

Bit 19: DBCDNE.

IDCHNG

Bit 20: IDCHNG.

GAHBCFG

This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFELVL
rw 		TXFELVL
rw 		DMAEN
rw 		HBSTLEN
rw 		GINTMSK
rw
Toggle fields

GINTMSK

Bit 0: GINTMSK.

HBSTLEN

Bits 1-4: HBSTLEN.

DMAEN

Bit 5: DMAEN.

TXFELVL

Bit 7: TXFELVL.

PTXFELVL

Bit 8: PTXFELVL.

GUSBCFG

This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.

Offset: 0xc, size: 32, reset: 0x00001400, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDMOD
rw 		FHMOD
rw 		TSDPS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYLPC
rw 		TRDT
rw 		HNPCAP
rw 		SRPCAP
rw 		PHYSEL
rw 		TOCAL
rw
Toggle fields

TOCAL

Bits 0-2: TOCAL.

PHYSEL

Bit 6: PHYSEL.

SRPCAP

Bit 8: SRPCAP.

HNPCAP

Bit 9: HNPCAP.

TRDT

Bits 10-13: TRDT.

PHYLPC

Bit 15: PHYLPC.

TSDPS

Bit 22: TSDPS.

FHMOD

Bit 29: FHMOD.

FDMOD

Bit 30: FDMOD.

GRSTCTL

The application uses this register to reset various hardware features inside the core.

Offset: 0x10, size: 32, reset: 0x80000000, access: Unspecified

2/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AHBIDL
r 		DMAREQ
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFNUM
rw 		TXFFLSH
rw 		RXFFLSH
rw 		PSRST
rw 		CSRST
rw
Toggle fields

CSRST

Bit 0: CSRST.

PSRST

Bit 1: PSRST.

RXFFLSH

Bit 4: RXFFLSH.

TXFFLSH

Bit 5: TXFFLSH.

TXFNUM

Bits 6-10: TXFNUM.

DMAREQ

Bit 30: DMAREQ.

AHBIDL

Bit 31: AHBIDL.

GINTSTS

This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the OTG_GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.

Offset: 0x14, size: 32, reset: 0x14000020, access: Unspecified

11/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPINT
rw 		SRQINT
rw 		DISCINT
rw 		CIDSCHG
rw 		PTXFE
r 		HCINT
r 		HPRTINT
r 		DATAFSUSP
rw 		IPXFR
rw 		IISOIXFR
rw 		OEPINT
r 		IEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPF
rw 		ISOODRP
rw 		ENUMDNE
rw 		USBRST
rw 		USBSUSP
rw 		ESUSP
rw 		GONAKEFF
r 		GINAKEFF
r 		NPTXFE
r 		RXFLVL
r 		SOF
rw 		OTGINT
r 		MMIS
rw 		CMOD
r
Toggle fields

CMOD

Bit 0: CMOD.

MMIS

Bit 1: MMIS.

OTGINT

Bit 2: OTGINT.

SOF

Bit 3: SOF.

RXFLVL

Bit 4: RXFLVL.

NPTXFE

Bit 5: NPTXFE.

GINAKEFF

Bit 6: GINAKEFF.

GONAKEFF

Bit 7: GONAKEFF.

ESUSP

Bit 10: ESUSP.

USBSUSP

Bit 11: USBSUSP.

USBRST

Bit 12: USBRST.

ENUMDNE

Bit 13: ENUMDNE.

ISOODRP

Bit 14: ISOODRP.

EOPF

Bit 15: EOPF.

IEPINT

Bit 18: IEPINT.

OEPINT

Bit 19: OEPINT.

IISOIXFR

Bit 20: IISOIXFR.

IPXFR

Bit 21: IPXFR.

DATAFSUSP

Bit 22: DATAFSUSP.

HPRTINT

Bit 24: HPRTINT.

HCINT

Bit 25: HCINT.

PTXFE

Bit 26: PTXFE.

CIDSCHG

Bit 28: CIDSCHG.

DISCINT

Bit 29: DISCINT.

SRQINT

Bit 30: SRQINT.

WKUPINT

Bit 31: WKUPINT.

GINTMSK

This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (OTG_GINTSTS) register bit corresponding to that interrupt is still set.

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUIM
rw 		SRQIM
rw 		DISCINT
rw 		CIDSCHGM
rw 		LPMINTM
rw 		PTXFEM
rw 		HCIM
rw 		PRTIM
r 		RSTDETM
rw 		FSUSPM
rw 		IPXFRM
rw 		IISOIXFRM
rw 		OEPINT
rw 		IEPINT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOPFM
rw 		ISOODRPM
rw 		ENUMDNEM
rw 		USBRST
rw 		USBSUSPM
rw 		ESUSPM
rw 		GONAKEFFM
rw 		GINAKEFFM
rw 		NPTXFEM
rw 		RXFLVLM
rw 		SOFM
rw 		OTGINT
rw 		MMISM
rw
Toggle fields

MMISM

Bit 1: MMISM.

OTGINT

Bit 2: OTGINT.

SOFM

Bit 3: SOFM.

RXFLVLM

Bit 4: RXFLVLM.

NPTXFEM

Bit 5: NPTXFEM.

GINAKEFFM

Bit 6: GINAKEFFM.

GONAKEFFM

Bit 7: GONAKEFFM.

ESUSPM

Bit 10: ESUSPM.

USBSUSPM

Bit 11: USBSUSPM.

USBRST

Bit 12: USBRST.

ENUMDNEM

Bit 13: ENUMDNEM.

ISOODRPM

Bit 14: ISOODRPM.

EOPFM

Bit 15: EOPFM.

IEPINT

Bit 18: IEPINT.

OEPINT

Bit 19: OEPINT.

IISOIXFRM

Bit 20: IISOIXFRM.

IPXFRM

Bit 21: IPXFRM.

FSUSPM

Bit 22: FSUSPM.

RSTDETM

Bit 23: RSTDETM.

PRTIM

Bit 24: PRTIM.

HCIM

Bit 25: HCIM.

PTXFEM

Bit 26: PTXFEM.

LPMINTM

Bit 27: LPMINTM.

CIDSCHGM

Bit 28: CIDSCHGM.

DISCINT

Bit 29: DISCINT.

SRQIM

Bit 30: SRQIM.

WUIM

Bit 31: WUIM.

GRXSTSR

This description is for register OTG_GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STSPHST
r 		FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: EPNUM.

BCNT

Bits 4-14: BCNT.

DPID

Bits 15-16: DPID.

PKTSTS

Bits 17-20: PKTSTS.

FRMNUM

Bits 21-24: FRMNUM.

STSPHST

Bit 27: STSPHST.

GRXSTSP

This description is for register OTG_GRXSTSP in Device mode. Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is asserted.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STSPHST
r 		FRMNUM
r 		PKTSTS
r 		DPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DPID
r 		BCNT
r 		EPNUM
r
Toggle fields

EPNUM

Bits 0-3: EPNUM.

BCNT

Bits 4-14: BCNT.

DPID

Bits 15-16: DPID.

PKTSTS

Bits 17-20: PKTSTS.

FRMNUM

Bits 21-24: FRMNUM.

STSPHST

Bit 27: STSPHST.

GRXFSIZ

The application can program the RAM size that must be allocated to the Rx FIFO.

Offset: 0x24, size: 32, reset: 0x00000400, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFD
rw
Toggle fields

RXFD

Bits 0-15: RXFD.

HNPTXFSIZ

Host mode

Offset: 0x28, size: 32, reset: 0x02000200, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSA
rw
Toggle fields

NPTXFSA

Bits 0-15: NPTXFSA.

NPTXFD

Bits 16-31: NPTXFD.

HNPTXSTS

In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue.

Offset: 0x2c, size: 32, reset: 0x00080400, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NPTXQTOP
r 		NPTQXSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NPTXFSAV
r
Toggle fields

NPTXFSAV

Bits 0-15: NPTXFSAV.

NPTQXSAV

Bits 16-23: NPTQXSAV.

NPTXQTOP

Bits 24-30: NPTXQTOP.

GCCFG

OTG general core configuration register

Offset: 0x38, size: 32, reset: 0x00000000, access: Unspecified

3/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDEN
rw 		VBDEN
rw 		SDEN
rw 		PDEN
rw 		BCDEN
rw 		PWRDWN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PS2DET
r 		SDET
r 		PDET
r
Toggle fields

PDET

Bit 1: PDET.

SDET

Bit 2: SDET.

PS2DET

Bit 3: PS2DET.

PWRDWN

Bit 16: PWRDWN.

BCDEN

Bit 17: BCDEN.

PDEN

Bit 19: PDEN.

SDEN

Bit 20: SDEN.

VBDEN

Bit 21: VBDEN.

IDEN

Bit 22: IDEN.

CID

This is a register containing the Product ID as reset value.

Offset: 0x3c, size: 32, reset: 0x00004000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRODUCT_ID
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRODUCT_ID
rw
Toggle fields

PRODUCT_ID

Bits 0-31: PRODUCT_ID.

GLPMCFG

OTG core LPM configuration register

Offset: 0x54, size: 32, reset: 0x00000000, access: Unspecified

4/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENBESL
rw 		LPMRCNTSTS
r 		SNDLPM
rw 		LPMRCNT
rw 		LPMCHIDX
rw 		L1RSMOK
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLPSTS
r 		LPMRSP
r 		L1DSEN
rw 		BESLTHRS
rw 		L1SSEN
rw 		REMWAKE
rw 		BESL
rw 		LPMACK
rw 		LPMEN
rw
Toggle fields

LPMEN

Bit 0: LPMEN.

LPMACK

Bit 1: LPMACK.

BESL

Bits 2-5: BESL.

REMWAKE

Bit 6: REMWAKE.

L1SSEN

Bit 7: L1SSEN.

BESLTHRS

Bits 8-11: BESLTHRS.

L1DSEN

Bit 12: L1DSEN.

LPMRSP

Bits 13-14: LPMRSP.

SLPSTS

Bit 15: SLPSTS.

L1RSMOK

Bit 16: L1RSMOK.

LPMCHIDX

Bits 17-20: LPMCHIDX.

LPMRCNT

Bits 21-23: LPMRCNT.

SNDLPM

Bit 24: SNDLPM.

LPMRCNTSTS

Bits 25-27: LPMRCNTSTS.

ENBESL

Bit 28: ENBESL.

HPTXFSIZ

OTG host periodic transmit FIFO size register

Offset: 0x100, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXFSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXSA
rw
Toggle fields

PTXSA

Bits 0-15: PTXSA.

PTXFSIZ

Bits 16-31: PTXFSIZ.

DIEPTXF1

OTG device IN endpoint transmit FIFO 1 size register

Offset: 0x104, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF2

OTG device IN endpoint transmit FIFO 2 size register

Offset: 0x108, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF3

OTG device IN endpoint transmit FIFO 3 size register

Offset: 0x10c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF4

OTG device IN endpoint transmit FIFO 4 size register

Offset: 0x110, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF5

OTG device IN endpoint transmit FIFO 5 size register

Offset: 0x114, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF6

OTG device IN endpoint transmit FIFO 6 size register

Offset: 0x118, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF7

OTG device IN endpoint transmit FIFO 7 size register

Offset: 0x11c, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

DIEPTXF8

OTG device IN endpoint transmit FIFO 8 size register

Offset: 0x120, size: 32, reset: 0x02000400, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INEPTXFD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXSA
rw
Toggle fields

INEPTXSA

Bits 0-15: INEPTXSA.

INEPTXFD

Bits 16-31: INEPTXFD.

HCFG

This register configures the core after power-on. Do not make changes to this register after initializing the host.

Offset: 0x400, size: 32, reset: 0x00000000, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERSSCHEDENA
rw 		FRLSTEN
rw 		DESCDMA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSLSS
r 		FSLSPCS
rw
Toggle fields

FSLSPCS

Bits 0-1: FSLSPCS.

FSLSS

Bit 2: FSLSS.

DESCDMA

Bit 23: DESCDMA.

FRLSTEN

Bits 24-25: FRLSTEN.

PERSSCHEDENA

Bit 26: PERSSCHEDENA.

HFIR

This register stores the frame interval information for the current speed to which the OTG controller has enumerated.

Offset: 0x404, size: 32, reset: 0x0000EA60, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RLDCTRL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRIVL
rw
Toggle fields

FRIVL

Bits 0-15: FRIVL.

RLDCTRL

Bit 16: RLDCTRL.

HFNUM

This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.

Offset: 0x408, size: 32, reset: 0x00003FFF, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FTREM
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRNUM
r
Toggle fields

FRNUM

Bits 0-15: FRNUM.

FTREM

Bits 16-31: FTREM.

HPTXSTS

This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue.

Offset: 0x410, size: 32, reset: 0x00080100, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTXQTOP
r 		PTXQSAV
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTXFSAVL
r
Toggle fields

PTXFSAVL

Bits 0-15: PTXFSAVL.

PTXQSAV

Bits 16-23: PTXQSAV.

PTXQTOP

Bits 24-31: PTXQTOP.

HAINT

When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in OTG_GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.

Offset: 0x414, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINT
r
Toggle fields

HAINT

Bits 0-15: HAINT.

HAINTMSK

The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HAINTM
rw
Toggle fields

HAINTM

Bits 0-15: HAINTM.

HFLBADDR

This register holds the starting address of the frame list information (scatter/gather mode).

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HFLBADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HFLBADDR
rw
Toggle fields

HFLBADDR

Bits 0-31: HFLBADDR.

HPRT

This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in OTG_GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.

Offset: 0x440, size: 32, reset: 0x00000000, access: Unspecified

4/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PSPD
r 		PTCTL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PTCTL
rw 		PPWR
rw 		PLSTS
r 		PRST
rw 		PSUSP
rw 		PRES
rw 		POCCHNG
rw 		POCA
r 		PENCHNG
rw 		PENA
rw 		PCDET
rw 		PCSTS
r
Toggle fields

PCSTS

Bit 0: PCSTS.

PCDET

Bit 1: PCDET.

PENA

Bit 2: PENA.

PENCHNG

Bit 3: PENCHNG.

POCA

Bit 4: POCA.

POCCHNG

Bit 5: POCCHNG.

PRES

Bit 6: PRES.

PSUSP

Bit 7: PSUSP.

PRST

Bit 8: PRST.

PLSTS

Bits 10-11: PLSTS.

PPWR

Bit 12: PPWR.

PTCTL

Bits 13-16: PTCTL.

PSPD

Bits 17-18: PSPD.

HCCHAR0

OTG host channel 0 characteristics register

Offset: 0x500, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT0

OTG host channel 0 split control register

Offset: 0x504, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT0

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x508, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK0

This register reflects the mask for each channel status described in the previous section.

Offset: 0x50c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ0

OTG host channel 0 transfer size register

Offset: 0x510, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA0

OTG host channel 0 DMA address register in buffer DMA [alternate]

Offset: 0x514, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB0

OTG host channel-n DMA address buffer register

Offset: 0x51c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR1

OTG host channel 1 characteristics register

Offset: 0x520, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT1

OTG host channel 1 split control register

Offset: 0x524, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT1

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x528, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK1

This register reflects the mask for each channel status described in the previous section.

Offset: 0x52c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ1

OTG host channel 1 transfer size register

Offset: 0x530, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA1

OTG host channel 1 DMA address register in buffer DMA [alternate]

Offset: 0x534, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB1

OTG host channel-n DMA address buffer register

Offset: 0x53c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR2

OTG host channel 2 characteristics register

Offset: 0x540, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT2

OTG host channel 2 split control register

Offset: 0x544, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT2

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x548, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK2

This register reflects the mask for each channel status described in the previous section.

Offset: 0x54c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ2

OTG host channel 2 transfer size register

Offset: 0x550, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA2

OTG host channel 2 DMA address register in buffer DMA [alternate]

Offset: 0x554, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB2

OTG host channel-n DMA address buffer register

Offset: 0x55c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR3

OTG host channel 3 characteristics register

Offset: 0x560, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT3

OTG host channel 3 split control register

Offset: 0x564, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT3

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x568, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK3

This register reflects the mask for each channel status described in the previous section.

Offset: 0x56c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ3

OTG host channel 3 transfer size register

Offset: 0x570, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA3

OTG host channel 3 DMA address register in buffer DMA [alternate]

Offset: 0x574, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB3

OTG host channel-n DMA address buffer register

Offset: 0x57c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR4

OTG host channel 4 characteristics register

Offset: 0x580, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT4

OTG host channel 4 split control register

Offset: 0x584, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT4

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x588, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK4

This register reflects the mask for each channel status described in the previous section.

Offset: 0x58c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ4

OTG host channel 4 transfer size register

Offset: 0x590, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA4

OTG host channel 4 DMA address register in buffer DMA [alternate]

Offset: 0x594, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB4

OTG host channel-n DMA address buffer register

Offset: 0x59c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR5

OTG host channel 5 characteristics register

Offset: 0x5a0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT5

OTG host channel 5 split control register

Offset: 0x5a4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT5

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x5a8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK5

This register reflects the mask for each channel status described in the previous section.

Offset: 0x5ac, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ5

OTG host channel 5 transfer size register

Offset: 0x5b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA5

OTG host channel 5 DMA address register in buffer DMA [alternate]

Offset: 0x5b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB5

OTG host channel-n DMA address buffer register

Offset: 0x5bc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR6

OTG host channel 6 characteristics register

Offset: 0x5c0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT6

OTG host channel 6 split control register

Offset: 0x5c4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT6

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x5c8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK6

This register reflects the mask for each channel status described in the previous section.

Offset: 0x5cc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ6

OTG host channel 6 transfer size register

Offset: 0x5d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA6

OTG host channel 6 DMA address register in buffer DMA [alternate]

Offset: 0x5d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB6

OTG host channel-n DMA address buffer register

Offset: 0x5dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR7

OTG host channel 7 characteristics register

Offset: 0x5e0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT7

OTG host channel 7 split control register

Offset: 0x5e4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT7

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x5e8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK7

This register reflects the mask for each channel status described in the previous section.

Offset: 0x5ec, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ7

OTG host channel 7 transfer size register

Offset: 0x5f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA7

OTG host channel 7 DMA address register in buffer DMA [alternate]

Offset: 0x5f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB7

OTG host channel-n DMA address buffer register

Offset: 0x5fc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR8

OTG host channel 8 characteristics register

Offset: 0x600, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT8

OTG host channel 8 split control register

Offset: 0x604, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT8

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x608, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK8

This register reflects the mask for each channel status described in the previous section.

Offset: 0x60c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ8

OTG host channel 8 transfer size register

Offset: 0x610, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA8

OTG host channel 8 DMA address register in buffer DMA [alternate]

Offset: 0x614, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB8

OTG host channel-n DMA address buffer register

Offset: 0x61c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR9

OTG host channel 9 characteristics register

Offset: 0x620, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT9

OTG host channel 9 split control register

Offset: 0x624, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT9

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x628, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK9

This register reflects the mask for each channel status described in the previous section.

Offset: 0x62c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ9

OTG host channel 9 transfer size register

Offset: 0x630, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA9

OTG host channel 9 DMA address register in buffer DMA [alternate]

Offset: 0x634, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB9

OTG host channel-n DMA address buffer register

Offset: 0x63c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR10

OTG host channel 10 characteristics register

Offset: 0x640, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT10

OTG host channel 10 split control register

Offset: 0x644, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT10

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x648, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK10

This register reflects the mask for each channel status described in the previous section.

Offset: 0x64c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ10

OTG host channel 10 transfer size register

Offset: 0x650, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA10

OTG host channel 10 DMA address register in buffer DMA [alternate]

Offset: 0x654, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB10

OTG host channel-n DMA address buffer register

Offset: 0x65c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR11

OTG host channel 11 characteristics register

Offset: 0x660, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT11

OTG host channel 11 split control register

Offset: 0x664, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT11

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x668, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK11

This register reflects the mask for each channel status described in the previous section.

Offset: 0x66c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ11

OTG host channel 11 transfer size register

Offset: 0x670, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA11

OTG host channel 11 DMA address register in buffer DMA [alternate]

Offset: 0x674, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB11

OTG host channel-n DMA address buffer register

Offset: 0x67c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR12

OTG host channel 12 characteristics register

Offset: 0x680, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT12

OTG host channel 12 split control register

Offset: 0x684, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT12

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x688, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK12

This register reflects the mask for each channel status described in the previous section.

Offset: 0x68c, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ12

OTG host channel 12 transfer size register

Offset: 0x690, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA12

OTG host channel 12 DMA address register in buffer DMA [alternate]

Offset: 0x694, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB12

OTG host channel-n DMA address buffer register

Offset: 0x69c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR13

OTG host channel 13 characteristics register

Offset: 0x6a0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT13

OTG host channel 13 split control register

Offset: 0x6a4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT13

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x6a8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK13

This register reflects the mask for each channel status described in the previous section.

Offset: 0x6ac, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ13

OTG host channel 13 transfer size register

Offset: 0x6b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA13

OTG host channel 13 DMA address register in buffer DMA [alternate]

Offset: 0x6b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB13

OTG host channel-n DMA address buffer register

Offset: 0x6bc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR14

OTG host channel 14 characteristics register

Offset: 0x6c0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT14

OTG host channel 14 split control register

Offset: 0x6c4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT14

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x6c8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK14

This register reflects the mask for each channel status described in the previous section.

Offset: 0x6cc, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ14

OTG host channel 14 transfer size register

Offset: 0x6d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA14

OTG host channel 14 DMA address register in buffer DMA [alternate]

Offset: 0x6d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB14

OTG host channel-n DMA address buffer register

Offset: 0x6dc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

HCCHAR15

OTG host channel 15 characteristics register

Offset: 0x6e0, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHENA
rw 		CHDIS
rw 		DAD
rw 		MCNT
rw 		EPTYP
rw 		LSDEV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EPDIR
rw 		EPNUM
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

EPNUM

Bits 11-14: EPNUM.

EPDIR

Bit 15: EPDIR.

LSDEV

Bit 17: LSDEV.

EPTYP

Bits 18-19: EPTYP.

MCNT

Bits 20-21: MCNT.

DAD

Bits 22-28: DAD.

CHDIS

Bit 30: CHDIS.

CHENA

Bit 31: CHENA.

HCSPLT15

OTG host channel 15 split control register

Offset: 0x6e4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPLITEN
rw 		COMPLSPLT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XACTPOS
rw 		HUBADDR
rw 		PRTADDR
rw
Toggle fields

PRTADDR

Bits 0-6: PRTADDR.

HUBADDR

Bits 7-13: HUBADDR.

XACTPOS

Bits 14-15: XACTPOS.

COMPLSPLT

Bit 16: COMPLSPLT.

SPLITEN

Bit 31: SPLITEN.

HCINT15

This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (OTG_HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_HAINT and OTG_GINTSTS registers.

Offset: 0x6e8, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLL
rw 		XCSXACTERR
rw 		BNA
rw 		DTERR
rw 		FRMOR
rw 		BBERR
rw 		TXERR
rw 		NYET
rw 		ACK
rw 		NAK
rw 		STALL
rw 		AHBERR
rw 		CHH
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

CHH

Bit 1: CHH.

AHBERR

Bit 2: AHBERR.

STALL

Bit 3: STALL.

NAK

Bit 4: NAK.

ACK

Bit 5: ACK.

NYET

Bit 6: NYET.

TXERR

Bit 7: TXERR.

BBERR

Bit 8: BBERR.

FRMOR

Bit 9: FRMOR.

DTERR

Bit 10: DTERR.

BNA

Bit 11: BNA.

XCSXACTERR

Bit 12: XCSXACTERR.

DESCLSTROLL

Bit 13: DESCLSTROLL.

HCINTMSK15

This register reflects the mask for each channel status described in the previous section.

Offset: 0x6ec, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DESCLSTROLLMSK
rw 		BNAMSK
rw 		DTERRM
rw 		FRMORM
rw 		BBERRM
rw 		TXERRM
rw 		NYET
rw 		ACKM
rw 		NAKM
rw 		STALLM
rw 		AHBERRM
rw 		CHHM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

CHHM

Bit 1: CHHM.

AHBERRM

Bit 2: AHBERRM.

STALLM

Bit 3: STALLM.

NAKM

Bit 4: NAKM.

ACKM

Bit 5: ACKM.

NYET

Bit 6: NYET.

TXERRM

Bit 7: TXERRM.

BBERRM

Bit 8: BBERRM.

FRMORM

Bit 9: FRMORM.

DTERRM

Bit 10: DTERRM.

BNAMSK

Bit 11: BNAMSK.

DESCLSTROLLMSK

Bit 13: DESCLSTROLLMSK.

HCTSIZ15

OTG host channel 15 transfer size register

Offset: 0x6f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DPID
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

DPID

Bits 29-30: DPID.

HCDMA15

OTG host channel 15 DMA address register in buffer DMA [alternate]

Offset: 0x6f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

HCDMAB15

OTG host channel-n DMA address buffer register

Offset: 0x6fc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HCDMAB
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HCDMAB
r
Toggle fields

HCDMAB

Bits 0-31: HCDMAB.

DCFG

This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

Offset: 0x800, size: 32, reset: 0x02200000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PERSCHIVL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRATIM
rw 		XCVRDLY
rw 		PFIVL
rw 		DAD
rw 		NZLSOHSK
rw 		DSPD
rw
Toggle fields

DSPD

Bits 0-1: DSPD.

NZLSOHSK

Bit 2: NZLSOHSK.

DAD

Bits 4-10: DAD.

PFIVL

Bits 11-12: PFIVL.

XCVRDLY

Bit 14: XCVRDLY.

ERRATIM

Bit 15: ERRATIM.

PERSCHIVL

Bits 24-25: PERSCHIVL.

DCTL

OTG device control register

Offset: 0x804, size: 32, reset: 0x00000002, access: Unspecified

2/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSBESLRJCT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POPRGDNE
rw 		CGONAK
w 		SGONAK
w 		CGINAK
w 		SGINAK
w 		TCTL
rw 		GONSTS
r 		GINSTS
r 		SDIS
rw 		RWUSIG
rw
Toggle fields

RWUSIG

Bit 0: RWUSIG.

SDIS

Bit 1: SDIS.

GINSTS

Bit 2: GINSTS.

GONSTS

Bit 3: GONSTS.

TCTL

Bits 4-6: TCTL.

SGINAK

Bit 7: SGINAK.

CGINAK

Bit 8: CGINAK.

SGONAK

Bit 9: SGONAK.

CGONAK

Bit 10: CGONAK.

POPRGDNE

Bit 11: POPRGDNE.

DSBESLRJCT

Bit 18: DSBESLRJCT.

DSTS

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (OTG_DAINT) register.

Offset: 0x808, size: 32, reset: 0x00000010, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DEVLNSTS
r 		FNSOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FNSOF
r 		EERR
r 		ENUMSPD
r 		SUSPSTS
r
Toggle fields

SUSPSTS

Bit 0: SUSPSTS.

ENUMSPD

Bits 1-2: ENUMSPD.

EERR

Bit 3: EERR.

FNSOF

Bits 8-21: FNSOF.

DEVLNSTS

Bits 22-23: DEVLNSTS.

DIEPMSK

This register works with each of the OTG_DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the OTG_DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.

Offset: 0x810, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKM
rw 		BNAM
rw 		TXFURM
rw 		INEPNEM
rw 		INEPNMM
rw 		ITTXFEMSK
rw 		TOM
rw 		AHBERRM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

EPDM

Bit 1: EPDM.

AHBERRM

Bit 2: AHBERRM.

TOM

Bit 3: TOM.

ITTXFEMSK

Bit 4: ITTXFEMSK.

INEPNMM

Bit 5: INEPNMM.

INEPNEM

Bit 6: INEPNEM.

TXFURM

Bit 8: TXFURM.

BNAM

Bit 9: BNAM.

NAKM

Bit 13: NAKM.

DOEPMSK

This register works with each of the OTG_DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the OTG_DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

Offset: 0x814, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETMSK
rw 		NAKMSK
rw 		BERRM
rw 		BNAM
rw 		OUTPKTERRM
rw 		B2BSTUPM
rw 		STSPHSRXM
rw 		OTEPDM
rw 		STUPM
rw 		AHBERRM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

EPDM

Bit 1: EPDM.

AHBERRM

Bit 2: AHBERRM.

STUPM

Bit 3: STUPM.

OTEPDM

Bit 4: OTEPDM.

STSPHSRXM

Bit 5: STSPHSRXM.

B2BSTUPM

Bit 6: B2BSTUPM.

OUTPKTERRM

Bit 8: OUTPKTERRM.

BNAM

Bit 9: BNAM.

BERRM

Bit 12: BERRM.

NAKMSK

Bit 13: NAKMSK.

NYETMSK

Bit 14: NYETMSK.

DAINT

When a significant event occurs on an endpoint, a OTG_DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the OTG_GINTSTS register (OEPINT or IEPINT in OTG_GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).

Offset: 0x818, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPINT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPINT
r
Toggle fields

IEPINT

Bits 0-15: IEPINT.

OEPINT

Bits 16-31: OEPINT.

DAINTMSK

The OTG_DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_DAINT register bit corresponding to that interrupt is still set.

Offset: 0x81c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEPM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEPM
rw
Toggle fields

IEPM

Bits 0-15: IEPM.

OEPM

Bits 16-31: OEPM.

DVBUSDIS

This register specifies the VBUS discharge time after VBUS pulsing during SRP.

Offset: 0x828, size: 32, reset: 0x000017D7, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VBUSDT
rw
Toggle fields

VBUSDT

Bits 0-15: VBUSDT.

DVBUSPULSE

This register specifies the VBUS pulsing time during SRP.

Offset: 0x82c, size: 32, reset: 0x000005B8, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DVBUSP
rw
Toggle fields

DVBUSP

Bits 0-15: DVBUSP.

DTHRCTL

OTG device threshold control register

Offset: 0x830, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ARPEN
rw 		RXTHRLEN
rw 		RXTHREN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXTHRLEN
rw 		ISOTHREN
rw 		NONISOTHREN
rw
Toggle fields

NONISOTHREN

Bit 0: NONISOTHREN.

ISOTHREN

Bit 1: ISOTHREN.

TXTHRLEN

Bits 2-10: TXTHRLEN.

RXTHREN

Bit 16: RXTHREN.

RXTHRLEN

Bits 17-25: RXTHRLEN.

ARPEN

Bit 27: ARPEN.

DIEPEMPMSK

This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_OTG_DIEPINTx).

Offset: 0x834, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTXFEM
rw
Toggle fields

INEPTXFEM

Bits 0-15: INEPTXFEM.

DEACHINT

OTG device each endpoint interrupt register

Offset: 0x838, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INT
r
Toggle fields

IEP1INT

Bit 1: IEP1INT.

OEP1INT

Bit 17: OEP1INT.

DEACHINTMSK

There is one interrupt bit for endpoint 1 IN and one interrupt bit for endpoint 1 OUT.

Offset: 0x83c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OEP1INTM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IEP1INTM
rw
Toggle fields

IEP1INTM

Bit 1: IEP1INTM.

OEP1INTM

Bit 17: OEP1INTM.

HS_DIEPEACHMSK1

This register works with the OTG_DIEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_IN for endpoint #1. The IN endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

Offset: 0x844, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAKM
rw 		BNAM
rw 		TXFURM
rw 		INEPNEM
rw 		ITTXFEMSK
rw 		TOM
rw 		AHBERRM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

EPDM

Bit 1: EPDM.

AHBERRM

Bit 2: AHBERRM.

TOM

Bit 3: TOM.

ITTXFEMSK

Bit 4: ITTXFEMSK.

INEPNEM

Bit 6: INEPNEM.

TXFURM

Bit 8: TXFURM.

BNAM

Bit 9: BNAM.

NAKM

Bit 13: NAKM.

HS_DOEPEACHMSK1

This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.

Offset: 0x884, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NYETMSK
rw 		NAKMSK
rw 		BERRM
rw 		BNAM
rw 		OUTPKTERRM
rw 		B2BSTUPM
rw 		OTEPDM
rw 		STUPM
rw 		AHBERRM
rw 		EPDM
rw 		XFRCM
rw
Toggle fields

XFRCM

Bit 0: XFRCM.

EPDM

Bit 1: EPDM.

AHBERRM

Bit 2: AHBERRM.

STUPM

Bit 3: STUPM.

OTEPDM

Bit 4: OTEPDM.

B2BSTUPM

Bit 6: B2BSTUPM.

OUTPKTERRM

Bit 8: OUTPKTERRM.

BNAM

Bit 9: BNAM.

BERRM

Bit 12: BERRM.

NAKMSK

Bit 13: NAKMSK.

NYETMSK

Bit 14: NYETMSK.

DIEPCTL0

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x900, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT0

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x908, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ0

The application must modify this register before enabling endpoint 0.

Offset: 0x910, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: XFRSIZ.

PKTCNT

Bits 19-20: PKTCNT.

DIEPDMA0

OTG device IN endpoint 0 DMA address register

Offset: 0x914, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS0

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x918, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL1

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x920, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT1

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x928, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ1

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x930, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA1

OTG device IN endpoint 1 DMA address register

Offset: 0x934, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS1

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x938, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL2

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x940, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT2

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x948, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ2

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x950, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA2

OTG device IN endpoint 2 DMA address register

Offset: 0x954, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS2

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x958, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL3

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x960, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT3

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x968, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ3

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x970, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA3

OTG device IN endpoint 3 DMA address register

Offset: 0x974, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS3

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x978, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL4

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x980, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT4

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x988, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ4

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x990, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA4

OTG device IN endpoint 4 DMA address register

Offset: 0x994, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS4

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x998, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL5

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x9a0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT5

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x9a8, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ5

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x9b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA5

OTG device IN endpoint 5 DMA address register

Offset: 0x9b4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS5

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x9b8, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL6

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x9c0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT6

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x9c8, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ6

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x9d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA6

OTG device IN endpoint 6 DMA address register

Offset: 0x9d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS6

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x9d8, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL7

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0x9e0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT7

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0x9e8, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ7

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0x9f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA7

OTG device IN endpoint 7 DMA address register

Offset: 0x9f4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS7

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0x9f8, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DIEPCTL8

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xa00, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		TXFNUM
rw 		STALL
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

STALL

Bit 21: STALL.

TXFNUM

Bits 22-25: TXFNUM.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SODDFRM

Bit 29: SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DIEPINT8

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in OTG_GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (OTG_DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xa08, size: 32, reset: 0x00000080, access: Unspecified

2/12 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NAK
rw 		PKTDRPSTS
rw 		BNA
rw 		TXFIFOUDRN
rw 		TXFE
r 		INEPNE
r 		INEPNM
rw 		ITTXFE
rw 		TOC
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

TOC

Bit 3: TOC.

ITTXFE

Bit 4: ITTXFE.

INEPNM

Bit 5: INEPNM.

INEPNE

Bit 6: INEPNE.

TXFE

Bit 7: TXFE.

TXFIFOUDRN

Bit 8: TXFIFOUDRN.

BNA

Bit 9: BNA.

PKTDRPSTS

Bit 11: PKTDRPSTS.

NAK

Bit 13: NAK.

DIEPTSIZ8

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the OTG_DIEPCTLx registers (EPENA bit in OTG_DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xa10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

MCNT

Bits 29-30: MCNT.

DIEPDMA8

OTG device IN endpoint 8 DMA address register

Offset: 0xa14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DTXFSTS8

This read-only register contains the free space information for the device IN endpoint Tx FIFO.

Offset: 0xa18, size: 32, reset: 0x00000200, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INEPTFSAV
r
Toggle fields

INEPTFSAV

Bits 0-15: INEPTFSAV.

DOEPCTL0

This section describes the OTG_DOEPCTL0 register.

Offset: 0xb00, size: 32, reset: 0x00008000, access: Unspecified

5/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
w 		EPDIS
r 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
r 		NAKSTS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
r 		MPSIZ
r
Toggle fields

MPSIZ

Bits 0-1: MPSIZ.

USBAEP

Bit 15: USBAEP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT0

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xb08, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ0

The application must modify this register before enabling endpoint 0.

Offset: 0xb10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STUPCNT
rw 		PKTCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-6: XFRSIZ.

PKTCNT

Bit 19: PKTCNT.

STUPCNT

Bits 29-30: STUPCNT.

DOEPDMA0

OTG device OUT endpoint 0 DMA address register

Offset: 0xb14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL1

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xb20, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT1

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xb28, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ1

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xb30, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA1

OTG device OUT endpoint 1 DMA address register

Offset: 0xb34, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL2

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xb40, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT2

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xb48, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ2

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xb50, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA2

OTG device OUT endpoint 2 DMA address register

Offset: 0xb54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL3

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xb60, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT3

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xb68, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ3

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xb70, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA3

OTG device OUT endpoint 3 DMA address register

Offset: 0xb74, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL4

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xb80, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT4

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xb88, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ4

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xb90, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA4

OTG device OUT endpoint 4 DMA address register

Offset: 0xb94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL5

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xba0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT5

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xba8, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ5

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xbb0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA5

OTG device OUT endpoint 5 DMA address register

Offset: 0xbb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL6

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xbc0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT6

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xbc8, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ6

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xbd0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA6

OTG device OUT endpoint 6 DMA address register

Offset: 0xbd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL7

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xbe0, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT7

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xbe8, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ7

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xbf0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA7

OTG device OUT endpoint 7 DMA address register

Offset: 0xbf4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

DOEPCTL8

The application uses this register to control the behavior of each logical endpoint other than endpoint 0.

Offset: 0xc00, size: 32, reset: 0x00000000, access: Unspecified

2/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EPENA
rw 		EPDIS
rw 		SD1PID_SODDFRM
w 		SD0PID_SEVNFRM
w 		SNAK
w 		CNAK
w 		STALL
rw 		SNPM
rw 		EPTYP
rw 		NAKSTS
r 		EONUM_DPIP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBAEP
rw 		MPSIZ
rw
Toggle fields

MPSIZ

Bits 0-10: MPSIZ.

USBAEP

Bit 15: USBAEP.

EONUM_DPIP

Bit 16: EONUM_DPIP.

NAKSTS

Bit 17: NAKSTS.

EPTYP

Bits 18-19: EPTYP.

SNPM

Bit 20: SNPM.

STALL

Bit 21: STALL.

CNAK

Bit 26: CNAK.

SNAK

Bit 27: SNAK.

SD0PID_SEVNFRM

Bit 28: SD0PID_SEVNFRM.

SD1PID_SODDFRM

Bit 29: SD1PID_SODDFRM.

EPDIS

Bit 30: EPDIS.

EPENA

Bit 31: EPENA.

DOEPINT8

This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the OTG_GINTSTS register (OEPINT bit in OTG_GINTSTS) is set. Before the application can read this register, it must first read the OTG_DAINT register to get the exact endpoint number for the OTG_DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the OTG_DAINT and OTG_GINTSTS registers.

Offset: 0xc08, size: 32, reset: 0x00000080, access: read-write

0/13 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPKTRX
rw 		NYET
rw 		NAK
rw 		BERR
rw 		BNA
rw 		OUTPKTERR
rw 		B2BSTUP
rw 		STSPHSRX
rw 		OTEPDIS
rw 		STUP
rw 		AHBERR
rw 		EPDISD
rw 		XFRC
rw
Toggle fields

XFRC

Bit 0: XFRC.

EPDISD

Bit 1: EPDISD.

AHBERR

Bit 2: AHBERR.

STUP

Bit 3: STUP.

OTEPDIS

Bit 4: OTEPDIS.

STSPHSRX

Bit 5: STSPHSRX.

B2BSTUP

Bit 6: B2BSTUP.

OUTPKTERR

Bit 8: OUTPKTERR.

BNA

Bit 9: BNA.

BERR

Bit 12: BERR.

NAK

Bit 13: NAK.

NYET

Bit 14: NYET.

STPKTRX

Bit 15: STPKTRX.

DOEPTSIZ8

The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the OTG_DOEPCTLx registers (EPENA bit in OTG_DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit.

Offset: 0xc10, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDPID_STUPCNT
rw 		PKTCNT
rw 		XFRSIZ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFRSIZ
rw
Toggle fields

XFRSIZ

Bits 0-18: XFRSIZ.

PKTCNT

Bits 19-28: PKTCNT.

RXDPID_STUPCNT

Bits 29-30: RXDPID_STUPCNT.

DOEPDMA8

OTG device OUT endpoint 8 DMA address register

Offset: 0xc14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAADDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAADDR
rw
Toggle fields

DMAADDR

Bits 0-31: DMAADDR.

PCGCCTL

This register is available in host and device modes.

Offset: 0xe00, size: 32, reset: 0x200B8000, access: Unspecified

3/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP
r 		PHYSLEEP
r 		ENL1GTG
rw 		PHYSUSP
r 		GATEHCLK
rw 		STPPCLK
rw
Toggle fields

STPPCLK

Bit 0: STPPCLK.

GATEHCLK

Bit 1: GATEHCLK.

PHYSUSP

Bit 4: PHYSUSP.

ENL1GTG

Bit 5: ENL1GTG.

PHYSLEEP

Bit 6: PHYSLEEP.

SUSP

Bit 7: SUSP.

PWR

0x50001000: PWR

28/83 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CSR1
0x8 CR2
0xc CR3
0x10 MPUCR
0x14 MCUCR
0x20 WKUPCR
0x24 WKUPFR
0x28 MPUWKUPENR
0x2c MCUWKUPENR
0x3f4 VER
0x3f8 ID
0x3fc SID
Toggle registers

CR1

Reset on any system reset. This register provides write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALS
rw 		AVDEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBP
rw 		PLS
rw 		PVDEN
rw 		LVDS
rw 		LPCFG
rw 		LPDS
rw
Toggle fields

LPDS

Bit 0: LPDS.

LPCFG

Bit 1: LPCFG.

LVDS

Bit 2: LVDS.

PVDEN

Bit 4: PVDEN.

PLS

Bits 5-7: PLS.

DBP

Bit 8: DBP.

AVDEN

Bit 16: AVDEN.

ALS

Bits 17-18: ALS.

CSR1

Reset on any system reset.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AVDO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVDO
r
Toggle fields

PVDO

Bit 4: PVDO.

AVDO

Bit 16: AVDO.

CR2

Not reset by wakeup from Standby mode, Application reset (NRST, IWDG, ...) and VDD POR, but reset only by VSW POR and VSWRST. Access 6 wait states when writing this register. After reset the register is write-protected and the DBP bit in the PWR control register 1 (PWR_CR1) has to be set before it can be written. When DBP is cleared, there is no bus errors generated when writing this register. This register shall not be accessed when the RCC VSWRST register bit in Section10.7.89: RCC Backup Domain Control Register (RCC_BDCR) resets the VSW domain. This register provides Write access security when enabled by TZEN register bit in Section10.7.2: RCC TrustZone Control Register (RCC_TZCR). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

6/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEMPH
r 		TEMPL
r 		VBATH
r 		VBATL
r 		RRRDY
r 		BRRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MONEN
rw 		RREN
rw 		BREN
rw
Toggle fields

BREN

Bit 0: BREN.

RREN

Bit 1: RREN.

MONEN

Bit 4: MONEN.

BRRDY

Bit 16: BRRDY.

RRRDY

Bit 17: RRRDY.

VBATL

Bit 20: VBATL.

VBATH

Bit 21: VBATH.

TEMPL

Bit 22: TEMPL.

TEMPH

Bit 23: TEMPH.

CR3

Not reset by wakeup from Standby mode and Application reset (such as NRST, IWDG) but only reset by VDD POR. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0xc, size: 32, reset: 0x50000000, access: Unspecified

3/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REG11RDY
r 		REG11EN
rw 		REG18RDY
r 		REG18EN
rw 		USB33RDY
r 		USB33DEN
rw 		POPL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRRETEN
rw 		DDRSRDIS
rw 		DDRSREN
rw 		VBRS
rw 		VBE
rw
Toggle fields

VBE

Bit 8: VBE.

VBRS

Bit 9: VBRS.

DDRSREN

Bit 10: DDRSREN.

DDRSRDIS

Bit 11: DDRSRDIS.

DDRRETEN

Bit 12: DDRRETEN.

POPL

Bits 17-21: POPL.

USB33DEN

Bit 24: USB33DEN.

USB33RDY

Bit 26: USB33RDY.

REG18EN

Bit 28: REG18EN.

REG18RDY

Bit 29: REG18RDY.

REG11EN

Bit 30: REG11EN.

REG11RDY

Bit 31: REG11RDY.

MPUCR

See individual bits for reset condition. Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access generates a bus error. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0x10, size: 32, reset: 0x00000000, access: Unspecified

4/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STANDBYWFIL2
r 		CSSF
rw 		SBFMPU
r 		SBF
r 		STOPF
r 		CSTBYDIS
rw 		PDDS
rw
Toggle fields

PDDS

Bit 0: PDDS.

CSTBYDIS

Bit 3: CSTBYDIS.

STOPF

Bit 5: STOPF.

SBF

Bit 6: SBF.

SBFMPU

Bit 7: SBFMPU.

CSSF

Bit 9: CSSF.

STANDBYWFIL2

Bit 15: STANDBYWFIL2.

MCUCR

See individual bits for reset condition. Access 6 wait states when writing this register. This register is always non-secure. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0x14, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEEPSLEEP
r 		CSSF
rw 		SBF
r 		STOPF
r 		PDDS
rw
Toggle fields

PDDS

Bit 0: PDDS.

STOPF

Bit 5: STOPF.

SBF

Bit 6: SBF.

CSSF

Bit 9: CSSF.

DEEPSLEEP

Bit 15: DEEPSLEEP.

WKUPCR

Not reset by wakeup from Standby mode, but by any application reset (such as NRST, IWDG). Access 6 wait states when writing this register (when clearing a WKUPF, the AHB write access completes after the WKUPF has cleared). This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access on individual WKUPC[6:1], WKUPP[6:1] bits and WKUPPUPD[6:1] bit pairs are discarded when the corresponding WKUPEN[6:1] bit in PWR MPU wakeup enable register (PWR_MPUWKUPENR) is set. No bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPPUPD6
rw 		WKUPPUPD5
rw 		WKUPPUPD4
rw 		WKUPPUPD3
rw 		WKUPPUPD2
rw 		WKUPPUPD1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPP6
rw 		WKUPP5
rw 		WKUPP4
rw 		WKUPP3
rw 		WKUPP2
rw 		WKUPP1
rw 		WKUPC6
rw 		WKUPC5
rw 		WKUPC4
rw 		WKUPC3
rw 		WKUPC2
rw 		WKUPC1
rw
Toggle fields

WKUPC1

Bit 0: WKUPC1.

WKUPC2

Bit 1: WKUPC2.

WKUPC3

Bit 2: WKUPC3.

WKUPC4

Bit 3: WKUPC4.

WKUPC5

Bit 4: WKUPC5.

WKUPC6

Bit 5: WKUPC6.

WKUPP1

Bit 8: WKUPP1.

WKUPP2

Bit 9: WKUPP2.

WKUPP3

Bit 10: WKUPP3.

WKUPP4

Bit 11: WKUPP4.

WKUPP5

Bit 12: WKUPP5.

WKUPP6

Bit 13: WKUPP6.

WKUPPUPD1

Bits 16-17: WKUPPUPD1.

WKUPPUPD2

Bits 18-19: WKUPPUPD2.

WKUPPUPD3

Bits 20-21: WKUPPUPD3.

WKUPPUPD4

Bits 22-23: WKUPPUPD4.

WKUPPUPD5

Bits 24-25: WKUPPUPD5.

WKUPPUPD6

Bits 26-27: WKUPPUPD6.

WKUPFR

Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...)

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPF6
r 		WKUPF5
r 		WKUPF4
r 		WKUPF3
r 		WKUPF2
r 		WKUPF1
r
Toggle fields

WKUPF1

Bit 0: WKUPF1.

WKUPF2

Bit 1: WKUPF2.

WKUPF3

Bit 2: WKUPF3.

WKUPF4

Bit 3: WKUPF4.

WKUPF5

Bit 4: WKUPF5.

WKUPF6

Bit 5: WKUPF6.

MPUWKUPENR

Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...). Access 6 wait states when writing this register. This register provides Write access security when enabled by TZEN register bit in Section10: Reset and clock control (RCC). When security is enabled a non-secure write access is discarded and a bus error is generated. Secure and non-secure read accesses are granted and return the register value. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPEN6
rw 		WKUPEN5
rw 		WKUPEN4
rw 		WKUPEN3
rw 		WKUPEN2
rw 		WKUPEN1
rw
Toggle fields

WKUPEN1

Bit 0: WKUPEN1.

WKUPEN2

Bit 1: WKUPEN2.

WKUPEN3

Bit 2: WKUPEN3.

WKUPEN4

Bit 3: WKUPEN4.

WKUPEN5

Bit 4: WKUPEN5.

WKUPEN6

Bit 5: WKUPEN6.

MCUWKUPENR

Not reset by wakeup from Standby mode but by any Application reset (NRST, IWDG, ...) Access 6 wait states when writing this register. When a system reset occurs during the register write cycle the written data is not guaranteed.

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WKUPEN6
rw 		WKUPEN5
rw 		WKUPEN4
rw 		WKUPEN3
rw 		WKUPEN2
rw 		WKUPEN1
rw
Toggle fields

WKUPEN1

Bit 0: WKUPEN1.

WKUPEN2

Bit 1: WKUPEN2.

WKUPEN3

Bit 2: WKUPEN3.

WKUPEN4

Bit 3: WKUPEN4.

WKUPEN5

Bit 4: WKUPEN5.

WKUPEN6

Bit 5: WKUPEN6.

VER

PWR IP version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

ID

PWR IP identification register

Offset: 0x3f8, size: 32, reset: 0x00010001, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IPID.

SID

PWR size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

QUADSPI

0x58003000: QUADSPI1

15/59 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 DCR
0x8 SR
0xc FCR
0x10 DLR
0x14 CCR
0x18 AR
0x1c ABR
0x20 DR
0x24 PSMKR
0x28 PSMAR
0x2c PIR
0x30 LPTR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

QUADSPI control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRESCALER
rw 		PMM
rw 		APMS
rw 		TOIE
rw 		SMIE
rw 		FTIE
rw 		TCIE
rw 		TEIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTHRES
rw 		FSEL
rw 		DFM
rw 		SSHIFT
rw 		TCEN
rw 		DMAEN
rw 		ABORT
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

ABORT

Bit 1: ABORT.

DMAEN

Bit 2: DMAEN.

TCEN

Bit 3: TCEN.

SSHIFT

Bit 4: SSHIFT.

DFM

Bit 6: DFM.

FSEL

Bit 7: FSEL.

FTHRES

Bits 8-11: FTHRES.

TEIE

Bit 16: TEIE.

TCIE

Bit 17: TCIE.

FTIE

Bit 18: FTIE.

SMIE

Bit 19: SMIE.

TOIE

Bit 20: TOIE.

APMS

Bit 22: APMS.

PMM

Bit 23: PMM.

PRESCALER

Bits 24-31: PRESCALER.

DCR

QUADSPI device configuration register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSHT
rw 		CKMODE
rw
Toggle fields

CKMODE

Bit 0: CKMODE.

CSHT

Bits 8-10: CSHT.

FSIZE

Bits 16-20: FSIZE.

SR

QUADSPI status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLEVEL
r 		BUSY
r 		TOF
r 		SMF
r 		FTF
r 		TCF
r 		TEF
r
Toggle fields

TEF

Bit 0: TEF.

TCF

Bit 1: TCF.

FTF

Bit 2: FTF.

SMF

Bit 3: SMF.

TOF

Bit 4: TOF.

BUSY

Bit 5: BUSY.

FLEVEL

Bits 8-12: FLEVEL.

FCR

QUADSPI flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTOF
w 		CSMF
w 		CTCF
w 		CTEF
w
Toggle fields

CTEF

Bit 0: CTEF.

CTCF

Bit 1: CTCF.

CSMF

Bit 3: CSMF.

CTOF

Bit 4: CTOF.

DLR

QUADSPI data length register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DL
rw
Toggle fields

DL

Bits 0-31: DL.

CCR

QUADSPI communication configuration register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDRM
rw 		DHHC
rw 		FRCM
rw 		SIOO
rw 		FMODE
rw 		DMODE
rw 		DCYC
rw 		ABSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABMODE
rw 		ADSIZE
rw 		ADMODE
rw 		IMODE
rw 		INSTRUCTION
rw
Toggle fields

INSTRUCTION

Bits 0-7: INSTRUCTION.

IMODE

Bits 8-9: IMODE.

ADMODE

Bits 10-11: ADMODE.

ADSIZE

Bits 12-13: ADSIZE.

ABMODE

Bits 14-15: ABMODE.

ABSIZE

Bits 16-17: ABSIZE.

DCYC

Bits 18-22: DCYC.

DMODE

Bits 24-25: DMODE.

FMODE

Bits 26-27: FMODE.

SIOO

Bit 28: SIOO.

FRCM

Bit 29: FRCM.

DHHC

Bit 30: DHHC.

DDRM

Bit 31: DDRM.

AR

QUADSPI address register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDRESS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS
rw
Toggle fields

ADDRESS

Bits 0-31: ADDRESS.

ABR

QUADSPI alternate bytes registers

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALTERNATE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALTERNATE
rw
Toggle fields

ALTERNATE

Bits 0-31: ALTERNATE.

DR

QUADSPI data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

PSMKR

QUADSPI polling status mask register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
rw
Toggle fields

MASK

Bits 0-31: MASK.

PSMAR

QUADSPI polling status match register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH
rw
Toggle fields

MATCH

Bits 0-31: MATCH.

PIR

QUADSPI polling interval register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTERVAL
rw
Toggle fields

INTERVAL

Bits 0-15: INTERVAL.

LPTR

QUADSPI low-power timeout register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMEOUT
rw
Toggle fields

TIMEOUT

Bits 0-15: TIMEOUT.

HWCFGR

QUADSPI HW configuration register

Offset: 0x3f0, size: 32, reset: 0x0000B058, access: read-only

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDLENGTH
r 		PRESCVAL
r 		FIFOPTR
r 		FIFOSIZE
r
Toggle fields

FIFOSIZE

Bits 0-3: FIFOSIZE.

FIFOPTR

Bits 4-7: FIFOPTR.

PRESCVAL

Bits 8-11: PRESCVAL.

IDLENGTH

Bits 12-15: IDLENGTH.

VERR

QUADSPI version register

Offset: 0x3f4, size: 32, reset: 0x00000041, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

QUADSPI identification register

Offset: 0x3f8, size: 32, reset: 0x00140031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

QUADSPI size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

RCC

0x50000000: RCC

38/1428 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TZCR
0xc OCENSETR
0x10 OCENCLRR
0x18 HSICFGR
0x1c CSICFGR
0x20 MPCKSELR
0x24 ASSCKSELR
0x28 RCK12SELR
0x2c MPCKDIVR
0x30 AXIDIVR
0x3c APB4DIVR
0x40 APB5DIVR
0x44 RTCDIVR
0x48 MSSCKSELR
0x80 PLL1CR
0x84 PLL1CFGR1
0x88 PLL1CFGR2
0x8c PLL1FRACR
0x90 PLL1CSGR
0x94 PLL2CR
0x98 PLL2CFGR1
0x9c PLL2CFGR2
0xa0 PLL2FRACR
0xa4 PLL2CSGR
0xc0 I2C46CKSELR
0xc4 SPI6CKSELR
0xc8 UART1CKSELR
0xcc RNG1CKSELR
0xd0 CPERCKSELR
0xd4 STGENCKSELR
0xd8 DDRITFCR
0x100 MP_BOOTCR
0x104 MP_SREQSETR
0x108 MP_SREQCLRR
0x10c MP_GCR
0x110 MP_APRSTCR
0x114 MP_APRSTSR
0x140 BDCR
0x144 RDLSICR
0x180 APB4RSTSETR
0x184 APB4RSTCLRR
0x188 APB5RSTSETR
0x18c APB5RSTCLRR
0x190 AHB5RSTSETR
0x194 AHB5RSTCLRR
0x198 AHB6RSTSETR
0x19c AHB6RSTCLRR
0x1a0 TZAHB6RSTSETR
0x1a4 TZAHB6RSTCLRR
0x200 MP_APB4ENSETR
0x204 MP_APB4ENCLRR
0x208 MP_APB5ENSETR
0x20c MP_APB5ENCLRR
0x210 MP_AHB5ENSETR
0x214 MP_AHB5ENCLRR
0x218 MP_AHB6ENSETR
0x21c MP_AHB6ENCLRR
0x220 MP_TZAHB6ENSETR
0x224 MP_TZAHB6ENCLRR
0x280 MC_APB4ENSETR
0x284 MC_APB4ENCLRR
0x288 MC_APB5ENSETR
0x28c MC_APB5ENCLRR
0x290 MC_AHB5ENSETR
0x294 MC_AHB5ENCLRR
0x298 MC_AHB6ENSETR
0x29c MC_AHB6ENCLRR
0x300 MP_APB4LPENSETR
0x304 MP_APB4LPENCLRR
0x308 MP_APB5LPENSETR
0x30c MP_APB5LPENCLRR
0x310 MP_AHB5LPENSETR
0x314 MP_AHB5LPENCLRR
0x318 MP_AHB6LPENSETR
0x31c MP_AHB6LPENCLRR
0x320 MP_TZAHB6LPENSETR
0x324 MP_TZAHB6LPENCLRR
0x380 MC_APB4LPENSETR
0x384 MC_APB4LPENCLRR
0x388 MC_APB5LPENSETR
0x38c MC_APB5LPENCLRR
0x390 MC_AHB5LPENSETR
0x394 MC_AHB5LPENCLRR
0x398 MC_AHB6LPENSETR
0x39c MC_AHB6LPENCLRR
0x400 BR_RSTSCLRR
0x404 MP_GRSTCSETR
0x408 MP_RSTSCLRR
0x40c MP_IWDGFZSETR
0x410 MP_IWDGFZCLRR
0x414 MP_CIER
0x418 MP_CIFR
0x41c PWRLPDLYCR
0x420 MP_RSTSSETR
0x800 MCO1CFGR
0x804 MCO2CFGR
0x808 OCRDYR
0x80c DBGCFGR
0x820 RCK3SELR
0x824 RCK4SELR
0x828 TIMG1PRER
0x82c TIMG2PRER
0x830 MCUDIVR
0x834 APB1DIVR
0x838 APB2DIVR
0x83c APB3DIVR
0x880 PLL3CR
0x884 PLL3CFGR1
0x888 PLL3CFGR2
0x88c PLL3FRACR
0x890 PLL3CSGR
0x894 PLL4CR
0x898 PLL4CFGR1
0x89c PLL4CFGR2
0x8a0 PLL4FRACR
0x8a4 PLL4CSGR
0x8c0 I2C12CKSELR
0x8c4 I2C35CKSELR
0x8c8 SAI1CKSELR
0x8cc SAI2CKSELR
0x8d0 SAI3CKSELR
0x8d4 SAI4CKSELR
0x8d8 SPI2S1CKSELR
0x8dc SPI2S23CKSELR
0x8e0 SPI45CKSELR
0x8e4 UART6CKSELR
0x8e8 UART24CKSELR
0x8ec UART35CKSELR
0x8f0 UART78CKSELR
0x8f4 SDMMC12CKSELR
0x8f8 SDMMC3CKSELR
0x8fc ETHCKSELR
0x900 QSPICKSELR
0x904 FMCCKSELR
0x90c FDCANCKSELR
0x914 SPDIFCKSELR
0x918 CECCKSELR
0x91c USBCKSELR
0x920 RNG2CKSELR
0x924 DSICKSELR
0x928 ADCCKSELR
0x92c LPTIM45CKSELR
0x930 LPTIM23CKSELR
0x934 LPTIM1CKSELR
0x980 APB1RSTSETR
0x984 APB1RSTCLRR
0x988 APB2RSTSETR
0x98c APB2RSTCLRR
0x990 APB3RSTSETR
0x994 APB3RSTCLRR
0x998 AHB2RSTSETR
0x99c AHB2RSTCLRR
0x9a0 AHB3RSTSETR
0x9a4 AHB3RSTCLRR
0x9a8 AHB4RSTSETR
0x9ac AHB4RSTCLRR
0xa00 MP_APB1ENSETR
0xa04 MP_APB1ENCLRR
0xa08 MP_APB2ENSETR
0xa0c MP_APB2ENCLRR
0xa10 MP_APB3ENSETR
0xa14 MP_APB3ENCLRR
0xa18 MP_AHB2ENSETR
0xa1c MP_AHB2ENCLRR
0xa20 MP_AHB3ENSETR
0xa24 MP_AHB3ENCLRR
0xa28 MP_AHB4ENSETR
0xa2c MP_AHB4ENCLRR
0xa38 MP_MLAHBENSETR
0xa3c MP_MLAHBENCLRR
0xa80 MC_APB1ENSETR
0xa84 MC_APB1ENCLRR
0xa88 MC_APB2ENSETR
0xa8c MC_APB2ENCLRR
0xa90 MC_APB3ENSETR
0xa94 MC_APB3ENCLRR
0xa98 MC_AHB2ENSETR
0xa9c MC_AHB2ENCLRR
0xaa0 MC_AHB3ENSETR
0xaa4 MC_AHB3ENCLRR
0xaa8 MC_AHB4ENSETR
0xaac MC_AHB4ENCLRR
0xab0 MC_AXIMENSETR
0xab4 MC_AXIMENCLRR
0xab8 MC_MLAHBENSETR
0xabc MC_MLAHBENCLRR
0xb00 MP_APB1LPENSETR
0xb04 MP_APB1LPENCLRR
0xb08 MP_APB2LPENSETR
0xb0c MP_APB2LPENCLRR
0xb10 MP_APB3LPENSETR
0xb14 MP_APB3LPENCLRR
0xb18 MP_AHB2LPENSETR
0xb1c MP_AHB2LPENCLRR
0xb20 MP_AHB3LPENSETR
0xb24 MP_AHB3LPENCLRR
0xb28 MP_AHB4LPENSETR
0xb2c MP_AHB4LPENCLRR
0xb30 MP_AXIMLPENSETR
0xb34 MP_AXIMLPENCLRR
0xb38 MP_MLAHBLPENSETR
0xb3c MP_MLAHBLPENCLRR
0xb80 MC_APB1LPENSETR
0xb84 MC_APB1LPENCLRR
0xb88 MC_APB2LPENSETR
0xb8c MC_APB2LPENCLRR
0xb90 MC_APB3LPENSETR
0xb94 MC_APB3LPENCLRR
0xb98 MC_AHB2LPENSETR
0xb9c MC_AHB2LPENCLRR
0xba0 MC_AHB3LPENSETR
0xba4 MC_AHB3LPENCLRR
0xba8 MC_AHB4LPENSETR
0xbac MC_AHB4LPENCLRR
0xbb0 MC_AXIMLPENSETR
0xbb4 MC_AXIMLPENCLRR
0xbb8 MC_MLAHBLPENSETR
0xbbc MC_MLAHBLPENCLRR
0xc00 MC_RSTSCLRR
0xc14 MC_CIER
0xc18 MC_CIFR
0xff4 VERR
0xff8 IDR
0xffc SIDR
Toggle registers

TZCR

This register is used to switch the RCC into secure mode. This register can only be accessed in secure mode.

Offset: 0x0, size: 32, reset: 0x00000003, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCKPROT
rw 		TZEN
rw
Toggle fields

TZEN

Bit 0: TZEN.

MCKPROT

Bit 1: MCKPROT.

OCENSETR

This register is used to control the oscillators.Writing to this register has no effect, writing will set the corresponding bits. Reading will give the effective values of each bit.If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0xc, size: 32, reset: 0x00000001, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSECSSON
rw 		HSEBYP
rw 		HSEKERON
rw 		HSEON
rw 		DIGBYP
rw 		CSIKERON
rw 		CSION
rw 		HSIKERON
rw 		HSION
rw
Toggle fields

HSION

Bit 0: HSION.

HSIKERON

Bit 1: HSIKERON.

CSION

Bit 4: CSION.

CSIKERON

Bit 5: CSIKERON.

DIGBYP

Bit 7: DIGBYP.

HSEON

Bit 8: HSEON.

HSEKERON

Bit 9: HSEKERON.

HSEBYP

Bit 10: HSEBYP.

HSECSSON

Bit 11: HSECSSON.

OCENCLRR

This register is used to control the oscillators.Writing to this register has no effect, writing will clear the corresponding bits. Reading will give the effective values of the enable bits.If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x10, size: 32, reset: 0x00000001, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSEBYP
rw 		HSEKERON
rw 		HSEON
rw 		DIGBYP
rw 		CSIKERON
rw 		CSION
rw 		HSIKERON
rw 		HSION
rw
Toggle fields

HSION

Bit 0: HSION.

HSIKERON

Bit 1: HSIKERON.

CSION

Bit 4: CSION.

CSIKERON

Bit 5: CSIKERON.

DIGBYP

Bit 7: DIGBYP.

HSEON

Bit 8: HSEON.

HSEKERON

Bit 9: HSEKERON.

HSEBYP

Bit 10: HSEBYP.

HSICFGR

This register is used to configure the HSI. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSITRIM
rw 		HSIDIV
rw
Toggle fields

HSIDIV

Bits 0-1: HSIDIV.

HSITRIM

Bits 8-14: HSITRIM.

HSICAL

Bits 16-27: HSICAL.

CSICFGR

This register is used to fine-tune the CSI frequency. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See The clock restore sequence description for details.

Offset: 0x1c, size: 32, reset: 0x00001000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSICAL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSITRIM
rw
Toggle fields

CSITRIM

Bits 8-12: CSITRIM.

CSICAL

Bits 16-23: CSICAL.

MPCKSELR

This register is used to select the clock source for the MPU. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x20, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MPUSRCRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUSRC
rw
Toggle fields

MPUSRC

Bits 0-1: MPUSRC.

MPUSRCRDY

Bit 31: MPUSRCRDY.

ASSCKSELR

This register is used to select the clock source for the AXI sub-system. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x24, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXISSRCRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AXISSRC
rw
Toggle fields

AXISSRC

Bits 0-2: AXISSRC.

AXISSRCRDY

Bit 31: AXISSRCRDY.

RCK12SELR

This register is used to select the reference clock for PLL1 and PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x28, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL12SRCRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL12SRC
rw
Toggle fields

PLL12SRC

Bits 0-1: PLL12SRC.

PLL12SRCRDY

Bit 31: PLL12SRCRDY.

MPCKDIVR

This register is used to control the MPU clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.

Offset: 0x2c, size: 32, reset: 0x80000001, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MPUDIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUDIV
rw
Toggle fields

MPUDIV

Bits 0-2: MPUDIV.

MPUDIVRDY

Bit 31: MPUDIVRDY.

AXIDIVR

This register is used to control the AXI Matrix clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.

Offset: 0x30, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXIDIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AXIDIV
rw
Toggle fields

AXIDIV

Bits 0-2: AXIDIV.

AXIDIVRDY

Bit 31: AXIDIVRDY.

APB4DIVR

This register is used to control the APB4 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.

Offset: 0x3c, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APB4DIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB4DIV
rw
Toggle fields

APB4DIV

Bits 0-2: APB4DIV.

APB4DIVRDY

Bit 31: APB4DIVRDY.

APB5DIVR

This register is used to control the APB5 clock divider. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.

Offset: 0x40, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APB5DIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB5DIV
rw
Toggle fields

APB5DIV

Bits 0-2: APB5DIV.

APB5DIVRDY

Bit 31: APB5DIVRDY.

RTCDIVR

This register is used to divide the HSE clock for RTC. If TZEN = , this register can only be modified in secure mode.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCDIV
rw
Toggle fields

RTCDIV

Bits 0-5: RTCDIV.

MSSCKSELR

This register is used to select the clock source for the MCU sub-system, including the MCU itself. If TZEN = MCKPROT = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x48, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCUSSRCRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCUSSRC
rw
Toggle fields

MCUSSRC

Bits 0-1: MCUSSRC.

MCUSSRCRDY

Bit 31: MCUSSRCRDY.

PLL1CR

This register is used to control the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x80, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVREN
rw 		DIVQEN
rw 		DIVPEN
rw 		SSCG_CTRL
rw 		PLL1RDY
r 		PLLON
rw
Toggle fields

PLLON

Bit 0: PLLON.

PLL1RDY

Bit 1: PLL1RDY.

SSCG_CTRL

Bit 2: SSCG_CTRL.

DIVPEN

Bit 4: DIVPEN.

DIVQEN

Bit 5: DIVQEN.

DIVREN

Bit 6: DIVREN.

PLL1CFGR1

This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x84, size: 32, reset: 0x00010031, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVM1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVN
rw
Toggle fields

DIVN

Bits 0-8: DIVN.

DIVM1

Bits 16-21: DIVM1.

PLL1CFGR2

This register is used to configure the PLL1. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x88, size: 32, reset: 0x00010100, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVQ
rw 		DIVP
rw
Toggle fields

DIVP

Bits 0-6: DIVP.

DIVQ

Bits 8-14: DIVQ.

DIVR

Bits 16-22: DIVR.

PLL1FRACR

This register is used to fine-tune the frequency of the PLL1 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRACLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACV
rw
Toggle fields

FRACV

Bits 3-15: FRACV.

FRACLE

Bit 16: FRACLE.

PLL1CSGR

This register is used to configure the PLL1.It is not recommended to change the content of this register when the PLL1 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INC_STEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSCG_MODE
rw 		RPDFN_DIS
rw 		TPDFN_DIS
rw 		MOD_PER
rw
Toggle fields

MOD_PER

Bits 0-12: MOD_PER.

TPDFN_DIS

Bit 13: TPDFN_DIS.

RPDFN_DIS

Bit 14: RPDFN_DIS.

SSCG_MODE

Bit 15: SSCG_MODE.

INC_STEP

Bits 16-30: INC_STEP.

PLL2CR

This register is used to control the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x94, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVREN
rw 		DIVQEN
rw 		DIVPEN
rw 		SSCG_CTRL
rw 		PLL2RDY
r 		PLLON
rw
Toggle fields

PLLON

Bit 0: PLLON.

PLL2RDY

Bit 1: PLL2RDY.

SSCG_CTRL

Bit 2: SSCG_CTRL.

DIVPEN

Bit 4: DIVPEN.

DIVQEN

Bit 5: DIVQEN.

DIVREN

Bit 6: DIVREN.

PLL2CFGR1

This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x98, size: 32, reset: 0x00010063, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVM2
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVN
rw
Toggle fields

DIVN

Bits 0-8: DIVN.

DIVM2

Bits 16-21: DIVM2.

PLL2CFGR2

This register is used to configure the PLL2. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0x9c, size: 32, reset: 0x00010101, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVQ
rw 		DIVP
rw
Toggle fields

DIVP

Bits 0-6: DIVP.

DIVQ

Bits 8-14: DIVQ.

DIVR

Bits 16-22: DIVR.

PLL2FRACR

This register is used to fine-tune the frequency of the PLL2 VCO. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRACLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACV
rw
Toggle fields

FRACV

Bits 3-15: FRACV.

FRACLE

Bit 16: FRACLE.

PLL2CSGR

This register is used to configure the PLL2. It is not recommended to change the content of this register when the PLL2 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = , this register can only be modified in secure mode. Write access to this register is not allowed during the clock restore sequence. See Section: The clock restore sequence description for details.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INC_STEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSCG_MODE
rw 		RPDFN_DIS
rw 		TPDFN_DIS
rw 		MOD_PER
rw
Toggle fields

MOD_PER

Bits 0-12: MOD_PER.

TPDFN_DIS

Bit 13: TPDFN_DIS.

RPDFN_DIS

Bit 14: RPDFN_DIS.

SSCG_MODE

Bit 15: SSCG_MODE.

INC_STEP

Bits 16-30: INC_STEP.

I2C46CKSELR

This register is used to control the selection of the kernel clock for the I2C4 and I2C6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.

Offset: 0xc0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C46SRC
rw
Toggle fields

I2C46SRC

Bits 0-2: I2C46SRC.

SPI6CKSELR

This register is used to control the selection of the kernel clock for the SPI6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.

Offset: 0xc4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI6SRC
rw
Toggle fields

SPI6SRC

Bits 0-2: SPI6SRC.

UART1CKSELR

This register is used to control the selection of the kernel clock for the USART1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.

Offset: 0xc8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UART1SRC
rw
Toggle fields

UART1SRC

Bits 0-2: UART1SRC.

RNG1CKSELR

This register is used to control the selection of the kernel clock for the RNG1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.

Offset: 0xcc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG1SRC
rw
Toggle fields

RNG1SRC

Bits 0-1: RNG1SRC.

CPERCKSELR

This register is used to select an oscillator source as kernel clock for the per_ck clock. The per_ck clock is distributed to several peripherals. Refer to Section: Clock enabling delays.

Offset: 0xd0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKPERSRC
rw
Toggle fields

CKPERSRC

Bits 0-1: CKPERSRC.

STGENCKSELR

This register is used to select the peripheral clock for the STGEN block. Note that this clock is used to provide a time reference for the application. Refer to Section: Clock enabling delays. If TZEN = , this register can only be modified in secure mode.

Offset: 0xd4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STGENSRC
rw
Toggle fields

STGENSRC

Bits 0-1: STGENSRC.

DDRITFCR

This register is used to control the DDR interface, including the DDRC and DDRPHYC. If TZEN = , this register can only be modified in secure mode.

Offset: 0xd8, size: 32, reset: 0x000FD02A, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GSKP_DUR
rw 		DFILP_WIDTH
rw 		GSKPCTRL
rw 		GSKPMOD
rw 		DDRCKMOD
rw 		DPHYCTLRST
rw 		DPHYRST
rw 		DPHYAPBRST
rw 		DDRCORERST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRCAXIRST
rw 		DDRCAPBRST
rw 		KERDCG_DLY
rw 		DDRPHYCAPBLPEN
rw 		DDRPHYCAPBEN
rw 		AXIDCGEN
rw 		DDRCAPBLPEN
rw 		DDRCAPBEN
rw 		DDRPHYCLPEN
rw 		DDRPHYCEN
rw 		DDRC2LPEN
rw 		DDRC2EN
rw 		DDRC1LPEN
rw 		DDRC1EN
rw
Toggle fields

DDRC1EN

Bit 0: DDRC1EN.

DDRC1LPEN

Bit 1: DDRC1LPEN.

DDRC2EN

Bit 2: DDRC2EN.

DDRC2LPEN

Bit 3: DDRC2LPEN.

DDRPHYCEN

Bit 4: DDRPHYCEN.

DDRPHYCLPEN

Bit 5: DDRPHYCLPEN.

DDRCAPBEN

Bit 6: DDRCAPBEN.

DDRCAPBLPEN

Bit 7: DDRCAPBLPEN.

AXIDCGEN

Bit 8: AXIDCGEN.

DDRPHYCAPBEN

Bit 9: DDRPHYCAPBEN.

DDRPHYCAPBLPEN

Bit 10: DDRPHYCAPBLPEN.

KERDCG_DLY

Bits 11-13: KERDCG_DLY.

DDRCAPBRST

Bit 14: DDRCAPBRST.

DDRCAXIRST

Bit 15: DDRCAXIRST.

DDRCORERST

Bit 16: DDRCORERST.

DPHYAPBRST

Bit 17: DPHYAPBRST.

DPHYRST

Bit 18: DPHYRST.

DPHYCTLRST

Bit 19: DPHYCTLRST.

DDRCKMOD

Bits 20-22: DDRCKMOD.

GSKPMOD

Bit 23: GSKPMOD.

GSKPCTRL

Bit 24: GSKPCTRL.

DFILP_WIDTH

Bits 25-27: DFILP_WIDTH.

GSKP_DUR

Bits 28-31: GSKP_DUR.

MP_BOOTCR

This register is used to control the HOLD boot function when the system exits from Standby. Refer to Section: MCU HOLD_BOOT after processor reset. This register is reset when a system reset occurs, but not when the circuit exits from Standby (app_rst reset).If TZEN = , this register can only be modified in secure mode. This register can only be accessed by the MPU.

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPU_BEN
rw 		MCU_BEN
rw
Toggle fields

MCU_BEN

Bit 0: MCU_BEN.

MPU_BEN

Bit 1: MPU_BEN.

MP_SREQSETR

Writing has no effect, reading will return the values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPREQ_P1
rw 		STPREQ_P0
rw
Toggle fields

STPREQ_P0

Bit 0: STPREQ_P0.

STPREQ_P1

Bit 1: STPREQ_P1.

MP_SREQCLRR

Writing has no effect, reading will return the effective values of the bits. Writing a sets the corresponding bit to . The MCU cannot access to this register. If TZEN = , this register can only be modified in secure mode.

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STPREQ_P1
rw 		STPREQ_P0
rw
Toggle fields

STPREQ_P0

Bit 0: STPREQ_P0.

STPREQ_P1

Bit 1: STPREQ_P1.

MP_GCR

The register contains global control bits. If TZEN = , this register can only be modified in secure mode.

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_MCU
rw
Toggle fields

BOOT_MCU

Bit 0: BOOT_MCU.

MP_APRSTCR

This register is used to control the behavior of the warm reset. If TZEN = , this register can only be modified in secure mode.

Offset: 0x110, size: 32, reset: 0x00007F00, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTTO
rw 		RDCTLEN
rw
Toggle fields

RDCTLEN

Bit 0: RDCTLEN.

RSTTO

Bits 8-14: RSTTO.

MP_APRSTSR

This register provides a status of the RDCTL. If TZEN = , this register can only be modified in secure mode.

Offset: 0x114, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSTTOV
r
Toggle fields

RSTTOV

Bits 8-14: RSTTOV.

BDCR

This register is used to control the LSE function. Wait states are inserted in case of successive write accesses to this register. The number of wait states may be up to 7 cycles of AHB4 clock.After a system reset, the register RCC_BDCR is write-protected. In order to modify this register, the DBP bit in the PWR control register 1 (PWR_CR1) has to be set to . Bits of RCC_BDCR register are only reset after a backup domain reset: nreset_vsw (see Section10.3.6: Backup domain reset). Any other internal or external reset will not have any effect on these bits.This register is located into the VSW domain. If TZEN = , this register can only be modified in secure mode.

Offset: 0x140, size: 32, reset: 0x00000020, access: Unspecified

3/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VSWRST
rw 		RTCCKEN
rw 		RTCSRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSECSSD
r 		LSECSSON
rw 		LSEDRV
rw 		DIGBYP
rw 		LSERDY
r 		LSEBYP
rw 		LSEON
rw
Toggle fields

LSEON

Bit 0: LSEON.

LSEBYP

Bit 1: LSEBYP.

LSERDY

Bit 2: LSERDY.

DIGBYP

Bit 3: DIGBYP.

LSEDRV

Bits 4-5: LSEDRV.

LSECSSON

Bit 8: LSECSSON.

LSECSSD

Bit 9: LSECSSD.

RTCSRC

Bits 16-17: RTCSRC.

RTCCKEN

Bit 20: RTCCKEN.

VSWRST

Bit 31: VSWRST.

RDLSICR

This register is used to control the minimum NRST active duration and LSI function.0 to 7 wait states are inserted for word, half-word and byte accesses. Wait states are inserted in case of successive accesses to this register.This register is reset by the por_rst reset, and it is located into the VDD domain. If TZEN = , this register can only be modified in secure mode.

Offset: 0x144, size: 32, reset: 0x00000000, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPARE
rw 		EADLY
rw 		MRD
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIRDY
r 		LSION
rw
Toggle fields

LSION

Bit 0: LSION.

LSIRDY

Bit 1: LSIRDY.

MRD

Bits 16-20: MRD.

EADLY

Bits 24-26: EADLY.

SPARE

Bits 27-31: SPARE.

APB4RSTSETR

This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBPHYRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRPERFMRST
rw 		DSIRST
rw 		LTDCRST
rw
Toggle fields

LTDCRST

Bit 0: LTDCRST.

DSIRST

Bit 4: DSIRST.

DDRPERFMRST

Bit 8: DDRPERFMRST.

USBPHYRST

Bit 16: USBPHYRST.

APB4RSTCLRR

This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.

Offset: 0x184, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBPHYRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRPERFMRST
rw 		DSIRST
rw 		LTDCRST
rw
Toggle fields

LTDCRST

Bit 0: LTDCRST.

DSIRST

Bit 4: DSIRST.

DDRPERFMRST

Bit 8: DDRPERFMRST.

USBPHYRST

Bit 16: USBPHYRST.

APB5RSTSETR

This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.

Offset: 0x188, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		I2C6RST
rw 		I2C4RST
rw 		SPI6RST
rw
Toggle fields

SPI6RST

Bit 0: SPI6RST.

I2C4RST

Bit 2: I2C4RST.

I2C6RST

Bit 3: I2C6RST.

USART1RST

Bit 4: USART1RST.

STGENRST

Bit 20: STGENRST.

APB5RSTCLRR

This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1RST
rw 		I2C6RST
rw 		I2C4RST
rw 		SPI6RST
rw
Toggle fields

SPI6RST

Bit 0: SPI6RST.

I2C4RST

Bit 2: I2C4RST.

I2C6RST

Bit 3: I2C6RST.

USART1RST

Bit 4: USART1RST.

STGENRST

Bit 20: STGENRST.

AHB5RSTSETR

This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXIMCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG1RST
rw 		HASH1RST
rw 		CRYP1RST
rw 		GPIOZRST
rw
Toggle fields

GPIOZRST

Bit 0: GPIOZRST.

CRYP1RST

Bit 4: CRYP1RST.

HASH1RST

Bit 5: HASH1RST.

RNG1RST

Bit 6: RNG1RST.

AXIMCRST

Bit 16: AXIMCRST.

AHB5RSTCLRR

This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXIMCRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG1RST
rw 		HASH1RST
rw 		CRYP1RST
rw 		GPIOZRST
rw
Toggle fields

GPIOZRST

Bit 0: GPIOZRST.

CRYP1RST

Bit 4: CRYP1RST.

HASH1RST

Bit 5: HASH1RST.

RNG1RST

Bit 6: RNG1RST.

AXIMCRST

Bit 16: AXIMCRST.

AHB6RSTSETR

This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral.

Offset: 0x198, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHRST
rw 		CRC1RST
rw 		SDMMC2RST
rw 		SDMMC1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIRST
rw 		FMCRST
rw 		ETHMACRST
rw 		GPURST
rw
Toggle fields

GPURST

Bit 5: GPURST.

ETHMACRST

Bit 10: ETHMACRST.

FMCRST

Bit 12: FMCRST.

QSPIRST

Bit 14: QSPIRST.

SDMMC1RST

Bit 16: SDMMC1RST.

SDMMC2RST

Bit 17: SDMMC2RST.

CRC1RST

Bit 20: CRC1RST.

USBHRST

Bit 24: USBHRST.

AHB6RSTCLRR

This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral.

Offset: 0x19c, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHRST
rw 		CRC1RST
rw 		SDMMC2RST
rw 		SDMMC1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIRST
rw 		FMCRST
rw 		ETHMACRST
rw
Toggle fields

ETHMACRST

Bit 10: ETHMACRST.

FMCRST

Bit 12: FMCRST.

QSPIRST

Bit 14: QSPIRST.

SDMMC1RST

Bit 16: SDMMC1RST.

SDMMC2RST

Bit 17: SDMMC2RST.

CRC1RST

Bit 20: CRC1RST.

USBHRST

Bit 24: USBHRST.

TZAHB6RSTSETR

This register is used to activate the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a activates the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMARST
rw
Toggle fields

MDMARST

Bit 0: MDMARST.

TZAHB6RSTCLRR

This register is used to release the reset of the corresponding peripheral. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a releases the reset of the corresponding peripheral. If TZEN = , this register can only be modified in secure mode.

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMARST
rw
Toggle fields

MDMARST

Bit 0: MDMARST.

MP_APB4ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROEN
rw 		USBPHYEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG2APBEN
rw 		DDRPERFMEN
rw 		DSIEN
rw 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LTDCEN.

DSIEN

Bit 4: DSIEN.

DDRPERFMEN

Bit 8: DDRPERFMEN.

IWDG2APBEN

Bit 15: IWDG2APBEN.

USBPHYEN

Bit 16: USBPHYEN.

STGENROEN

Bit 20: STGENROEN.

MP_APB4ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .

Offset: 0x204, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROEN
rw 		USBPHYEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG2APBEN
rw 		DDRPERFMEN
rw 		DSIEN
rw 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LTDCEN.

DSIEN

Bit 4: DSIEN.

DDRPERFMEN

Bit 8: DDRPERFMEN.

IWDG2APBEN

Bit 15: IWDG2APBEN.

USBPHYEN

Bit 16: USBPHYEN.

STGENROEN

Bit 20: STGENROEN.

MP_APB5ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .

Offset: 0x208, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENEN
rw 		BSECEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG1APBEN
rw 		TZPCEN
rw 		TZC2EN
rw 		TZC1EN
rw 		RTCAPBEN
rw 		USART1EN
rw 		I2C6EN
rw 		I2C4EN
rw 		SPI6EN
rw
Toggle fields

SPI6EN

Bit 0: SPI6EN.

I2C4EN

Bit 2: I2C4EN.

I2C6EN

Bit 3: I2C6EN.

USART1EN

Bit 4: USART1EN.

RTCAPBEN

Bit 8: RTCAPBEN.

TZC1EN

Bit 11: TZC1EN.

TZC2EN

Bit 12: TZC2EN.

TZPCEN

Bit 13: TZPCEN.

IWDG1APBEN

Bit 15: IWDG1APBEN.

BSECEN

Bit 16: BSECEN.

STGENEN

Bit 20: STGENEN.

MP_APB5ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .

Offset: 0x20c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENEN
rw 		BSECEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG1APBEN
rw 		TZPCEN
rw 		TZC2EN
rw 		TZC1EN
rw 		RTCAPBEN
rw 		USART1EN
rw 		I2C6EN
rw 		I2C4EN
rw 		SPI6EN
rw
Toggle fields

SPI6EN

Bit 0: SPI6EN.

I2C4EN

Bit 2: I2C4EN.

I2C6EN

Bit 3: I2C6EN.

USART1EN

Bit 4: USART1EN.

RTCAPBEN

Bit 8: RTCAPBEN.

TZC1EN

Bit 11: TZC1EN.

TZC2EN

Bit 12: TZC2EN.

TZPCEN

Bit 13: TZPCEN.

IWDG1APBEN

Bit 15: IWDG1APBEN.

BSECEN

Bit 16: BSECEN.

STGENEN

Bit 20: STGENEN.

MP_AHB5ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.

Offset: 0x210, size: 32, reset: 0x00010000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXIMCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMEN
rw 		RNG1EN
rw 		HASH1EN
rw 		CRYP1EN
rw 		GPIOZEN
rw
Toggle fields

GPIOZEN

Bit 0: GPIOZEN.

CRYP1EN

Bit 4: CRYP1EN.

HASH1EN

Bit 5: HASH1EN.

RNG1EN

Bit 6: RNG1EN.

BKPSRAMEN

Bit 8: BKPSRAMEN.

AXIMCEN

Bit 16: AXIMCEN.

MP_AHB5ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.

Offset: 0x214, size: 32, reset: 0x00010000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AXIMCEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMEN
rw 		RNG1EN
rw 		HASH1EN
rw 		CRYP1EN
rw 		GPIOZEN
rw
Toggle fields

GPIOZEN

Bit 0: GPIOZEN.

CRYP1EN

Bit 4: CRYP1EN.

HASH1EN

Bit 5: HASH1EN.

RNG1EN

Bit 6: RNG1EN.

BKPSRAMEN

Bit 8: BKPSRAMEN.

AXIMCEN

Bit 16: AXIMCEN.

MP_AHB6ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .

Offset: 0x218, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHEN
rw 		CRC1EN
rw 		SDMMC2EN
rw 		SDMMC1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIEN
rw 		FMCEN
rw 		ETHMACEN
rw 		ETHRXEN
rw 		ETHTXEN
rw 		ETHCKEN
rw 		GPUEN
rw 		MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMAEN.

GPUEN

Bit 5: GPUEN.

ETHCKEN

Bit 7: ETHCKEN.

ETHTXEN

Bit 8: ETHTXEN.

ETHRXEN

Bit 9: ETHRXEN.

ETHMACEN

Bit 10: ETHMACEN.

FMCEN

Bit 12: FMCEN.

QSPIEN

Bit 14: QSPIEN.

SDMMC1EN

Bit 16: SDMMC1EN.

SDMMC2EN

Bit 17: SDMMC2EN.

CRC1EN

Bit 20: CRC1EN.

USBHEN

Bit 24: USBHEN.

MP_AHB6ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .

Offset: 0x21c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHEN
rw 		CRC1EN
rw 		SDMMC2EN
rw 		SDMMC1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIEN
rw 		FMCEN
rw 		ETHMACEN
rw 		ETHRXEN
rw 		ETHTXEN
rw 		ETHCKEN
rw 		GPUEN
rw 		MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMAEN.

GPUEN

Bit 5: GPUEN.

ETHCKEN

Bit 7: ETHCKEN.

ETHTXEN

Bit 8: ETHTXEN.

ETHRXEN

Bit 9: ETHRXEN.

ETHMACEN

Bit 10: ETHMACEN.

FMCEN

Bit 12: FMCEN.

QSPIEN

Bit 14: QSPIEN.

SDMMC1EN

Bit 16: SDMMC1EN.

SDMMC2EN

Bit 17: SDMMC2EN.

CRC1EN

Bit 20: CRC1EN.

USBHEN

Bit 24: USBHEN.

MP_TZAHB6ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.

Offset: 0x220, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMAEN.

MP_TZAHB6ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral. It shall be used to deallocate a peripheral from MPU. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.

Offset: 0x224, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMAEN.

MC_APB4ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0x280, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROEN
rw 		USBPHYEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRPERFMEN
rw 		DSIEN
rw 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LTDCEN.

DSIEN

Bit 4: DSIEN.

DDRPERFMEN

Bit 8: DDRPERFMEN.

USBPHYEN

Bit 16: USBPHYEN.

STGENROEN

Bit 20: STGENROEN.

MC_APB4ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0x284, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROEN
rw 		USBPHYEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRPERFMEN
rw 		DSIEN
rw 		LTDCEN
rw
Toggle fields

LTDCEN

Bit 0: LTDCEN.

DSIEN

Bit 4: DSIEN.

DDRPERFMEN

Bit 8: DDRPERFMEN.

USBPHYEN

Bit 16: USBPHYEN.

STGENROEN

Bit 20: STGENROEN.

MC_APB5ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0x288, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENEN
rw 		BSECEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZPCEN
rw 		TZC2EN
rw 		TZC1EN
rw 		RTCAPBEN
rw 		USART1EN
rw 		I2C6EN
rw 		I2C4EN
rw 		SPI6EN
rw
Toggle fields

SPI6EN

Bit 0: SPI6EN.

I2C4EN

Bit 2: I2C4EN.

I2C6EN

Bit 3: I2C6EN.

USART1EN

Bit 4: USART1EN.

RTCAPBEN

Bit 8: RTCAPBEN.

TZC1EN

Bit 11: TZC1EN.

TZC2EN

Bit 12: TZC2EN.

TZPCEN

Bit 13: TZPCEN.

BSECEN

Bit 16: BSECEN.

STGENEN

Bit 20: STGENEN.

MC_APB5ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0x28c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENEN
rw 		BSECEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZPCEN
rw 		TZC2EN
rw 		TZC1EN
rw 		RTCAPBEN
rw 		USART1EN
rw 		I2C6EN
rw 		I2C4EN
rw 		SPI6EN
rw
Toggle fields

SPI6EN

Bit 0: SPI6EN.

I2C4EN

Bit 2: I2C4EN.

I2C6EN

Bit 3: I2C6EN.

USART1EN

Bit 4: USART1EN.

RTCAPBEN

Bit 8: RTCAPBEN.

TZC1EN

Bit 11: TZC1EN.

TZC2EN

Bit 12: TZC2EN.

TZPCEN

Bit 13: TZPCEN.

BSECEN

Bit 16: BSECEN.

STGENEN

Bit 20: STGENEN.

MC_AHB5ENSETR

This register is used to set the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.

Offset: 0x290, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMEN
rw 		RNG1EN
rw 		HASH1EN
rw 		CRYP1EN
rw 		GPIOZEN
rw
Toggle fields

GPIOZEN

Bit 0: GPIOZEN.

CRYP1EN

Bit 4: CRYP1EN.

HASH1EN

Bit 5: HASH1EN.

RNG1EN

Bit 6: RNG1EN.

BKPSRAMEN

Bit 8: BKPSRAMEN.

MC_AHB5ENCLRR

This register is used to clear the peripheral clock enable bit If TZEN = , this register can only be modified in secure mode.

Offset: 0x294, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMEN
rw 		RNG1EN
rw 		HASH1EN
rw 		CRYP1EN
rw 		GPIOZEN
rw
Toggle fields

GPIOZEN

Bit 0: GPIOZEN.

CRYP1EN

Bit 4: CRYP1EN.

HASH1EN

Bit 5: HASH1EN.

RNG1EN

Bit 6: RNG1EN.

BKPSRAMEN

Bit 8: BKPSRAMEN.

MC_AHB6ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0x298, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHEN
rw 		CRC1EN
rw 		SDMMC2EN
rw 		SDMMC1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIEN
rw 		FMCEN
rw 		ETHMACEN
rw 		ETHRXEN
rw 		ETHTXEN
rw 		ETHCKEN
rw 		GPUEN
rw 		MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMAEN.

GPUEN

Bit 5: GPUEN.

ETHCKEN

Bit 7: ETHCKEN.

ETHTXEN

Bit 8: ETHTXEN.

ETHRXEN

Bit 9: ETHRXEN.

ETHMACEN

Bit 10: ETHMACEN.

FMCEN

Bit 12: FMCEN.

QSPIEN

Bit 14: QSPIEN.

SDMMC1EN

Bit 16: SDMMC1EN.

SDMMC2EN

Bit 17: SDMMC2EN.

CRC1EN

Bit 20: CRC1EN.

USBHEN

Bit 24: USBHEN.

MC_AHB6ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0x29c, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHEN
rw 		CRC1EN
rw 		SDMMC2EN
rw 		SDMMC1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPIEN
rw 		FMCEN
rw 		ETHMACEN
rw 		ETHRXEN
rw 		ETHTXEN
rw 		ETHCKEN
rw 		GPUEN
rw 		MDMAEN
rw
Toggle fields

MDMAEN

Bit 0: MDMAEN.

GPUEN

Bit 5: GPUEN.

ETHCKEN

Bit 7: ETHCKEN.

ETHTXEN

Bit 8: ETHTXEN.

ETHRXEN

Bit 9: ETHRXEN.

ETHMACEN

Bit 10: ETHMACEN.

FMCEN

Bit 12: FMCEN.

QSPIEN

Bit 14: QSPIEN.

SDMMC1EN

Bit 16: SDMMC1EN.

SDMMC2EN

Bit 17: SDMMC2EN.

CRC1EN

Bit 20: CRC1EN.

USBHEN

Bit 24: USBHEN.

MP_APB4LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0x300, size: 32, reset: 0x00118111, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROSTPEN
rw 		STGENROLPEN
rw 		USBPHYLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG2APBLPEN
rw 		DDRPERFMLPEN
rw 		DSILPEN
rw 		LTDCLPEN
rw
Toggle fields

LTDCLPEN

Bit 0: LTDCLPEN.

DSILPEN

Bit 4: DSILPEN.

DDRPERFMLPEN

Bit 8: DDRPERFMLPEN.

IWDG2APBLPEN

Bit 15: IWDG2APBLPEN.

USBPHYLPEN

Bit 16: USBPHYLPEN.

STGENROLPEN

Bit 20: STGENROLPEN.

STGENROSTPEN

Bit 21: STGENROSTPEN.

MP_APB4LPENCLRR

This register is used by the MCU

Offset: 0x304, size: 32, reset: 0x00118111, access: read-write

0/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROSTPEN
rw 		STGENROLPEN
rw 		USBPHYLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG2APBLPEN
rw 		DDRPERFMLPEN
rw 		DSILPEN
rw 		LTDCLPEN
rw
Toggle fields

LTDCLPEN

Bit 0: LTDCLPEN.

DSILPEN

Bit 4: DSILPEN.

DDRPERFMLPEN

Bit 8: DDRPERFMLPEN.

IWDG2APBLPEN

Bit 15: IWDG2APBLPEN.

USBPHYLPEN

Bit 16: USBPHYLPEN.

STGENROLPEN

Bit 20: STGENROLPEN.

STGENROSTPEN

Bit 21: STGENROSTPEN.

MP_APB5LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.

Offset: 0x308, size: 32, reset: 0x0011391D, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENSTPEN
rw 		STGENLPEN
rw 		BSECLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG1APBLPEN
rw 		TZPCLPEN
rw 		TZC2LPEN
rw 		TZC1LPEN
rw 		RTCAPBLPEN
rw 		USART1LPEN
rw 		I2C6LPEN
rw 		I2C4LPEN
rw 		SPI6LPEN
rw
Toggle fields

SPI6LPEN

Bit 0: SPI6LPEN.

I2C4LPEN

Bit 2: I2C4LPEN.

I2C6LPEN

Bit 3: I2C6LPEN.

USART1LPEN

Bit 4: USART1LPEN.

RTCAPBLPEN

Bit 8: RTCAPBLPEN.

TZC1LPEN

Bit 11: TZC1LPEN.

TZC2LPEN

Bit 12: TZC2LPEN.

TZPCLPEN

Bit 13: TZPCLPEN.

IWDG1APBLPEN

Bit 15: IWDG1APBLPEN.

BSECLPEN

Bit 16: BSECLPEN.

STGENLPEN

Bit 20: STGENLPEN.

STGENSTPEN

Bit 21: STGENSTPEN.

MP_APB5LPENCLRR

This register is used by the Mpu.

Offset: 0x30c, size: 32, reset: 0x0011391D, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENSTPEN
rw 		STGENLPEN
rw 		BSECLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IWDG1APBLPEN
rw 		TZPCLPEN
rw 		TZC2LPEN
rw 		TZC1LPEN
rw 		RTCAPBLPEN
rw 		USART1LPEN
rw 		I2C6LPEN
rw 		I2C4LPEN
rw 		SPI6LPEN
rw
Toggle fields

SPI6LPEN

Bit 0: SPI6LPEN.

I2C4LPEN

Bit 2: I2C4LPEN.

I2C6LPEN

Bit 3: I2C6LPEN.

USART1LPEN

Bit 4: USART1LPEN.

RTCAPBLPEN

Bit 8: RTCAPBLPEN.

TZC1LPEN

Bit 11: TZC1LPEN.

TZC2LPEN

Bit 12: TZC2LPEN.

TZPCLPEN

Bit 13: TZPCLPEN.

IWDG1APBLPEN

Bit 15: IWDG1APBLPEN.

BSECLPEN

Bit 16: BSECLPEN.

STGENLPEN

Bit 20: STGENLPEN.

STGENSTPEN

Bit 21: STGENSTPEN.

MP_AHB5LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.

Offset: 0x310, size: 32, reset: 0x00000171, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMLPEN
rw 		RNG1LPEN
rw 		HASH1LPEN
rw 		CRYP1LPEN
rw 		GPIOZLPEN
rw
Toggle fields

GPIOZLPEN

Bit 0: GPIOZLPEN.

CRYP1LPEN

Bit 4: CRYP1LPEN.

HASH1LPEN

Bit 5: HASH1LPEN.

RNG1LPEN

Bit 6: RNG1LPEN.

BKPSRAMLPEN

Bit 8: BKPSRAMLPEN.

MP_AHB5LPENCLRR

This register is used by the MCU

Offset: 0x314, size: 32, reset: 0x00000171, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMLPEN
rw 		RNG1LPEN
rw 		HASH1LPEN
rw 		CRYP1LPEN
rw 		GPIOZLPEN
rw
Toggle fields

GPIOZLPEN

Bit 0: GPIOZLPEN.

CRYP1LPEN

Bit 4: CRYP1LPEN.

HASH1LPEN

Bit 5: HASH1LPEN.

RNG1LPEN

Bit 6: RNG1LPEN.

BKPSRAMLPEN

Bit 8: BKPSRAMLPEN.

MP_AHB6LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0x318, size: 32, reset: 0x011357A1, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHLPEN
rw 		CRC1LPEN
rw 		SDMMC2LPEN
rw 		SDMMC1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPILPEN
rw 		FMCLPEN
rw 		ETHSTPEN
rw 		ETHMACLPEN
rw 		ETHRXLPEN
rw 		ETHTXLPEN
rw 		ETHCKLPEN
rw 		GPULPEN
rw 		MDMALPEN
rw
Toggle fields

MDMALPEN

Bit 0: MDMALPEN.

GPULPEN

Bit 5: GPULPEN.

ETHCKLPEN

Bit 7: ETHCKLPEN.

ETHTXLPEN

Bit 8: ETHTXLPEN.

ETHRXLPEN

Bit 9: ETHRXLPEN.

ETHMACLPEN

Bit 10: ETHMACLPEN.

ETHSTPEN

Bit 11: ETHSTPEN.

FMCLPEN

Bit 12: FMCLPEN.

QSPILPEN

Bit 14: QSPILPEN.

SDMMC1LPEN

Bit 16: SDMMC1LPEN.

SDMMC2LPEN

Bit 17: SDMMC2LPEN.

CRC1LPEN

Bit 20: CRC1LPEN.

USBHLPEN

Bit 24: USBHLPEN.

MP_AHB6LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0x31c, size: 32, reset: 0x011357A1, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHLPEN
rw 		CRC1LPEN
rw 		SDMMC2LPEN
rw 		SDMMC1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPILPEN
rw 		FMCLPEN
rw 		ETHSTPEN
rw 		ETHMACLPEN
rw 		ETHRXLPEN
rw 		ETHTXLPEN
rw 		ETHCKLPEN
rw 		GPULPEN
rw 		MDMALPEN
rw
Toggle fields

MDMALPEN

Bit 0: MDMALPEN.

GPULPEN

Bit 5: GPULPEN.

ETHCKLPEN

Bit 7: ETHCKLPEN.

ETHTXLPEN

Bit 8: ETHTXLPEN.

ETHRXLPEN

Bit 9: ETHRXLPEN.

ETHMACLPEN

Bit 10: ETHMACLPEN.

ETHSTPEN

Bit 11: ETHSTPEN.

FMCLPEN

Bit 12: FMCLPEN.

QSPILPEN

Bit 14: QSPILPEN.

SDMMC1LPEN

Bit 16: SDMMC1LPEN.

SDMMC2LPEN

Bit 17: SDMMC2LPEN.

CRC1LPEN

Bit 20: CRC1LPEN.

USBHLPEN

Bit 24: USBHLPEN.

MP_TZAHB6LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.

Offset: 0x320, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMALPEN
rw
Toggle fields

MDMALPEN

Bit 0: MDMALPEN.

MP_TZAHB6LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bits If TZEN = , this register can only be modified in secure mode.

Offset: 0x324, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDMALPEN
rw
Toggle fields

MDMALPEN

Bit 0: MDMALPEN.

MC_APB4LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0x380, size: 32, reset: 0x00110111, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROSTPEN
rw 		STGENROLPEN
rw 		USBPHYLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRPERFMLPEN
rw 		DSILPEN
rw 		LTDCLPEN
rw
Toggle fields

LTDCLPEN

Bit 0: LTDCLPEN.

DSILPEN

Bit 4: DSILPEN.

DDRPERFMLPEN

Bit 8: DDRPERFMLPEN.

USBPHYLPEN

Bit 16: USBPHYLPEN.

STGENROLPEN

Bit 20: STGENROLPEN.

STGENROSTPEN

Bit 21: STGENROSTPEN.

MC_APB4LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0x384, size: 32, reset: 0x00110111, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENROSTPEN
rw 		STGENROLPEN
rw 		USBPHYLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRPERFMLPEN
rw 		DSILPEN
rw 		LTDCLPEN
rw
Toggle fields

LTDCLPEN

Bit 0: LTDCLPEN.

DSILPEN

Bit 4: DSILPEN.

DDRPERFMLPEN

Bit 8: DDRPERFMLPEN.

USBPHYLPEN

Bit 16: USBPHYLPEN.

STGENROLPEN

Bit 20: STGENROLPEN.

STGENROSTPEN

Bit 21: STGENROSTPEN.

MC_APB5LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0x388, size: 32, reset: 0x0011391D, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENSTPEN
rw 		STGENLPEN
rw 		BSECLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZPCLPEN
rw 		TZC2LPEN
rw 		TZC1LPEN
rw 		RTCAPBLPEN
rw 		USART1LPEN
rw 		I2C6LPEN
rw 		I2C4LPEN
rw 		SPI6LPEN
rw
Toggle fields

SPI6LPEN

Bit 0: SPI6LPEN.

I2C4LPEN

Bit 2: I2C4LPEN.

I2C6LPEN

Bit 3: I2C6LPEN.

USART1LPEN

Bit 4: USART1LPEN.

RTCAPBLPEN

Bit 8: RTCAPBLPEN.

TZC1LPEN

Bit 11: TZC1LPEN.

TZC2LPEN

Bit 12: TZC2LPEN.

TZPCLPEN

Bit 13: TZPCLPEN.

BSECLPEN

Bit 16: BSECLPEN.

STGENLPEN

Bit 20: STGENLPEN.

STGENSTPEN

Bit 21: STGENSTPEN.

MC_APB5LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0x38c, size: 32, reset: 0x0011391D, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STGENSTPEN
rw 		STGENLPEN
rw 		BSECLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TZPCLPEN
rw 		TZC2LPEN
rw 		TZC1LPEN
rw 		RTCAPBLPEN
rw 		USART1LPEN
rw 		I2C6LPEN
rw 		I2C4LPEN
rw 		SPI6LPEN
rw
Toggle fields

SPI6LPEN

Bit 0: SPI6LPEN.

I2C4LPEN

Bit 2: I2C4LPEN.

I2C6LPEN

Bit 3: I2C6LPEN.

USART1LPEN

Bit 4: USART1LPEN.

RTCAPBLPEN

Bit 8: RTCAPBLPEN.

TZC1LPEN

Bit 11: TZC1LPEN.

TZC2LPEN

Bit 12: TZC2LPEN.

TZPCLPEN

Bit 13: TZPCLPEN.

BSECLPEN

Bit 16: BSECLPEN.

STGENLPEN

Bit 20: STGENLPEN.

STGENSTPEN

Bit 21: STGENSTPEN.

MC_AHB5LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit. If TZEN = , this register can only be modified in secure mode.

Offset: 0x390, size: 32, reset: 0x00000171, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMLPEN
rw 		RNG1LPEN
rw 		HASH1LPEN
rw 		CRYP1LPEN
rw 		GPIOZLPEN
rw
Toggle fields

GPIOZLPEN

Bit 0: GPIOZLPEN.

CRYP1LPEN

Bit 4: CRYP1LPEN.

HASH1LPEN

Bit 5: HASH1LPEN.

RNG1LPEN

Bit 6: RNG1LPEN.

BKPSRAMLPEN

Bit 8: BKPSRAMLPEN.

MC_AHB5LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit If TZEN = , this register can only be modified in secure mode.

Offset: 0x394, size: 32, reset: 0x00000171, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPSRAMLPEN
rw 		RNG1LPEN
rw 		HASH1LPEN
rw 		CRYP1LPEN
rw 		GPIOZLPEN
rw
Toggle fields

GPIOZLPEN

Bit 0: GPIOZLPEN.

CRYP1LPEN

Bit 4: CRYP1LPEN.

HASH1LPEN

Bit 5: HASH1LPEN.

RNG1LPEN

Bit 6: RNG1LPEN.

BKPSRAMLPEN

Bit 8: BKPSRAMLPEN.

MC_AHB6LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0x398, size: 32, reset: 0x011357A1, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHLPEN
rw 		CRC1LPEN
rw 		SDMMC2LPEN
rw 		SDMMC1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPILPEN
rw 		FMCLPEN
rw 		ETHSTPEN
rw 		ETHMACLPEN
rw 		ETHRXLPEN
rw 		ETHTXLPEN
rw 		ETHCKLPEN
rw 		GPULPEN
rw 		MDMALPEN
rw
Toggle fields

MDMALPEN

Bit 0: MDMALPEN.

GPULPEN

Bit 5: GPULPEN.

ETHCKLPEN

Bit 7: ETHCKLPEN.

ETHTXLPEN

Bit 8: ETHTXLPEN.

ETHRXLPEN

Bit 9: ETHRXLPEN.

ETHMACLPEN

Bit 10: ETHMACLPEN.

ETHSTPEN

Bit 11: ETHSTPEN.

FMCLPEN

Bit 12: FMCLPEN.

QSPILPEN

Bit 14: QSPILPEN.

SDMMC1LPEN

Bit 16: SDMMC1LPEN.

SDMMC2LPEN

Bit 17: SDMMC2LPEN.

CRC1LPEN

Bit 20: CRC1LPEN.

USBHLPEN

Bit 24: USBHLPEN.

MC_AHB6LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0x39c, size: 32, reset: 0x011357A1, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
USBHLPEN
rw 		CRC1LPEN
rw 		SDMMC2LPEN
rw 		SDMMC1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPILPEN
rw 		FMCLPEN
rw 		ETHSTPEN
rw 		ETHMACLPEN
rw 		ETHRXLPEN
rw 		ETHTXLPEN
rw 		ETHCKLPEN
rw 		GPULPEN
rw 		MDMALPEN
rw
Toggle fields

MDMALPEN

Bit 0: MDMALPEN.

GPULPEN

Bit 5: GPULPEN.

ETHCKLPEN

Bit 7: ETHCKLPEN.

ETHTXLPEN

Bit 8: ETHTXLPEN.

ETHRXLPEN

Bit 9: ETHRXLPEN.

ETHMACLPEN

Bit 10: ETHMACLPEN.

ETHSTPEN

Bit 11: ETHSTPEN.

FMCLPEN

Bit 12: FMCLPEN.

QSPILPEN

Bit 14: QSPILPEN.

SDMMC1LPEN

Bit 16: SDMMC1LPEN.

SDMMC2LPEN

Bit 17: SDMMC2LPEN.

CRC1LPEN

Bit 20: CRC1LPEN.

USBHLPEN

Bit 24: USBHLPEN.

BR_RSTSCLRR

This register is used by the BOOTROM to check the reset source. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR). Refer to Section10.3.13: Reset source identification for details.This register except MPUP[1:0]RSTF flags is located into VDD domain, and is reset by por_rst reset. The MPUP[1:0]RSTF flags are located into VDDCORE and are reset by nreset. If TZEN = , this register can only be modified in secure mode.

Offset: 0x400, size: 32, reset: 0x00000015, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUP1RSTF
rw 		MPUP0RSTF
rw 		IWDG2RSTF
rw 		IWDG1RSTF
rw 		MCSYSRSTF
rw 		MPSYSRSTF
rw 		VCORERSTF
rw 		HCSSRSTF
rw 		PADRSTF
rw 		BORRSTF
rw 		PORRSTF
rw
Toggle fields

PORRSTF

Bit 0: PORRSTF.

BORRSTF

Bit 1: BORRSTF.

PADRSTF

Bit 2: PADRSTF.

HCSSRSTF

Bit 3: HCSSRSTF.

VCORERSTF

Bit 4: VCORERSTF.

MPSYSRSTF

Bit 6: MPSYSRSTF.

MCSYSRSTF

Bit 7: MCSYSRSTF.

IWDG1RSTF

Bit 8: IWDG1RSTF.

IWDG2RSTF

Bit 9: IWDG2RSTF.

MPUP0RSTF

Bit 13: MPUP0RSTF.

MPUP1RSTF

Bit 14: MPUP1RSTF.

MP_GRSTCSETR

This register is used by the MPU in order to generate either a MCU reset or a system reset or a reset of one of the two MPU processors. Writing has no effect, reading returns the effective values of the corresponding bits. Writing a activates the reset.

Offset: 0x404, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPUP1RST
rw 		MPUP0RST
rw 		MCURST
rw 		MPSYSRST
rw
Toggle fields

MPSYSRST

Bit 0: MPSYSRST.

MCURST

Bit 1: MCURST.

MPUP0RST

Bit 4: MPUP0RST.

MPUP1RST

Bit 5: MPUP1RST.

MP_RSTSCLRR

This register is used by the MPU to check the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.

Offset: 0x408, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPARE
rw 		MPUP1RSTF
rw 		MPUP0RSTF
rw 		CSTDBYRSTF
rw 		STDBYRSTF
rw 		IWDG2RSTF
rw 		IWDG1RSTF
rw 		MCSYSRSTF
rw 		MPSYSRSTF
rw 		VCORERSTF
rw 		HCSSRSTF
rw 		PADRSTF
rw 		BORRSTF
rw 		PORRSTF
rw
Toggle fields

PORRSTF

Bit 0: PORRSTF.

BORRSTF

Bit 1: BORRSTF.

PADRSTF

Bit 2: PADRSTF.

HCSSRSTF

Bit 3: HCSSRSTF.

VCORERSTF

Bit 4: VCORERSTF.

MPSYSRSTF

Bit 6: MPSYSRSTF.

MCSYSRSTF

Bit 7: MCSYSRSTF.

IWDG1RSTF

Bit 8: IWDG1RSTF.

IWDG2RSTF

Bit 9: IWDG2RSTF.

STDBYRSTF

Bit 11: STDBYRSTF.

CSTDBYRSTF

Bit 12: CSTDBYRSTF.

MPUP0RSTF

Bit 13: MPUP0RSTF.

MPUP1RSTF

Bit 14: MPUP1RSTF.

SPARE

Bit 15: SPARE.

MP_IWDGFZSETR

This register is used by the BOOTROM in order to freeze the IWDGs clocks. After a system reset or Standby reset (nreset), or a CStandby reset (cstby_rst) the MPU is allowed to write it once.Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to . If TZEN = , this register can only be modified in secure mode.

Offset: 0x40c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FZ_IWDG2
rw 		FZ_IWDG1
rw
Toggle fields

FZ_IWDG1

Bit 0: FZ_IWDG1.

FZ_IWDG2

Bit 1: FZ_IWDG2.

MP_IWDGFZCLRR

This register is used by the BOOTROM in order to unfreeze the IWDGs clocks. Writing has no effect, reading will return the effective values of the corresponding bits. Writing a clears the corresponding bit to . If TZEN = , this register can only be modified in secure mode.

Offset: 0x410, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FZ_IWDG2
rw 		FZ_IWDG1
rw
Toggle fields

FZ_IWDG1

Bit 0: FZ_IWDG1.

FZ_IWDG2

Bit 1: FZ_IWDG2.

MP_CIER

This register shall be used by the MPU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.

Offset: 0x414, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIE
rw 		LSECSSIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4DYIE
rw 		PLL3DYIE
rw 		PLL2DYIE
rw 		PLL1DYIE
rw 		CSIRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle fields

LSIRDYIE

Bit 0: LSIRDYIE.

LSERDYIE

Bit 1: LSERDYIE.

HSIRDYIE

Bit 2: HSIRDYIE.

HSERDYIE

Bit 3: HSERDYIE.

CSIRDYIE

Bit 4: CSIRDYIE.

PLL1DYIE

Bit 8: PLL1DYIE.

PLL2DYIE

Bit 9: PLL2DYIE.

PLL3DYIE

Bit 10: PLL3DYIE.

PLL4DYIE

Bit 11: PLL4DYIE.

LSECSSIE

Bit 16: LSECSSIE.

WKUPIE

Bit 20: WKUPIE.

MP_CIFR

This register shall be used by the MPU in order to read and clear the interrupt flags.Writing has no effect, writing will clear the corresponding flag.Refer to Section10.5: RCC interrupts for more details. If TZEN = , this register can only be modified in secure mode.

Offset: 0x418, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPF
rw 		LSECSSF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4DYF
rw 		PLL3DYF
rw 		PLL2DYF
rw 		PLL1DYF
rw 		CSIRDYF
rw 		HSERDYF
rw 		HSIRDYF
rw 		LSERDYF
rw 		LSIRDYF
rw
Toggle fields

LSIRDYF

Bit 0: LSIRDYF.

LSERDYF

Bit 1: LSERDYF.

HSIRDYF

Bit 2: HSIRDYF.

HSERDYF

Bit 3: HSERDYF.

CSIRDYF

Bit 4: CSIRDYF.

PLL1DYF

Bit 8: PLL1DYF.

PLL2DYF

Bit 9: PLL2DYF.

PLL3DYF

Bit 10: PLL3DYF.

PLL4DYF

Bit 11: PLL4DYF.

LSECSSF

Bit 16: LSECSSF.

WKUPF

Bit 20: WKUPF.

PWRLPDLYCR

This register is used to program the delay between the moment where the system exits from one of the Stop modes, and the moment where it is allowed to enable the PLLs and provide a clock to bridges and processors. If TZEN = , this register can only be modified in secure mode.

Offset: 0x41c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCTMPSKP
rw 		PWRLP_DLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PWRLP_DLY
rw
Toggle fields

PWRLP_DLY

Bits 0-21: PWRLP_DLY.

MCTMPSKP

Bit 24: MCTMPSKP.

MP_RSTSSETR

This register is dedicated to the BOOTROM code in order to update the reset source. This register is updated by the BOOTROM code, after a power-on reset (por_rst), a system reset (nreset), or an exit from Standby or CStandby. The application software shall not use this register. In order to identify the reset source, the MPU application must use RCC MPU Reset Status Clear Register (RCC_MP_RSTSCLRR), and the MCU application must use the RCC MCU Reset Status Clear Register (RCC_MC_RSTSCLRR).Writing has no effect, reading will return the effective values of the corresponding bits. Writing a sets the corresponding bit to .Refer to Section10.3.13: Reset source identification for details.The register is located in VDDCORE.If TZEN = , this register can only be modified in secure mode.

Offset: 0x420, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPARE
rw 		MPUP1RSTF
rw 		MPUP0RSTF
rw 		CSTDBYRSTF
rw 		STDBYRSTF
rw 		IWDG2RSTF
rw 		IWDG1RSTF
rw 		MCSYSRSTF
rw 		MPSYSRSTF
rw 		VCORERSTF
rw 		HCSSRSTF
rw 		PADRSTF
rw 		BORRSTF
rw 		PORRSTF
rw
Toggle fields

PORRSTF

Bit 0: PORRSTF.

BORRSTF

Bit 1: BORRSTF.

PADRSTF

Bit 2: PADRSTF.

HCSSRSTF

Bit 3: HCSSRSTF.

VCORERSTF

Bit 4: VCORERSTF.

MPSYSRSTF

Bit 6: MPSYSRSTF.

MCSYSRSTF

Bit 7: MCSYSRSTF.

IWDG1RSTF

Bit 8: IWDG1RSTF.

IWDG2RSTF

Bit 9: IWDG2RSTF.

STDBYRSTF

Bit 11: STDBYRSTF.

CSTDBYRSTF

Bit 12: CSTDBYRSTF.

MPUP0RSTF

Bit 13: MPUP0RSTF.

MPUP1RSTF

Bit 14: MPUP1RSTF.

SPARE

Bit 15: SPARE.

MCO1CFGR

This register is used to select the clock generated on MCO1 output.

Offset: 0x800, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCO1ON
rw 		MCO1DIV
rw 		MCO1SEL
rw
Toggle fields

MCO1SEL

Bits 0-2: MCO1SEL.

MCO1DIV

Bits 4-7: MCO1DIV.

MCO1ON

Bit 12: MCO1ON.

MCO2CFGR

This register is used to select the clock generated on MCO2 output.

Offset: 0x804, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCO2ON
rw 		MCO2DIV
rw 		MCO2SEL
rw
Toggle fields

MCO2SEL

Bits 0-2: MCO2SEL.

MCO2DIV

Bits 4-7: MCO2DIV.

MCO2ON

Bit 12: MCO2ON.

OCRDYR

This is a read-only access register, It contains the status flags of oscillators. Writing has no effect.

Offset: 0x808, size: 32, reset: 0x00000000, access: read-only

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKREST
r 		AXICKRDY
r 		MPUCKRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSERDY
r 		CSIRDY
r 		HSIDIVRDY
r 		HSIRDY
r
Toggle fields

HSIRDY

Bit 0: HSIRDY.

HSIDIVRDY

Bit 2: HSIDIVRDY.

CSIRDY

Bit 4: CSIRDY.

HSERDY

Bit 8: HSERDY.

MPUCKRDY

Bit 23: MPUCKRDY.

AXICKRDY

Bit 24: AXICKRDY.

CKREST

Bit 25: CKREST.

DBGCFGR

This is register contains the enable control of the debug and trace function, and the clock divider for the trace function.

Offset: 0x80c, size: 32, reset: 0x00000001, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBGRST
rw 		TRACECKEN
rw 		DBGCKEN
rw 		TRACEDIV
rw
Toggle fields

TRACEDIV

Bits 0-2: TRACEDIV.

DBGCKEN

Bit 8: DBGCKEN.

TRACECKEN

Bit 9: TRACECKEN.

DBGRST

Bit 12: DBGRST.

RCK3SELR

This register is used to select the reference clock for PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x820, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL3SRCRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL3SRC
rw
Toggle fields

PLL3SRC

Bits 0-1: PLL3SRC.

PLL3SRCRDY

Bit 31: PLL3SRCRDY.

RCK4SELR

This register is used to select the reference clock for PLL4.

Offset: 0x824, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL4SRCRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4SRC
rw
Toggle fields

PLL4SRC

Bits 0-1: PLL4SRC.

PLL4SRCRDY

Bit 31: PLL4SRCRDY.

TIMG1PRER

This register is used to control the prescaler value of timers located into APB1 domain. It concerns TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13 and TIM14. Refer to Section: Sub-system clock generation for additional information.

Offset: 0x828, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMG1PRERDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMG1PRE
rw
Toggle fields

TIMG1PRE

Bit 0: TIMG1PRE.

TIMG1PRERDY

Bit 31: TIMG1PRERDY.

TIMG2PRER

This register is used to control the prescaler value of timers located into APB2 domain. It concerns TIM1, TIM8, TIM15, TIM16, and TIM17. Refer to Section: Sub-system clock generation for additional information.

Offset: 0x82c, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TIMG2PRERDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMG2PRE
rw
Toggle fields

TIMG2PRE

Bit 0: TIMG2PRE.

TIMG2PRERDY

Bit 31: TIMG2PRERDY.

MCUDIVR

This register is used to control the MCU sub-system clock prescaler. Refer to Section: Sub-system clock generation for additional information. If TZEN = , this register can only be modified in secure mode.

Offset: 0x830, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCUDIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCUDIV
rw
Toggle fields

MCUDIV

Bits 0-3: MCUDIV.

MCUDIVRDY

Bit 31: MCUDIVRDY.

APB1DIVR

This register is used to control the APB1 clock prescaler. Refer to section Section1.4.6.3: Sub-System Clock Generation for additional information.

Offset: 0x834, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APB1DIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB1DIV
rw
Toggle fields

APB1DIV

Bits 0-2: APB1DIV.

APB1DIVRDY

Bit 31: APB1DIVRDY.

APB2DIVR

This register is used to control the APB2 clock prescaler. Refer to Section: Sub-system clock generation for additional information.

Offset: 0x838, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APB2DIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB2DIV
rw
Toggle fields

APB2DIV

Bits 0-2: APB2DIV.

APB2DIVRDY

Bit 31: APB2DIVRDY.

APB3DIVR

This register is used to control the APB3 clock prescaler. Refer to Section: Sub-system clock generation for additional information.

Offset: 0x83c, size: 32, reset: 0x80000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APB3DIVRDY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APB3DIV
rw
Toggle fields

APB3DIV

Bits 0-2: APB3DIV.

APB3DIVRDY

Bit 31: APB3DIVRDY.

PLL3CR

This register is used to control the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x880, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVREN
rw 		DIVQEN
rw 		DIVPEN
rw 		SSCG_CTRL
rw 		PLL3RDY
r 		PLLON
rw
Toggle fields

PLLON

Bit 0: PLLON.

PLL3RDY

Bit 1: PLL3RDY.

SSCG_CTRL

Bit 2: SSCG_CTRL.

DIVPEN

Bit 4: DIVPEN.

DIVQEN

Bit 5: DIVQEN.

DIVREN

Bit 6: DIVREN.

PLL3CFGR1

This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x884, size: 32, reset: 0x00010031, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IFRGE
rw 		DIVM3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVN
rw
Toggle fields

DIVN

Bits 0-8: DIVN.

DIVM3

Bits 16-21: DIVM3.

IFRGE

Bits 24-25: IFRGE.

PLL3CFGR2

This register is used to configure the PLL3. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x888, size: 32, reset: 0x00010101, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVQ
rw 		DIVP
rw
Toggle fields

DIVP

Bits 0-6: DIVP.

DIVQ

Bits 8-14: DIVQ.

DIVR

Bits 16-22: DIVR.

PLL3FRACR

This register is used to fine-tune the frequency of the PLL3 VCO. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x88c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRACLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACV
rw
Toggle fields

FRACV

Bits 3-15: FRACV.

FRACLE

Bit 16: FRACLE.

PLL3CSGR

This register is used to configure the PLL3.It is not recommended to change the content of this register when the PLL3 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x890, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INC_STEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSCG_MODE
rw 		RPDFN_DIS
rw 		TPDFN_DIS
rw 		MOD_PER
rw
Toggle fields

MOD_PER

Bits 0-12: MOD_PER.

TPDFN_DIS

Bit 13: TPDFN_DIS.

RPDFN_DIS

Bit 14: RPDFN_DIS.

SSCG_MODE

Bit 15: SSCG_MODE.

INC_STEP

Bits 16-30: INC_STEP.

PLL4CR

This register is used to control the PLL4.

Offset: 0x894, size: 32, reset: 0x00000000, access: Unspecified

1/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVREN
rw 		DIVQEN
rw 		DIVPEN
rw 		SSCG_CTRL
rw 		PLL4RDY
r 		PLLON
rw
Toggle fields

PLLON

Bit 0: PLLON.

PLL4RDY

Bit 1: PLL4RDY.

SSCG_CTRL

Bit 2: SSCG_CTRL.

DIVPEN

Bit 4: DIVPEN.

DIVQEN

Bit 5: DIVQEN.

DIVREN

Bit 6: DIVREN.

PLL4CFGR1

This register is used to configure the PLL4.

Offset: 0x898, size: 32, reset: 0x00010031, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IFRGE
rw 		DIVM4
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVN
rw
Toggle fields

DIVN

Bits 0-8: DIVN.

DIVM4

Bits 16-21: DIVM4.

IFRGE

Bits 24-25: IFRGE.

PLL4CFGR2

This register is used to configure the PLL4.

Offset: 0x89c, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIVR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVQ
rw 		DIVP
rw
Toggle fields

DIVP

Bits 0-6: DIVP.

DIVQ

Bits 8-14: DIVQ.

DIVR

Bits 16-22: DIVR.

PLL4FRACR

This register is used to fine-tune the frequency of the PLL4 VCO.

Offset: 0x8a0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FRACLE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACV
rw
Toggle fields

FRACV

Bits 3-15: FRACV.

FRACLE

Bit 16: FRACLE.

PLL4CSGR

This register is used to configure the PLL4.It is not recommended to change the content of this register when the PLL4 is enabled (PLLON = ). Refer to Section: Using the PLLs in spread spectrum mode for details. If TZEN = MCKPROT = , this register can only be modified in secure mode.

Offset: 0x8a4, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INC_STEP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSCG_MODE
rw 		RPDFN_DIS
rw 		TPDFN_DIS
rw 		MOD_PER
rw
Toggle fields

MOD_PER

Bits 0-12: MOD_PER.

TPDFN_DIS

Bit 13: TPDFN_DIS.

RPDFN_DIS

Bit 14: RPDFN_DIS.

SSCG_MODE

Bit 15: SSCG_MODE.

INC_STEP

Bits 16-30: INC_STEP.

I2C12CKSELR

This register is used to control the selection of the kernel clock for the I2C1 and I2C2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C12SRC
rw
Toggle fields

I2C12SRC

Bits 0-2: I2C12SRC.

I2C35CKSELR

This register is used to control the selection of the kernel clock for the I2C3 and I2C5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8c4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C35SRC
rw
Toggle fields

I2C35SRC

Bits 0-2: I2C35SRC.

SAI1CKSELR

This register is used to control the selection of the kernel clock for the SAI1 and DFSDM audio clock. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8c8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI1SRC
rw
Toggle fields

SAI1SRC

Bits 0-2: SAI1SRC.

SAI2CKSELR

This register is used to control the selection of the kernel clock for the SAI2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8cc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI2SRC
rw
Toggle fields

SAI2SRC

Bits 0-2: SAI2SRC.

SAI3CKSELR

This register is used to control the selection of the kernel clock for the SAI3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8d0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI3SRC
rw
Toggle fields

SAI3SRC

Bits 0-2: SAI3SRC.

SAI4CKSELR

This register is used to control the selection of the kernel clock for the SAI4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8d4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAI4SRC
rw
Toggle fields

SAI4SRC

Bits 0-2: SAI4SRC.

SPI2S1CKSELR

This register is used to control the selection of the kernel clock for the SPI/I2S1. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8d8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI1SRC
rw
Toggle fields

SPI1SRC

Bits 0-2: SPI1SRC.

SPI2S23CKSELR

This register is used to control the selection of the kernel clock for the SPI/I2S2,3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8dc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI23SRC
rw
Toggle fields

SPI23SRC

Bits 0-2: SPI23SRC.

SPI45CKSELR

This register is used to control the selection of the kernel clock for the SPI4,5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI45SRC
rw
Toggle fields

SPI45SRC

Bits 0-2: SPI45SRC.

UART6CKSELR

This register is used to control the selection of the kernel clock for the USART6. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8e4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UART6SRC
rw
Toggle fields

UART6SRC

Bits 0-2: UART6SRC.

UART24CKSELR

This register is used to control the selection of the kernel clock for the USART2 and UART4. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8e8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UART24SRC
rw
Toggle fields

UART24SRC

Bits 0-2: UART24SRC.

UART35CKSELR

This register is used to control the selection of the kernel clock for the USART3 and UART5. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8ec, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UART35SRC
rw
Toggle fields

UART35SRC

Bits 0-2: UART35SRC.

UART78CKSELR

This register is used to control the selection of the kernel clock for the UART7 and UART8. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8f0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UART78SRC
rw
Toggle fields

UART78SRC

Bits 0-2: UART78SRC.

SDMMC12CKSELR

This register is used to control the selection of the kernel clock for the SDMMC1 and SDMMC2. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8f4, size: 32, reset: 0x00000003, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMC12SRC
rw
Toggle fields

SDMMC12SRC

Bits 0-2: SDMMC12SRC.

SDMMC3CKSELR

This register is used to control the selection of the kernel clock for the SDMMC3. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8f8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMMC3SRC
rw
Toggle fields

SDMMC3SRC

Bits 0-2: SDMMC3SRC.

ETHCKSELR

This register is used to control the selection of the kernel clock for the ETH block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x8fc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETHPTPDIV
rw 		ETHSRC
rw
Toggle fields

ETHSRC

Bits 0-1: ETHSRC.

ETHPTPDIV

Bits 4-7: ETHPTPDIV.

QSPICKSELR

This register is used to control the selection of the kernel clock for the QUADSPI. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x900, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
QSPISRC
rw
Toggle fields

QSPISRC

Bits 0-1: QSPISRC.

FMCCKSELR

This register is used to control the selection of the kernel clock for the FMC block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x904, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMCSRC
rw
Toggle fields

FMCSRC

Bits 0-1: FMCSRC.

FDCANCKSELR

This register is used to control the selection of the kernel clock for the FDCAN block. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x90c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FDCANSRC
rw
Toggle fields

FDCANSRC

Bits 0-1: FDCANSRC.

SPDIFCKSELR

This register is used to control the selection of the kernel clock for the SPDIFRX. Note that changing the clock source on-the-fly is allowed, and will not generate any timing violation, however the user has to ensure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Refer to Section: Clock enabling delays.

Offset: 0x914, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPDIFSRC
rw
Toggle fields

SPDIFSRC

Bits 0-1: SPDIFSRC.

CECCKSELR

This register is used to control the selection of the kernel clock for the CEC-HDMI.

Offset: 0x918, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CECSRC
rw
Toggle fields

CECSRC

Bits 0-1: CECSRC.

USBCKSELR

This register is used to control the selection of the kernel clock for the USBPHY PLL of the USB HOST and USB OTG

Offset: 0x91c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOSRC
rw 		USBPHYSRC
rw
Toggle fields

USBPHYSRC

Bits 0-1: USBPHYSRC.

USBOSRC

Bit 4: USBOSRC.

RNG2CKSELR

This register is used to control the selection of the kernel clock for the RNG2.

Offset: 0x920, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG2SRC
rw
Toggle fields

RNG2SRC

Bits 0-1: RNG2SRC.

DSICKSELR

This register is used to control the selection of the kernel clock for the DSI block.

Offset: 0x924, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSISRC
rw
Toggle fields

DSISRC

Bit 0: DSISRC.

ADCCKSELR

This register is used to control the selection of the kernel clock for the ADC block.

Offset: 0x928, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADCSRC
rw
Toggle fields

ADCSRC

Bits 0-1: ADCSRC.

LPTIM45CKSELR

This register is used to control the selection of the kernel clock for the LPTIM4 and LPTIM5 blocks.

Offset: 0x92c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM45SRC
rw
Toggle fields

LPTIM45SRC

Bits 0-2: LPTIM45SRC.

LPTIM23CKSELR

This register is used to control the selection of the kernel clock for the LPTIM2 and LPTIM3 blocks.

Offset: 0x930, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM23SRC
rw
Toggle fields

LPTIM23SRC

Bits 0-2: LPTIM23SRC.

LPTIM1CKSELR

This register is used to control the selection of the kernel clock for the LPTIM1 block.

Offset: 0x934, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPTIM1SRC
rw
Toggle fields

LPTIM1SRC

Bits 0-2: LPTIM1SRC.

APB1RSTSETR

This register is used to activate the reset of the corresponding peripheral.

Offset: 0x980, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSRST
rw 		DAC12RST
rw 		CECRST
rw 		SPDIFRST
rw 		I2C5RST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART8RST
rw 		UART7RST
rw 		UART5RST
rw 		UART4RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3RST
rw 		USART2RST
rw 		SPI3RST
rw 		SPI2RST
rw 		LPTIM1RST
rw 		TIM14RST
rw 		TIM13RST
rw 		TIM12RST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2RST.

TIM3RST

Bit 1: TIM3RST.

TIM4RST

Bit 2: TIM4RST.

TIM5RST

Bit 3: TIM5RST.

TIM6RST

Bit 4: TIM6RST.

TIM7RST

Bit 5: TIM7RST.

TIM12RST

Bit 6: TIM12RST.

TIM13RST

Bit 7: TIM13RST.

TIM14RST

Bit 8: TIM14RST.

LPTIM1RST

Bit 9: LPTIM1RST.

SPI2RST

Bit 11: SPI2RST.

SPI3RST

Bit 12: SPI3RST.

USART2RST

Bit 14: USART2RST.

USART3RST

Bit 15: USART3RST.

UART4RST

Bit 16: UART4RST.

UART5RST

Bit 17: UART5RST.

UART7RST

Bit 18: UART7RST.

UART8RST

Bit 19: UART8RST.

I2C1RST

Bit 21: I2C1RST.

I2C2RST

Bit 22: I2C2RST.

I2C3RST

Bit 23: I2C3RST.

I2C5RST

Bit 24: I2C5RST.

SPDIFRST

Bit 26: SPDIFRST.

CECRST

Bit 27: CECRST.

DAC12RST

Bit 29: DAC12RST.

MDIOSRST

Bit 31: MDIOSRST.

APB1RSTCLRR

This register is used to release the reset of the corresponding peripheral.

Offset: 0x984, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSRST
rw 		DAC12RST
rw 		CECRST
rw 		SPDIFRST
rw 		I2C5RST
rw 		I2C3RST
rw 		I2C2RST
rw 		I2C1RST
rw 		UART8RST
rw 		UART7RST
rw 		UART5RST
rw 		UART4RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3RST
rw 		USART2RST
rw 		SPI3RST
rw 		SPI2RST
rw 		LPTIM1RST
rw 		TIM14RST
rw 		TIM13RST
rw 		TIM12RST
rw 		TIM7RST
rw 		TIM6RST
rw 		TIM5RST
rw 		TIM4RST
rw 		TIM3RST
rw 		TIM2RST
rw
Toggle fields

TIM2RST

Bit 0: TIM2RST.

TIM3RST

Bit 1: TIM3RST.

TIM4RST

Bit 2: TIM4RST.

TIM5RST

Bit 3: TIM5RST.

TIM6RST

Bit 4: TIM6RST.

TIM7RST

Bit 5: TIM7RST.

TIM12RST

Bit 6: TIM12RST.

TIM13RST

Bit 7: TIM13RST.

TIM14RST

Bit 8: TIM14RST.

LPTIM1RST

Bit 9: LPTIM1RST.

SPI2RST

Bit 11: SPI2RST.

SPI3RST

Bit 12: SPI3RST.

USART2RST

Bit 14: USART2RST.

USART3RST

Bit 15: USART3RST.

UART4RST

Bit 16: UART4RST.

UART5RST

Bit 17: UART5RST.

UART7RST

Bit 18: UART7RST.

UART8RST

Bit 19: UART8RST.

I2C1RST

Bit 21: I2C1RST.

I2C2RST

Bit 22: I2C2RST.

I2C3RST

Bit 23: I2C3RST.

I2C5RST

Bit 24: I2C5RST.

SPDIFRST

Bit 26: SPDIFRST.

CECRST

Bit 27: CECRST.

DAC12RST

Bit 29: DAC12RST.

MDIOSRST

Bit 31: MDIOSRST.

APB2RSTSETR

This register is used to activate the reset of the corresponding peripheral.

Offset: 0x988, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANRST
rw 		DFSDMRST
rw 		SAI3RST
rw 		SAI2RST
rw 		SAI1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6RST
rw 		SPI5RST
rw 		SPI4RST
rw 		SPI1RST
rw 		TIM17RST
rw 		TIM16RST
rw 		TIM15RST
rw 		TIM8RST
rw 		TIM1RST
rw
Toggle fields

TIM1RST

Bit 0: TIM1RST.

TIM8RST

Bit 1: TIM8RST.

TIM15RST

Bit 2: TIM15RST.

TIM16RST

Bit 3: TIM16RST.

TIM17RST

Bit 4: TIM17RST.

SPI1RST

Bit 8: SPI1RST.

SPI4RST

Bit 9: SPI4RST.

SPI5RST

Bit 10: SPI5RST.

USART6RST

Bit 13: USART6RST.

SAI1RST

Bit 16: SAI1RST.

SAI2RST

Bit 17: SAI2RST.

SAI3RST

Bit 18: SAI3RST.

DFSDMRST

Bit 20: DFSDMRST.

FDCANRST

Bit 24: FDCANRST.

APB2RSTCLRR

This register is used to release the reset of the corresponding peripheral.

Offset: 0x98c, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANRST
rw 		DFSDMRST
rw 		SAI3RST
rw 		SAI2RST
rw 		SAI1RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6RST
rw 		SPI5RST
rw 		SPI4RST
rw 		SPI1RST
rw 		TIM17RST
rw 		TIM16RST
rw 		TIM15RST
rw 		TIM8RST
rw 		TIM1RST
rw
Toggle fields

TIM1RST

Bit 0: TIM1RST.

TIM8RST

Bit 1: TIM8RST.

TIM15RST

Bit 2: TIM15RST.

TIM16RST

Bit 3: TIM16RST.

TIM17RST

Bit 4: TIM17RST.

SPI1RST

Bit 8: SPI1RST.

SPI4RST

Bit 9: SPI4RST.

SPI5RST

Bit 10: SPI5RST.

USART6RST

Bit 13: USART6RST.

SAI1RST

Bit 16: SAI1RST.

SAI2RST

Bit 17: SAI2RST.

SAI3RST

Bit 18: SAI3RST.

DFSDMRST

Bit 20: DFSDMRST.

FDCANRST

Bit 24: FDCANRST.

APB3RSTSETR

This register is used to activate the reset of the corresponding peripheral.

Offset: 0x990, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFRST
rw 		SYSCFGRST
rw 		SAI4RST
rw 		LPTIM5RST
rw 		LPTIM4RST
rw 		LPTIM3RST
rw 		LPTIM2RST
rw
Toggle fields

LPTIM2RST

Bit 0: LPTIM2RST.

LPTIM3RST

Bit 1: LPTIM3RST.

LPTIM4RST

Bit 2: LPTIM4RST.

LPTIM5RST

Bit 3: LPTIM5RST.

SAI4RST

Bit 8: SAI4RST.

SYSCFGRST

Bit 11: SYSCFGRST.

VREFRST

Bit 13: VREFRST.

DTSRST

Bit 16: DTSRST.

APB3RSTCLRR

This register is used to release the reset of the corresponding peripheral.

Offset: 0x994, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSRST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFRST
rw 		SYSCFGRST
rw 		SAI4RST
rw 		LPTIM5RST
rw 		LPTIM4RST
rw 		LPTIM3RST
rw 		LPTIM2RST
rw
Toggle fields

LPTIM2RST

Bit 0: LPTIM2RST.

LPTIM3RST

Bit 1: LPTIM3RST.

LPTIM4RST

Bit 2: LPTIM4RST.

LPTIM5RST

Bit 3: LPTIM5RST.

SAI4RST

Bit 8: SAI4RST.

SYSCFGRST

Bit 11: SYSCFGRST.

VREFRST

Bit 13: VREFRST.

DTSRST

Bit 16: DTSRST.

AHB2RSTSETR

This register is used to activate the reset of the corresponding peripheral.

Offset: 0x998, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBORST
rw 		ADC12RST
rw 		DMAMUXRST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1RST.

DMA2RST

Bit 1: DMA2RST.

DMAMUXRST

Bit 2: DMAMUXRST.

ADC12RST

Bit 5: ADC12RST.

USBORST

Bit 8: USBORST.

SDMMC3RST

Bit 16: SDMMC3RST.

AHB2RSTCLRR

This register is used to release the reset of the corresponding peripheral.

Offset: 0x99c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBORST
rw 		ADC12RST
rw 		DMAMUXRST
rw 		DMA2RST
rw 		DMA1RST
rw
Toggle fields

DMA1RST

Bit 0: DMA1RST.

DMA2RST

Bit 1: DMA2RST.

DMAMUXRST

Bit 2: DMAMUXRST.

ADC12RST

Bit 5: ADC12RST.

USBORST

Bit 8: USBORST.

SDMMC3RST

Bit 16: SDMMC3RST.

AHB3RSTSETR

This register is used to activate the reset of the corresponding peripheral.

Offset: 0x9a0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCRST
rw 		HSEMRST
rw 		CRC2RST
rw 		RNG2RST
rw 		HASH2RST
rw 		CRYP2RST
rw 		DCMIRST
rw
Toggle fields

DCMIRST

Bit 0: DCMIRST.

CRYP2RST

Bit 4: CRYP2RST.

HASH2RST

Bit 5: HASH2RST.

RNG2RST

Bit 6: RNG2RST.

CRC2RST

Bit 7: CRC2RST.

HSEMRST

Bit 11: HSEMRST.

IPCCRST

Bit 12: IPCCRST.

AHB3RSTCLRR

This register is used to release the reset of the corresponding peripheral.

Offset: 0x9a4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCRST
rw 		HSEMRST
rw 		CRC2RST
rw 		RNG2RST
rw 		HASH2RST
rw 		CRYP2RST
rw 		DCMIRST
rw
Toggle fields

DCMIRST

Bit 0: DCMIRST.

CRYP2RST

Bit 4: CRYP2RST.

HASH2RST

Bit 5: HASH2RST.

RNG2RST

Bit 6: RNG2RST.

CRC2RST

Bit 7: CRC2RST.

HSEMRST

Bit 11: HSEMRST.

IPCCRST

Bit 12: IPCCRST.

AHB4RSTSETR

This register is used to activate the reset of the corresponding peripheral

Offset: 0x9a8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKRST
rw 		GPIOJRST
rw 		GPIOIRST
rw 		GPIOHRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: GPIOARST.

GPIOBRST

Bit 1: GPIOBRST.

GPIOCRST

Bit 2: GPIOCRST.

GPIODRST

Bit 3: GPIODRST.

GPIOERST

Bit 4: GPIOERST.

GPIOFRST

Bit 5: GPIOFRST.

GPIOGRST

Bit 6: GPIOGRST.

GPIOHRST

Bit 7: GPIOHRST.

GPIOIRST

Bit 8: GPIOIRST.

GPIOJRST

Bit 9: GPIOJRST.

GPIOKRST

Bit 10: GPIOKRST.

AHB4RSTCLRR

This register is used to release the reset of the corresponding peripheral.

Offset: 0x9ac, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKRST
rw 		GPIOJRST
rw 		GPIOIRST
rw 		GPIOHRST
rw 		GPIOGRST
rw 		GPIOFRST
rw 		GPIOERST
rw 		GPIODRST
rw 		GPIOCRST
rw 		GPIOBRST
rw 		GPIOARST
rw
Toggle fields

GPIOARST

Bit 0: GPIOARST.

GPIOBRST

Bit 1: GPIOBRST.

GPIOCRST

Bit 2: GPIOCRST.

GPIODRST

Bit 3: GPIODRST.

GPIOERST

Bit 4: GPIOERST.

GPIOFRST

Bit 5: GPIOFRST.

GPIOGRST

Bit 6: GPIOGRST.

GPIOHRST

Bit 7: GPIOHRST.

GPIOIRST

Bit 8: GPIOIRST.

GPIOJRST

Bit 9: GPIOJRST.

GPIOKRST

Bit 10: GPIOKRST.

MP_APB1ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa00, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSEN
rw 		DAC12EN
rw 		CECEN
rw 		SPDIFEN
rw 		I2C5EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART8EN
rw 		UART7EN
rw 		UART5EN
rw 		UART4EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3EN
rw 		USART2EN
rw 		SPI3EN
rw 		SPI2EN
rw 		LPTIM1EN
rw 		TIM14EN
rw 		TIM13EN
rw 		TIM12EN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2EN.

TIM3EN

Bit 1: TIM3EN.

TIM4EN

Bit 2: TIM4EN.

TIM5EN

Bit 3: TIM5EN.

TIM6EN

Bit 4: TIM6EN.

TIM7EN

Bit 5: TIM7EN.

TIM12EN

Bit 6: TIM12EN.

TIM13EN

Bit 7: TIM13EN.

TIM14EN

Bit 8: TIM14EN.

LPTIM1EN

Bit 9: LPTIM1EN.

SPI2EN

Bit 11: SPI2EN.

SPI3EN

Bit 12: SPI3EN.

USART2EN

Bit 14: USART2EN.

USART3EN

Bit 15: USART3EN.

UART4EN

Bit 16: UART4EN.

UART5EN

Bit 17: UART5EN.

UART7EN

Bit 18: UART7EN.

UART8EN

Bit 19: UART8EN.

I2C1EN

Bit 21: I2C1EN.

I2C2EN

Bit 22: I2C2EN.

I2C3EN

Bit 23: I2C3EN.

I2C5EN

Bit 24: I2C5EN.

SPDIFEN

Bit 26: SPDIFEN.

CECEN

Bit 27: CECEN.

DAC12EN

Bit 29: DAC12EN.

MDIOSEN

Bit 31: MDIOSEN.

MP_APB1ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xa04, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSEN
rw 		DAC12EN
rw 		CECEN
rw 		SPDIFEN
rw 		I2C5EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART8EN
rw 		UART7EN
rw 		UART5EN
rw 		UART4EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3EN
rw 		USART2EN
rw 		SPI3EN
rw 		SPI2EN
rw 		LPTIM1EN
rw 		TIM14EN
rw 		TIM13EN
rw 		TIM12EN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2EN.

TIM3EN

Bit 1: TIM3EN.

TIM4EN

Bit 2: TIM4EN.

TIM5EN

Bit 3: TIM5EN.

TIM6EN

Bit 4: TIM6EN.

TIM7EN

Bit 5: TIM7EN.

TIM12EN

Bit 6: TIM12EN.

TIM13EN

Bit 7: TIM13EN.

TIM14EN

Bit 8: TIM14EN.

LPTIM1EN

Bit 9: LPTIM1EN.

SPI2EN

Bit 11: SPI2EN.

SPI3EN

Bit 12: SPI3EN.

USART2EN

Bit 14: USART2EN.

USART3EN

Bit 15: USART3EN.

UART4EN

Bit 16: UART4EN.

UART5EN

Bit 17: UART5EN.

UART7EN

Bit 18: UART7EN.

UART8EN

Bit 19: UART8EN.

I2C1EN

Bit 21: I2C1EN.

I2C2EN

Bit 22: I2C2EN.

I2C3EN

Bit 23: I2C3EN.

I2C5EN

Bit 24: I2C5EN.

SPDIFEN

Bit 26: SPDIFEN.

CECEN

Bit 27: CECEN.

DAC12EN

Bit 29: DAC12EN.

MDIOSEN

Bit 31: MDIOSEN.

MP_APB2ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa08, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANEN
rw 		ADFSDMEN
rw 		DFSDMEN
rw 		SAI3EN
rw 		SAI2EN
rw 		SAI1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6EN
rw 		SPI5EN
rw 		SPI4EN
rw 		SPI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw 		TIM8EN
rw 		TIM1EN
rw
Toggle fields

TIM1EN

Bit 0: TIM1EN.

TIM8EN

Bit 1: TIM8EN.

TIM15EN

Bit 2: TIM15EN.

TIM16EN

Bit 3: TIM16EN.

TIM17EN

Bit 4: TIM17EN.

SPI1EN

Bit 8: SPI1EN.

SPI4EN

Bit 9: SPI4EN.

SPI5EN

Bit 10: SPI5EN.

USART6EN

Bit 13: USART6EN.

SAI1EN

Bit 16: SAI1EN.

SAI2EN

Bit 17: SAI2EN.

SAI3EN

Bit 18: SAI3EN.

DFSDMEN

Bit 20: DFSDMEN.

ADFSDMEN

Bit 21: ADFSDMEN.

FDCANEN

Bit 24: FDCANEN.

MP_APB2ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral.

Offset: 0xa0c, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANEN
rw 		ADFSDMEN
rw 		DFSDMEN
rw 		SAI3EN
rw 		SAI2EN
rw 		SAI1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6EN
rw 		SPI5EN
rw 		SPI4EN
rw 		SPI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw 		TIM8EN
rw 		TIM1EN
rw
Toggle fields

TIM1EN

Bit 0: TIM1EN.

TIM8EN

Bit 1: TIM8EN.

TIM15EN

Bit 2: TIM15EN.

TIM16EN

Bit 3: TIM16EN.

TIM17EN

Bit 4: TIM17EN.

SPI1EN

Bit 8: SPI1EN.

SPI4EN

Bit 9: SPI4EN.

SPI5EN

Bit 10: SPI5EN.

USART6EN

Bit 13: USART6EN.

SAI1EN

Bit 16: SAI1EN.

SAI2EN

Bit 17: SAI2EN.

SAI3EN

Bit 18: SAI3EN.

DFSDMEN

Bit 20: DFSDMEN.

ADFSDMEN

Bit 21: ADFSDMEN.

FDCANEN

Bit 24: FDCANEN.

MP_APB3ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa10, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDPEN
rw 		DTSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFEN
rw 		SYSCFGEN
rw 		SAI4EN
rw 		LPTIM5EN
rw 		LPTIM4EN
rw 		LPTIM3EN
rw 		LPTIM2EN
rw
Toggle fields

LPTIM2EN

Bit 0: LPTIM2EN.

LPTIM3EN

Bit 1: LPTIM3EN.

LPTIM4EN

Bit 2: LPTIM4EN.

LPTIM5EN

Bit 3: LPTIM5EN.

SAI4EN

Bit 8: SAI4EN.

SYSCFGEN

Bit 11: SYSCFGEN.

VREFEN

Bit 13: VREFEN.

DTSEN

Bit 16: DTSEN.

HDPEN

Bit 20: HDPEN.

MP_APB3ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral.

Offset: 0xa14, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDPEN
rw 		DTSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFEN
rw 		SYSCFGEN
rw 		SAI4EN
rw 		LPTIM5EN
rw 		LPTIM4EN
rw 		LPTIM3EN
rw 		LPTIM2EN
rw
Toggle fields

LPTIM2EN

Bit 0: LPTIM2EN.

LPTIM3EN

Bit 1: LPTIM3EN.

LPTIM4EN

Bit 2: LPTIM4EN.

LPTIM5EN

Bit 3: LPTIM5EN.

SAI4EN

Bit 8: SAI4EN.

SYSCFGEN

Bit 11: SYSCFGEN.

VREFEN

Bit 13: VREFEN.

DTSEN

Bit 16: DTSEN.

HDPEN

Bit 20: HDPEN.

MP_AHB2ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral

Offset: 0xa18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOEN
rw 		ADC12EN
rw 		DMAMUXEN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1EN.

DMA2EN

Bit 1: DMA2EN.

DMAMUXEN

Bit 2: DMAMUXEN.

ADC12EN

Bit 5: ADC12EN.

USBOEN

Bit 8: USBOEN.

SDMMC3EN

Bit 16: SDMMC3EN.

MP_AHB2ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral.

Offset: 0xa1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOEN
rw 		ADC12EN
rw 		DMAMUXEN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1EN.

DMA2EN

Bit 1: DMA2EN.

DMAMUXEN

Bit 2: DMAMUXEN.

ADC12EN

Bit 5: ADC12EN.

USBOEN

Bit 8: USBOEN.

SDMMC3EN

Bit 16: SDMMC3EN.

MP_AHB3ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral

Offset: 0xa20, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCEN
rw 		HSEMEN
rw 		CRC2EN
rw 		RNG2EN
rw 		HASH2EN
rw 		CRYP2EN
rw 		DCMIEN
rw
Toggle fields

DCMIEN

Bit 0: DCMIEN.

CRYP2EN

Bit 4: CRYP2EN.

HASH2EN

Bit 5: HASH2EN.

RNG2EN

Bit 6: RNG2EN.

CRC2EN

Bit 7: CRC2EN.

HSEMEN

Bit 11: HSEMEN.

IPCCEN

Bit 12: IPCCEN.

MP_AHB3ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral.

Offset: 0xa24, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCEN
rw 		HSEMEN
rw 		CRC2EN
rw 		RNG2EN
rw 		HASH2EN
rw 		CRYP2EN
rw 		DCMIEN
rw
Toggle fields

DCMIEN

Bit 0: DCMIEN.

CRYP2EN

Bit 4: CRYP2EN.

HASH2EN

Bit 5: HASH2EN.

RNG2EN

Bit 6: RNG2EN.

CRC2EN

Bit 7: CRC2EN.

HSEMEN

Bit 11: HSEMEN.

IPCCEN

Bit 12: IPCCEN.

MP_AHB4ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MPU.

Offset: 0xa28, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKEN
rw 		GPIOJEN
rw 		GPIOIEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: GPIOAEN.

GPIOBEN

Bit 1: GPIOBEN.

GPIOCEN

Bit 2: GPIOCEN.

GPIODEN

Bit 3: GPIODEN.

GPIOEEN

Bit 4: GPIOEEN.

GPIOFEN

Bit 5: GPIOFEN.

GPIOGEN

Bit 6: GPIOGEN.

GPIOHEN

Bit 7: GPIOHEN.

GPIOIEN

Bit 8: GPIOIEN.

GPIOJEN

Bit 9: GPIOJEN.

GPIOKEN

Bit 10: GPIOKEN.

MP_AHB4ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xa2c, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKEN
rw 		GPIOJEN
rw 		GPIOIEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: GPIOAEN.

GPIOBEN

Bit 1: GPIOBEN.

GPIOCEN

Bit 2: GPIOCEN.

GPIODEN

Bit 3: GPIODEN.

GPIOEEN

Bit 4: GPIOEEN.

GPIOFEN

Bit 5: GPIOFEN.

GPIOGEN

Bit 6: GPIOGEN.

GPIOHEN

Bit 7: GPIOHEN.

GPIOIEN

Bit 8: GPIOIEN.

GPIOJEN

Bit 9: GPIOJEN.

GPIOKEN

Bit 10: GPIOKEN.

MP_MLAHBENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa38, size: 32, reset: 0x00000010, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMEN
rw
Toggle fields

RETRAMEN

Bit 4: RETRAMEN.

MP_MLAHBENCLRR

This register is used to clear the peripheral clock enable bit.

Offset: 0xa3c, size: 32, reset: 0x00000010, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMEN
rw
Toggle fields

RETRAMEN

Bit 4: RETRAMEN.

MC_APB1ENSETR

This register is used to set the peripheral clock enable bit of the corresponding peripheral to . It shall be used to allocate a peripheral to the MCU. Writing has no effect, reading will return . Writing a sets the corresponding bit to .

Offset: 0xa80, size: 32, reset: 0x00000000, access: read-write

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSEN
rw 		DAC12EN
rw 		WWDG1EN
rw 		CECEN
rw 		SPDIFEN
rw 		I2C5EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART8EN
rw 		UART7EN
rw 		UART5EN
rw 		UART4EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3EN
rw 		USART2EN
rw 		SPI3EN
rw 		SPI2EN
rw 		LPTIM1EN
rw 		TIM14EN
rw 		TIM13EN
rw 		TIM12EN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2EN.

TIM3EN

Bit 1: TIM3EN.

TIM4EN

Bit 2: TIM4EN.

TIM5EN

Bit 3: TIM5EN.

TIM6EN

Bit 4: TIM6EN.

TIM7EN

Bit 5: TIM7EN.

TIM12EN

Bit 6: TIM12EN.

TIM13EN

Bit 7: TIM13EN.

TIM14EN

Bit 8: TIM14EN.

LPTIM1EN

Bit 9: LPTIM1EN.

SPI2EN

Bit 11: SPI2EN.

SPI3EN

Bit 12: SPI3EN.

USART2EN

Bit 14: USART2EN.

USART3EN

Bit 15: USART3EN.

UART4EN

Bit 16: UART4EN.

UART5EN

Bit 17: UART5EN.

UART7EN

Bit 18: UART7EN.

UART8EN

Bit 19: UART8EN.

I2C1EN

Bit 21: I2C1EN.

I2C2EN

Bit 22: I2C2EN.

I2C3EN

Bit 23: I2C3EN.

I2C5EN

Bit 24: I2C5EN.

SPDIFEN

Bit 26: SPDIFEN.

CECEN

Bit 27: CECEN.

WWDG1EN

Bit 28: WWDG1EN.

DAC12EN

Bit 29: DAC12EN.

MDIOSEN

Bit 31: MDIOSEN.

MC_APB1ENCLRR

This register is used to clear the peripheral clock enable bit of the corresponding peripheral.

Offset: 0xa84, size: 32, reset: 0x00000000, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSEN
rw 		DAC12EN
rw 		CECEN
rw 		SPDIFEN
rw 		I2C5EN
rw 		I2C3EN
rw 		I2C2EN
rw 		I2C1EN
rw 		UART8EN
rw 		UART7EN
rw 		UART5EN
rw 		UART4EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3EN
rw 		USART2EN
rw 		SPI3EN
rw 		SPI2EN
rw 		LPTIM1EN
rw 		TIM14EN
rw 		TIM13EN
rw 		TIM12EN
rw 		TIM7EN
rw 		TIM6EN
rw 		TIM5EN
rw 		TIM4EN
rw 		TIM3EN
rw 		TIM2EN
rw
Toggle fields

TIM2EN

Bit 0: TIM2EN.

TIM3EN

Bit 1: TIM3EN.

TIM4EN

Bit 2: TIM4EN.

TIM5EN

Bit 3: TIM5EN.

TIM6EN

Bit 4: TIM6EN.

TIM7EN

Bit 5: TIM7EN.

TIM12EN

Bit 6: TIM12EN.

TIM13EN

Bit 7: TIM13EN.

TIM14EN

Bit 8: TIM14EN.

LPTIM1EN

Bit 9: LPTIM1EN.

SPI2EN

Bit 11: SPI2EN.

SPI3EN

Bit 12: SPI3EN.

USART2EN

Bit 14: USART2EN.

USART3EN

Bit 15: USART3EN.

UART4EN

Bit 16: UART4EN.

UART5EN

Bit 17: UART5EN.

UART7EN

Bit 18: UART7EN.

UART8EN

Bit 19: UART8EN.

I2C1EN

Bit 21: I2C1EN.

I2C2EN

Bit 22: I2C2EN.

I2C3EN

Bit 23: I2C3EN.

I2C5EN

Bit 24: I2C5EN.

SPDIFEN

Bit 26: SPDIFEN.

CECEN

Bit 27: CECEN.

DAC12EN

Bit 29: DAC12EN.

MDIOSEN

Bit 31: MDIOSEN.

MC_APB2ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa88, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANEN
rw 		ADFSDMEN
rw 		DFSDMEN
rw 		SAI3EN
rw 		SAI2EN
rw 		SAI1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6EN
rw 		SPI5EN
rw 		SPI4EN
rw 		SPI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw 		TIM8EN
rw 		TIM1EN
rw
Toggle fields

TIM1EN

Bit 0: TIM1EN.

TIM8EN

Bit 1: TIM8EN.

TIM15EN

Bit 2: TIM15EN.

TIM16EN

Bit 3: TIM16EN.

TIM17EN

Bit 4: TIM17EN.

SPI1EN

Bit 8: SPI1EN.

SPI4EN

Bit 9: SPI4EN.

SPI5EN

Bit 10: SPI5EN.

USART6EN

Bit 13: USART6EN.

SAI1EN

Bit 16: SAI1EN.

SAI2EN

Bit 17: SAI2EN.

SAI3EN

Bit 18: SAI3EN.

DFSDMEN

Bit 20: DFSDMEN.

ADFSDMEN

Bit 21: ADFSDMEN.

FDCANEN

Bit 24: FDCANEN.

MC_APB2ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xa8c, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANEN
rw 		ADFSDMEN
rw 		DFSDMEN
rw 		SAI3EN
rw 		SAI2EN
rw 		SAI1EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6EN
rw 		SPI5EN
rw 		SPI4EN
rw 		SPI1EN
rw 		TIM17EN
rw 		TIM16EN
rw 		TIM15EN
rw 		TIM8EN
rw 		TIM1EN
rw
Toggle fields

TIM1EN

Bit 0: TIM1EN.

TIM8EN

Bit 1: TIM8EN.

TIM15EN

Bit 2: TIM15EN.

TIM16EN

Bit 3: TIM16EN.

TIM17EN

Bit 4: TIM17EN.

SPI1EN

Bit 8: SPI1EN.

SPI4EN

Bit 9: SPI4EN.

SPI5EN

Bit 10: SPI5EN.

USART6EN

Bit 13: USART6EN.

SAI1EN

Bit 16: SAI1EN.

SAI2EN

Bit 17: SAI2EN.

SAI3EN

Bit 18: SAI3EN.

DFSDMEN

Bit 20: DFSDMEN.

ADFSDMEN

Bit 21: ADFSDMEN.

FDCANEN

Bit 24: FDCANEN.

MC_APB3ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa90, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDPEN
rw 		DTSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFEN
rw 		SYSCFGEN
rw 		SAI4EN
rw 		LPTIM5EN
rw 		LPTIM4EN
rw 		LPTIM3EN
rw 		LPTIM2EN
rw
Toggle fields

LPTIM2EN

Bit 0: LPTIM2EN.

LPTIM3EN

Bit 1: LPTIM3EN.

LPTIM4EN

Bit 2: LPTIM4EN.

LPTIM5EN

Bit 3: LPTIM5EN.

SAI4EN

Bit 8: SAI4EN.

SYSCFGEN

Bit 11: SYSCFGEN.

VREFEN

Bit 13: VREFEN.

DTSEN

Bit 16: DTSEN.

HDPEN

Bit 20: HDPEN.

MC_APB3ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xa94, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDPEN
rw 		DTSEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFEN
rw 		SYSCFGEN
rw 		SAI4EN
rw 		LPTIM5EN
rw 		LPTIM4EN
rw 		LPTIM3EN
rw 		LPTIM2EN
rw
Toggle fields

LPTIM2EN

Bit 0: LPTIM2EN.

LPTIM3EN

Bit 1: LPTIM3EN.

LPTIM4EN

Bit 2: LPTIM4EN.

LPTIM5EN

Bit 3: LPTIM5EN.

SAI4EN

Bit 8: SAI4EN.

SYSCFGEN

Bit 11: SYSCFGEN.

VREFEN

Bit 13: VREFEN.

DTSEN

Bit 16: DTSEN.

HDPEN

Bit 20: HDPEN.

MC_AHB2ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xa98, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOEN
rw 		ADC12EN
rw 		DMAMUXEN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1EN.

DMA2EN

Bit 1: DMA2EN.

DMAMUXEN

Bit 2: DMAMUXEN.

ADC12EN

Bit 5: ADC12EN.

USBOEN

Bit 8: USBOEN.

SDMMC3EN

Bit 16: SDMMC3EN.

MC_AHB2ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xa9c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOEN
rw 		ADC12EN
rw 		DMAMUXEN
rw 		DMA2EN
rw 		DMA1EN
rw
Toggle fields

DMA1EN

Bit 0: DMA1EN.

DMA2EN

Bit 1: DMA2EN.

DMAMUXEN

Bit 2: DMAMUXEN.

ADC12EN

Bit 5: ADC12EN.

USBOEN

Bit 8: USBOEN.

SDMMC3EN

Bit 16: SDMMC3EN.

MC_AHB3ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xaa0, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCEN
rw 		HSEMEN
rw 		CRC2EN
rw 		RNG2EN
rw 		HASH2EN
rw 		CRYP2EN
rw 		DCMIEN
rw
Toggle fields

DCMIEN

Bit 0: DCMIEN.

CRYP2EN

Bit 4: CRYP2EN.

HASH2EN

Bit 5: HASH2EN.

RNG2EN

Bit 6: RNG2EN.

CRC2EN

Bit 7: CRC2EN.

HSEMEN

Bit 11: HSEMEN.

IPCCEN

Bit 12: IPCCEN.

MC_AHB3ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xaa4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCEN
rw 		HSEMEN
rw 		CRC2EN
rw 		RNG2EN
rw 		HASH2EN
rw 		CRYP2EN
rw 		DCMIEN
rw
Toggle fields

DCMIEN

Bit 0: DCMIEN.

CRYP2EN

Bit 4: CRYP2EN.

HASH2EN

Bit 5: HASH2EN.

RNG2EN

Bit 6: RNG2EN.

CRC2EN

Bit 7: CRC2EN.

HSEMEN

Bit 11: HSEMEN.

IPCCEN

Bit 12: IPCCEN.

MC_AHB4ENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xaa8, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKEN
rw 		GPIOJEN
rw 		GPIOIEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: GPIOAEN.

GPIOBEN

Bit 1: GPIOBEN.

GPIOCEN

Bit 2: GPIOCEN.

GPIODEN

Bit 3: GPIODEN.

GPIOEEN

Bit 4: GPIOEEN.

GPIOFEN

Bit 5: GPIOFEN.

GPIOGEN

Bit 6: GPIOGEN.

GPIOHEN

Bit 7: GPIOHEN.

GPIOIEN

Bit 8: GPIOIEN.

GPIOJEN

Bit 9: GPIOJEN.

GPIOKEN

Bit 10: GPIOKEN.

MC_AHB4ENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xaac, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKEN
rw 		GPIOJEN
rw 		GPIOIEN
rw 		GPIOHEN
rw 		GPIOGEN
rw 		GPIOFEN
rw 		GPIOEEN
rw 		GPIODEN
rw 		GPIOCEN
rw 		GPIOBEN
rw 		GPIOAEN
rw
Toggle fields

GPIOAEN

Bit 0: GPIOAEN.

GPIOBEN

Bit 1: GPIOBEN.

GPIOCEN

Bit 2: GPIOCEN.

GPIODEN

Bit 3: GPIODEN.

GPIOEEN

Bit 4: GPIOEEN.

GPIOFEN

Bit 5: GPIOFEN.

GPIOGEN

Bit 6: GPIOGEN.

GPIOHEN

Bit 7: GPIOHEN.

GPIOIEN

Bit 8: GPIOIEN.

GPIOJEN

Bit 9: GPIOJEN.

GPIOKEN

Bit 10: GPIOKEN.

MC_AXIMENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xab0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRAMEN
rw
Toggle fields

SYSRAMEN

Bit 0: SYSRAMEN.

MC_AXIMENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xab4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRAMEN
rw
Toggle fields

SYSRAMEN

Bit 0: SYSRAMEN.

MC_MLAHBENSETR

This register is used to set the peripheral clock enable bit

Offset: 0xab8, size: 32, reset: 0x00000010, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMEN
rw
Toggle fields

RETRAMEN

Bit 4: RETRAMEN.

MC_MLAHBENCLRR

This register is used to clear the peripheral clock enable bit

Offset: 0xabc, size: 32, reset: 0x00000010, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMEN
rw
Toggle fields

RETRAMEN

Bit 4: RETRAMEN.

MP_APB1LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb00, size: 32, reset: 0xADEFDBFF, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSLPEN
rw 		DAC12LPEN
rw 		CECLPEN
rw 		SPDIFLPEN
rw 		I2C5LPEN
rw 		I2C3LPEN
rw 		I2C2LPEN
rw 		I2C1LPEN
rw 		UART8LPEN
rw 		UART7LPEN
rw 		UART5LPEN
rw 		UART4LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3LPEN
rw 		USART2LPEN
rw 		SPI3LPEN
rw 		SPI2LPEN
rw 		LPTIM1LPEN
rw 		TIM14LPEN
rw 		TIM13LPEN
rw 		TIM12LPEN
rw 		TIM7LPEN
rw 		TIM6LPEN
rw 		TIM5LPEN
rw 		TIM4LPEN
rw 		TIM3LPEN
rw 		TIM2LPEN
rw
Toggle fields

TIM2LPEN

Bit 0: TIM2LPEN.

TIM3LPEN

Bit 1: TIM3LPEN.

TIM4LPEN

Bit 2: TIM4LPEN.

TIM5LPEN

Bit 3: TIM5LPEN.

TIM6LPEN

Bit 4: TIM6LPEN.

TIM7LPEN

Bit 5: TIM7LPEN.

TIM12LPEN

Bit 6: TIM12LPEN.

TIM13LPEN

Bit 7: TIM13LPEN.

TIM14LPEN

Bit 8: TIM14LPEN.

LPTIM1LPEN

Bit 9: LPTIM1LPEN.

SPI2LPEN

Bit 11: SPI2LPEN.

SPI3LPEN

Bit 12: SPI3LPEN.

USART2LPEN

Bit 14: USART2LPEN.

USART3LPEN

Bit 15: USART3LPEN.

UART4LPEN

Bit 16: UART4LPEN.

UART5LPEN

Bit 17: UART5LPEN.

UART7LPEN

Bit 18: UART7LPEN.

UART8LPEN

Bit 19: UART8LPEN.

I2C1LPEN

Bit 21: I2C1LPEN.

I2C2LPEN

Bit 22: I2C2LPEN.

I2C3LPEN

Bit 23: I2C3LPEN.

I2C5LPEN

Bit 24: I2C5LPEN.

SPDIFLPEN

Bit 26: SPDIFLPEN.

CECLPEN

Bit 27: CECLPEN.

DAC12LPEN

Bit 29: DAC12LPEN.

MDIOSLPEN

Bit 31: MDIOSLPEN.

MP_APB1LPENCLRR

This register is used by the MPU in order to clear the PERxLPEN bits .

Offset: 0xb04, size: 32, reset: 0xADEFDBFF, access: read-write

0/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSLPEN
rw 		DAC12LPEN
rw 		CECLPEN
rw 		SPDIFLPEN
rw 		I2C5LPEN
rw 		I2C3LPEN
rw 		I2C2LPEN
rw 		I2C1LPEN
rw 		UART8LPEN
rw 		UART7LPEN
rw 		UART5LPEN
rw 		UART4LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3LPEN
rw 		USART2LPEN
rw 		SPI3LPEN
rw 		SPI2LPEN
rw 		LPTIM1LPEN
rw 		TIM14LPEN
rw 		TIM13LPEN
rw 		TIM12LPEN
rw 		TIM7LPEN
rw 		TIM6LPEN
rw 		TIM5LPEN
rw 		TIM4LPEN
rw 		TIM3LPEN
rw 		TIM2LPEN
rw
Toggle fields

TIM2LPEN

Bit 0: TIM2LPEN.

TIM3LPEN

Bit 1: TIM3LPEN.

TIM4LPEN

Bit 2: TIM4LPEN.

TIM5LPEN

Bit 3: TIM5LPEN.

TIM6LPEN

Bit 4: TIM6LPEN.

TIM7LPEN

Bit 5: TIM7LPEN.

TIM12LPEN

Bit 6: TIM12LPEN.

TIM13LPEN

Bit 7: TIM13LPEN.

TIM14LPEN

Bit 8: TIM14LPEN.

LPTIM1LPEN

Bit 9: LPTIM1LPEN.

SPI2LPEN

Bit 11: SPI2LPEN.

SPI3LPEN

Bit 12: SPI3LPEN.

USART2LPEN

Bit 14: USART2LPEN.

USART3LPEN

Bit 15: USART3LPEN.

UART4LPEN

Bit 16: UART4LPEN.

UART5LPEN

Bit 17: UART5LPEN.

UART7LPEN

Bit 18: UART7LPEN.

UART8LPEN

Bit 19: UART8LPEN.

I2C1LPEN

Bit 21: I2C1LPEN.

I2C2LPEN

Bit 22: I2C2LPEN.

I2C3LPEN

Bit 23: I2C3LPEN.

I2C5LPEN

Bit 24: I2C5LPEN.

SPDIFLPEN

Bit 26: SPDIFLPEN.

CECLPEN

Bit 27: CECLPEN.

DAC12LPEN

Bit 29: DAC12LPEN.

MDIOSLPEN

Bit 31: MDIOSLPEN.

MP_APB2LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb08, size: 32, reset: 0x0137271F, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANLPEN
rw 		ADFSDMLPEN
rw 		DFSDMLPEN
rw 		SAI3LPEN
rw 		SAI2LPEN
rw 		SAI1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6LPEN
rw 		SPI5LPEN
rw 		SPI4LPEN
rw 		SPI1LPEN
rw 		TIM17LPEN
rw 		TIM16LPEN
rw 		TIM15LPEN
rw 		TIM8LPEN
rw 		TIM1LPEN
rw
Toggle fields

TIM1LPEN

Bit 0: TIM1LPEN.

TIM8LPEN

Bit 1: TIM8LPEN.

TIM15LPEN

Bit 2: TIM15LPEN.

TIM16LPEN

Bit 3: TIM16LPEN.

TIM17LPEN

Bit 4: TIM17LPEN.

SPI1LPEN

Bit 8: SPI1LPEN.

SPI4LPEN

Bit 9: SPI4LPEN.

SPI5LPEN

Bit 10: SPI5LPEN.

USART6LPEN

Bit 13: USART6LPEN.

SAI1LPEN

Bit 16: SAI1LPEN.

SAI2LPEN

Bit 17: SAI2LPEN.

SAI3LPEN

Bit 18: SAI3LPEN.

DFSDMLPEN

Bit 20: DFSDMLPEN.

ADFSDMLPEN

Bit 21: ADFSDMLPEN.

FDCANLPEN

Bit 24: FDCANLPEN.

MP_APB2LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb0c, size: 32, reset: 0x0137271F, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANLPEN
rw 		ADFSDMLPEN
rw 		DFSDMLPEN
rw 		SAI3LPEN
rw 		SAI2LPEN
rw 		SAI1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6LPEN
rw 		SPI5LPEN
rw 		SPI4LPEN
rw 		SPI1LPEN
rw 		TIM17LPEN
rw 		TIM16LPEN
rw 		TIM15LPEN
rw 		TIM8LPEN
rw 		TIM1LPEN
rw
Toggle fields

TIM1LPEN

Bit 0: TIM1LPEN.

TIM8LPEN

Bit 1: TIM8LPEN.

TIM15LPEN

Bit 2: TIM15LPEN.

TIM16LPEN

Bit 3: TIM16LPEN.

TIM17LPEN

Bit 4: TIM17LPEN.

SPI1LPEN

Bit 8: SPI1LPEN.

SPI4LPEN

Bit 9: SPI4LPEN.

SPI5LPEN

Bit 10: SPI5LPEN.

USART6LPEN

Bit 13: USART6LPEN.

SAI1LPEN

Bit 16: SAI1LPEN.

SAI2LPEN

Bit 17: SAI2LPEN.

SAI3LPEN

Bit 18: SAI3LPEN.

DFSDMLPEN

Bit 20: DFSDMLPEN.

ADFSDMLPEN

Bit 21: ADFSDMLPEN.

FDCANLPEN

Bit 24: FDCANLPEN.

MP_APB3LPENSETR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb10, size: 32, reset: 0x0003290F, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFLPEN
rw 		SYSCFGLPEN
rw 		SAI4LPEN
rw 		LPTIM5LPEN
rw 		LPTIM4LPEN
rw 		LPTIM3LPEN
rw 		LPTIM2LPEN
rw
Toggle fields

LPTIM2LPEN

Bit 0: LPTIM2LPEN.

LPTIM3LPEN

Bit 1: LPTIM3LPEN.

LPTIM4LPEN

Bit 2: LPTIM4LPEN.

LPTIM5LPEN

Bit 3: LPTIM5LPEN.

SAI4LPEN

Bit 8: SAI4LPEN.

SYSCFGLPEN

Bit 11: SYSCFGLPEN.

VREFLPEN

Bit 13: VREFLPEN.

DTSLPEN

Bit 16: DTSLPEN.

MP_APB3LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb14, size: 32, reset: 0x0003290F, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFLPEN
rw 		SYSCFGLPEN
rw 		SAI4LPEN
rw 		LPTIM5LPEN
rw 		LPTIM4LPEN
rw 		LPTIM3LPEN
rw 		LPTIM2LPEN
rw
Toggle fields

LPTIM2LPEN

Bit 0: LPTIM2LPEN.

LPTIM3LPEN

Bit 1: LPTIM3LPEN.

LPTIM4LPEN

Bit 2: LPTIM4LPEN.

LPTIM5LPEN

Bit 3: LPTIM5LPEN.

SAI4LPEN

Bit 8: SAI4LPEN.

SYSCFGLPEN

Bit 11: SYSCFGLPEN.

VREFLPEN

Bit 13: VREFLPEN.

DTSLPEN

Bit 16: DTSLPEN.

MP_AHB2LPENSETR

This register is used by the MPU in order to set the PERxLPEN bit.

Offset: 0xb18, size: 32, reset: 0x00010127, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOLPEN
rw 		ADC12LPEN
rw 		DMAMUXLPEN
rw 		DMA2LPEN
rw 		DMA1LPEN
rw
Toggle fields

DMA1LPEN

Bit 0: DMA1LPEN.

DMA2LPEN

Bit 1: DMA2LPEN.

DMAMUXLPEN

Bit 2: DMAMUXLPEN.

ADC12LPEN

Bit 5: ADC12LPEN.

USBOLPEN

Bit 8: USBOLPEN.

SDMMC3LPEN

Bit 16: SDMMC3LPEN.

MP_AHB2LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb1c, size: 32, reset: 0x00010127, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOLPEN
rw 		ADC12LPEN
rw 		DMAMUXLPEN
rw 		DMA2LPEN
rw 		DMA1LPEN
rw
Toggle fields

DMA1LPEN

Bit 0: DMA1LPEN.

DMA2LPEN

Bit 1: DMA2LPEN.

DMAMUXLPEN

Bit 2: DMAMUXLPEN.

ADC12LPEN

Bit 5: ADC12LPEN.

USBOLPEN

Bit 8: USBOLPEN.

SDMMC3LPEN

Bit 16: SDMMC3LPEN.

MP_AHB3LPENSETR

This register is used by the MPU

Offset: 0xb20, size: 32, reset: 0x000018F1, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCLPEN
rw 		HSEMLPEN
rw 		CRC2LPEN
rw 		RNG2LPEN
rw 		HASH2LPEN
rw 		CRYP2LPEN
rw 		DCMILPEN
rw
Toggle fields

DCMILPEN

Bit 0: DCMILPEN.

CRYP2LPEN

Bit 4: CRYP2LPEN.

HASH2LPEN

Bit 5: HASH2LPEN.

RNG2LPEN

Bit 6: RNG2LPEN.

CRC2LPEN

Bit 7: CRC2LPEN.

HSEMLPEN

Bit 11: HSEMLPEN.

IPCCLPEN

Bit 12: IPCCLPEN.

MP_AHB3LPENCLRR

This register is used by the MPU in order to clear the PERxLPEN bit

Offset: 0xb24, size: 32, reset: 0x000018F1, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCLPEN
rw 		HSEMLPEN
rw 		CRC2LPEN
rw 		RNG2LPEN
rw 		HASH2LPEN
rw 		CRYP2LPEN
rw 		DCMILPEN
rw
Toggle fields

DCMILPEN

Bit 0: DCMILPEN.

CRYP2LPEN

Bit 4: CRYP2LPEN.

HASH2LPEN

Bit 5: HASH2LPEN.

RNG2LPEN

Bit 6: RNG2LPEN.

CRC2LPEN

Bit 7: CRC2LPEN.

HSEMLPEN

Bit 11: HSEMLPEN.

IPCCLPEN

Bit 12: IPCCLPEN.

MP_AHB4LPENSETR

This register is used by the MPU

Offset: 0xb28, size: 32, reset: 0x000007FF, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKLPEN
rw 		GPIOJLPEN
rw 		GPIOILPEN
rw 		GPIOHLPEN
rw 		GPIOGLPEN
rw 		GPIOFLPEN
rw 		GPIOELPEN
rw 		GPIODLPEN
rw 		GPIOCLPEN
rw 		GPIOBLPEN
rw 		GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: GPIOALPEN.

GPIOBLPEN

Bit 1: GPIOBLPEN.

GPIOCLPEN

Bit 2: GPIOCLPEN.

GPIODLPEN

Bit 3: GPIODLPEN.

GPIOELPEN

Bit 4: GPIOELPEN.

GPIOFLPEN

Bit 5: GPIOFLPEN.

GPIOGLPEN

Bit 6: GPIOGLPEN.

GPIOHLPEN

Bit 7: GPIOHLPEN.

GPIOILPEN

Bit 8: GPIOILPEN.

GPIOJLPEN

Bit 9: GPIOJLPEN.

GPIOKLPEN

Bit 10: GPIOKLPEN.

MP_AHB4LPENCLRR

This register is used by the MPU

Offset: 0xb2c, size: 32, reset: 0x000007FF, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKLPEN
rw 		GPIOJLPEN
rw 		GPIOILPEN
rw 		GPIOHLPEN
rw 		GPIOGLPEN
rw 		GPIOFLPEN
rw 		GPIOELPEN
rw 		GPIODLPEN
rw 		GPIOCLPEN
rw 		GPIOBLPEN
rw 		GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: GPIOALPEN.

GPIOBLPEN

Bit 1: GPIOBLPEN.

GPIOCLPEN

Bit 2: GPIOCLPEN.

GPIODLPEN

Bit 3: GPIODLPEN.

GPIOELPEN

Bit 4: GPIOELPEN.

GPIOFLPEN

Bit 5: GPIOFLPEN.

GPIOGLPEN

Bit 6: GPIOGLPEN.

GPIOHLPEN

Bit 7: GPIOHLPEN.

GPIOILPEN

Bit 8: GPIOILPEN.

GPIOJLPEN

Bit 9: GPIOJLPEN.

GPIOKLPEN

Bit 10: GPIOKLPEN.

MP_AXIMLPENSETR

This register is used by the MPU

Offset: 0xb30, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRAMLPEN
rw
Toggle fields

SYSRAMLPEN

Bit 0: SYSRAMLPEN.

MP_AXIMLPENCLRR

This register is used by the MPU

Offset: 0xb34, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRAMLPEN
rw
Toggle fields

SYSRAMLPEN

Bit 0: SYSRAMLPEN.

MP_MLAHBLPENSETR

This register is used by the MPU in order to set the PERxLPEN bit

Offset: 0xb38, size: 32, reset: 0x00000017, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMLPEN
rw 		SRAM34LPEN
rw 		SRAM2LPEN
rw 		SRAM1LPEN
rw
Toggle fields

SRAM1LPEN

Bit 0: SRAM1LPEN.

SRAM2LPEN

Bit 1: SRAM2LPEN.

SRAM34LPEN

Bit 2: SRAM34LPEN.

RETRAMLPEN

Bit 4: RETRAMLPEN.

MP_MLAHBLPENCLRR

This register is used by the MPU in order to clear the PERxLPEN bit

Offset: 0xb3c, size: 32, reset: 0x00000017, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMLPEN
rw 		SRAM34LPEN
rw 		SRAM2LPEN
rw 		SRAM1LPEN
rw
Toggle fields

SRAM1LPEN

Bit 0: SRAM1LPEN.

SRAM2LPEN

Bit 1: SRAM2LPEN.

SRAM34LPEN

Bit 2: SRAM34LPEN.

RETRAMLPEN

Bit 4: RETRAMLPEN.

MC_APB1LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0xb80, size: 32, reset: 0xBDEFDBFF, access: read-write

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSLPEN
rw 		DAC12LPEN
rw 		WWDG1LPEN
rw 		CECLPEN
rw 		SPDIFLPEN
rw 		I2C5LPEN
rw 		I2C3LPEN
rw 		I2C2LPEN
rw 		I2C1LPEN
rw 		UART8LPEN
rw 		UART7LPEN
rw 		UART5LPEN
rw 		UART4LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3LPEN
rw 		USART2LPEN
rw 		SPI3LPEN
rw 		SPI2LPEN
rw 		LPTIM1LPEN
rw 		TIM14LPEN
rw 		TIM13LPEN
rw 		TIM12LPEN
rw 		TIM7LPEN
rw 		TIM6LPEN
rw 		TIM5LPEN
rw 		TIM4LPEN
rw 		TIM3LPEN
rw 		TIM2LPEN
rw
Toggle fields

TIM2LPEN

Bit 0: TIM2LPEN.

TIM3LPEN

Bit 1: TIM3LPEN.

TIM4LPEN

Bit 2: TIM4LPEN.

TIM5LPEN

Bit 3: TIM5LPEN.

TIM6LPEN

Bit 4: TIM6LPEN.

TIM7LPEN

Bit 5: TIM7LPEN.

TIM12LPEN

Bit 6: TIM12LPEN.

TIM13LPEN

Bit 7: TIM13LPEN.

TIM14LPEN

Bit 8: TIM14LPEN.

LPTIM1LPEN

Bit 9: LPTIM1LPEN.

SPI2LPEN

Bit 11: SPI2LPEN.

SPI3LPEN

Bit 12: SPI3LPEN.

USART2LPEN

Bit 14: USART2LPEN.

USART3LPEN

Bit 15: USART3LPEN.

UART4LPEN

Bit 16: UART4LPEN.

UART5LPEN

Bit 17: UART5LPEN.

UART7LPEN

Bit 18: UART7LPEN.

UART8LPEN

Bit 19: UART8LPEN.

I2C1LPEN

Bit 21: I2C1LPEN.

I2C2LPEN

Bit 22: I2C2LPEN.

I2C3LPEN

Bit 23: I2C3LPEN.

I2C5LPEN

Bit 24: I2C5LPEN.

SPDIFLPEN

Bit 26: SPDIFLPEN.

CECLPEN

Bit 27: CECLPEN.

WWDG1LPEN

Bit 28: WWDG1LPEN.

DAC12LPEN

Bit 29: DAC12LPEN.

MDIOSLPEN

Bit 31: MDIOSLPEN.

MC_APB1LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bits

Offset: 0xb84, size: 32, reset: 0xBDEFDBFF, access: read-write

0/27 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MDIOSLPEN
rw 		DAC12LPEN
rw 		WWDG1LPEN
rw 		CECLPEN
rw 		SPDIFLPEN
rw 		I2C5LPEN
rw 		I2C3LPEN
rw 		I2C2LPEN
rw 		I2C1LPEN
rw 		UART8LPEN
rw 		UART7LPEN
rw 		UART5LPEN
rw 		UART4LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3LPEN
rw 		USART2LPEN
rw 		SPI3LPEN
rw 		SPI2LPEN
rw 		LPTIM1LPEN
rw 		TIM14LPEN
rw 		TIM13LPEN
rw 		TIM12LPEN
rw 		TIM7LPEN
rw 		TIM6LPEN
rw 		TIM5LPEN
rw 		TIM4LPEN
rw 		TIM3LPEN
rw 		TIM2LPEN
rw
Toggle fields

TIM2LPEN

Bit 0: TIM2LPEN.

TIM3LPEN

Bit 1: TIM3LPEN.

TIM4LPEN

Bit 2: TIM4LPEN.

TIM5LPEN

Bit 3: TIM5LPEN.

TIM6LPEN

Bit 4: TIM6LPEN.

TIM7LPEN

Bit 5: TIM7LPEN.

TIM12LPEN

Bit 6: TIM12LPEN.

TIM13LPEN

Bit 7: TIM13LPEN.

TIM14LPEN

Bit 8: TIM14LPEN.

LPTIM1LPEN

Bit 9: LPTIM1LPEN.

SPI2LPEN

Bit 11: SPI2LPEN.

SPI3LPEN

Bit 12: SPI3LPEN.

USART2LPEN

Bit 14: USART2LPEN.

USART3LPEN

Bit 15: USART3LPEN.

UART4LPEN

Bit 16: UART4LPEN.

UART5LPEN

Bit 17: UART5LPEN.

UART7LPEN

Bit 18: UART7LPEN.

UART8LPEN

Bit 19: UART8LPEN.

I2C1LPEN

Bit 21: I2C1LPEN.

I2C2LPEN

Bit 22: I2C2LPEN.

I2C3LPEN

Bit 23: I2C3LPEN.

I2C5LPEN

Bit 24: I2C5LPEN.

SPDIFLPEN

Bit 26: SPDIFLPEN.

CECLPEN

Bit 27: CECLPEN.

WWDG1LPEN

Bit 28: WWDG1LPEN.

DAC12LPEN

Bit 29: DAC12LPEN.

MDIOSLPEN

Bit 31: MDIOSLPEN.

MC_APB2LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0xb88, size: 32, reset: 0x0137271F, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANLPEN
rw 		ADFSDMLPEN
rw 		DFSDMLPEN
rw 		SAI3LPEN
rw 		SAI2LPEN
rw 		SAI1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6LPEN
rw 		SPI5LPEN
rw 		SPI4LPEN
rw 		SPI1LPEN
rw 		TIM17LPEN
rw 		TIM16LPEN
rw 		TIM15LPEN
rw 		TIM8LPEN
rw 		TIM1LPEN
rw
Toggle fields

TIM1LPEN

Bit 0: TIM1LPEN.

TIM8LPEN

Bit 1: TIM8LPEN.

TIM15LPEN

Bit 2: TIM15LPEN.

TIM16LPEN

Bit 3: TIM16LPEN.

TIM17LPEN

Bit 4: TIM17LPEN.

SPI1LPEN

Bit 8: SPI1LPEN.

SPI4LPEN

Bit 9: SPI4LPEN.

SPI5LPEN

Bit 10: SPI5LPEN.

USART6LPEN

Bit 13: USART6LPEN.

SAI1LPEN

Bit 16: SAI1LPEN.

SAI2LPEN

Bit 17: SAI2LPEN.

SAI3LPEN

Bit 18: SAI3LPEN.

DFSDMLPEN

Bit 20: DFSDMLPEN.

ADFSDMLPEN

Bit 21: ADFSDMLPEN.

FDCANLPEN

Bit 24: FDCANLPEN.

MC_APB2LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0xb8c, size: 32, reset: 0x0137271F, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FDCANLPEN
rw 		ADFSDMLPEN
rw 		DFSDMLPEN
rw 		SAI3LPEN
rw 		SAI2LPEN
rw 		SAI1LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART6LPEN
rw 		SPI5LPEN
rw 		SPI4LPEN
rw 		SPI1LPEN
rw 		TIM17LPEN
rw 		TIM16LPEN
rw 		TIM15LPEN
rw 		TIM8LPEN
rw 		TIM1LPEN
rw
Toggle fields

TIM1LPEN

Bit 0: TIM1LPEN.

TIM8LPEN

Bit 1: TIM8LPEN.

TIM15LPEN

Bit 2: TIM15LPEN.

TIM16LPEN

Bit 3: TIM16LPEN.

TIM17LPEN

Bit 4: TIM17LPEN.

SPI1LPEN

Bit 8: SPI1LPEN.

SPI4LPEN

Bit 9: SPI4LPEN.

SPI5LPEN

Bit 10: SPI5LPEN.

USART6LPEN

Bit 13: USART6LPEN.

SAI1LPEN

Bit 16: SAI1LPEN.

SAI2LPEN

Bit 17: SAI2LPEN.

SAI3LPEN

Bit 18: SAI3LPEN.

DFSDMLPEN

Bit 20: DFSDMLPEN.

ADFSDMLPEN

Bit 21: ADFSDMLPEN.

FDCANLPEN

Bit 24: FDCANLPEN.

MC_APB3LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0xb90, size: 32, reset: 0x0003290F, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFLPEN
rw 		SYSCFGLPEN
rw 		SAI4LPEN
rw 		LPTIM5LPEN
rw 		LPTIM4LPEN
rw 		LPTIM3LPEN
rw 		LPTIM2LPEN
rw
Toggle fields

LPTIM2LPEN

Bit 0: LPTIM2LPEN.

LPTIM3LPEN

Bit 1: LPTIM3LPEN.

LPTIM4LPEN

Bit 2: LPTIM4LPEN.

LPTIM5LPEN

Bit 3: LPTIM5LPEN.

SAI4LPEN

Bit 8: SAI4LPEN.

SYSCFGLPEN

Bit 11: SYSCFGLPEN.

VREFLPEN

Bit 13: VREFLPEN.

DTSLPEN

Bit 16: DTSLPEN.

MC_APB3LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0xb94, size: 32, reset: 0x0003290F, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DTSLPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFLPEN
rw 		SYSCFGLPEN
rw 		SAI4LPEN
rw 		LPTIM5LPEN
rw 		LPTIM4LPEN
rw 		LPTIM3LPEN
rw 		LPTIM2LPEN
rw
Toggle fields

LPTIM2LPEN

Bit 0: LPTIM2LPEN.

LPTIM3LPEN

Bit 1: LPTIM3LPEN.

LPTIM4LPEN

Bit 2: LPTIM4LPEN.

LPTIM5LPEN

Bit 3: LPTIM5LPEN.

SAI4LPEN

Bit 8: SAI4LPEN.

SYSCFGLPEN

Bit 11: SYSCFGLPEN.

VREFLPEN

Bit 13: VREFLPEN.

DTSLPEN

Bit 16: DTSLPEN.

MC_AHB2LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0xb98, size: 32, reset: 0x00010127, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOLPEN
rw 		ADC12LPEN
rw 		DMAMUXLPEN
rw 		DMA2LPEN
rw 		DMA1LPEN
rw
Toggle fields

DMA1LPEN

Bit 0: DMA1LPEN.

DMA2LPEN

Bit 1: DMA2LPEN.

DMAMUXLPEN

Bit 2: DMAMUXLPEN.

ADC12LPEN

Bit 5: ADC12LPEN.

USBOLPEN

Bit 8: USBOLPEN.

SDMMC3LPEN

Bit 16: SDMMC3LPEN.

MC_AHB2LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0xb9c, size: 32, reset: 0x00010127, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDMMC3LPEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USBOLPEN
rw 		ADC12LPEN
rw 		DMAMUXLPEN
rw 		DMA2LPEN
rw 		DMA1LPEN
rw
Toggle fields

DMA1LPEN

Bit 0: DMA1LPEN.

DMA2LPEN

Bit 1: DMA2LPEN.

DMAMUXLPEN

Bit 2: DMAMUXLPEN.

ADC12LPEN

Bit 5: ADC12LPEN.

USBOLPEN

Bit 8: USBOLPEN.

SDMMC3LPEN

Bit 16: SDMMC3LPEN.

MC_AHB3LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0xba0, size: 32, reset: 0x000018F1, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCLPEN
rw 		HSEMLPEN
rw 		CRC2LPEN
rw 		RNG2LPEN
rw 		HASH2LPEN
rw 		CRYP2LPEN
rw 		DCMILPEN
rw
Toggle fields

DCMILPEN

Bit 0: DCMILPEN.

CRYP2LPEN

Bit 4: CRYP2LPEN.

HASH2LPEN

Bit 5: HASH2LPEN.

RNG2LPEN

Bit 6: RNG2LPEN.

CRC2LPEN

Bit 7: CRC2LPEN.

HSEMLPEN

Bit 11: HSEMLPEN.

IPCCLPEN

Bit 12: IPCCLPEN.

MC_AHB3LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit

Offset: 0xba4, size: 32, reset: 0x000018F1, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPCCLPEN
rw 		HSEMLPEN
rw 		CRC2LPEN
rw 		RNG2LPEN
rw 		HASH2LPEN
rw 		CRYP2LPEN
rw 		DCMILPEN
rw
Toggle fields

DCMILPEN

Bit 0: DCMILPEN.

CRYP2LPEN

Bit 4: CRYP2LPEN.

HASH2LPEN

Bit 5: HASH2LPEN.

RNG2LPEN

Bit 6: RNG2LPEN.

CRC2LPEN

Bit 7: CRC2LPEN.

HSEMLPEN

Bit 11: HSEMLPEN.

IPCCLPEN

Bit 12: IPCCLPEN.

MC_AHB4LPENSETR

This register is used by the MCU in order to set the PERxLPEN bit.

Offset: 0xba8, size: 32, reset: 0x000007FF, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKLPEN
rw 		GPIOJLPEN
rw 		GPIOILPEN
rw 		GPIOHLPEN
rw 		GPIOGLPEN
rw 		GPIOFLPEN
rw 		GPIOELPEN
rw 		GPIODLPEN
rw 		GPIOCLPEN
rw 		GPIOBLPEN
rw 		GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: GPIOALPEN.

GPIOBLPEN

Bit 1: GPIOBLPEN.

GPIOCLPEN

Bit 2: GPIOCLPEN.

GPIODLPEN

Bit 3: GPIODLPEN.

GPIOELPEN

Bit 4: GPIOELPEN.

GPIOFLPEN

Bit 5: GPIOFLPEN.

GPIOGLPEN

Bit 6: GPIOGLPEN.

GPIOHLPEN

Bit 7: GPIOHLPEN.

GPIOILPEN

Bit 8: GPIOILPEN.

GPIOJLPEN

Bit 9: GPIOJLPEN.

GPIOKLPEN

Bit 10: GPIOKLPEN.

MC_AHB4LPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.

Offset: 0xbac, size: 32, reset: 0x000007FF, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOKLPEN
rw 		GPIOJLPEN
rw 		GPIOILPEN
rw 		GPIOHLPEN
rw 		GPIOGLPEN
rw 		GPIOFLPEN
rw 		GPIOELPEN
rw 		GPIODLPEN
rw 		GPIOCLPEN
rw 		GPIOBLPEN
rw 		GPIOALPEN
rw
Toggle fields

GPIOALPEN

Bit 0: GPIOALPEN.

GPIOBLPEN

Bit 1: GPIOBLPEN.

GPIOCLPEN

Bit 2: GPIOCLPEN.

GPIODLPEN

Bit 3: GPIODLPEN.

GPIOELPEN

Bit 4: GPIOELPEN.

GPIOFLPEN

Bit 5: GPIOFLPEN.

GPIOGLPEN

Bit 6: GPIOGLPEN.

GPIOHLPEN

Bit 7: GPIOHLPEN.

GPIOILPEN

Bit 8: GPIOILPEN.

GPIOJLPEN

Bit 9: GPIOJLPEN.

GPIOKLPEN

Bit 10: GPIOKLPEN.

MC_AXIMLPENSETR

This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.

Offset: 0xbb0, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRAMLPEN
rw
Toggle fields

SYSRAMLPEN

Bit 0: SYSRAMLPEN.

MC_AXIMLPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.

Offset: 0xbb4, size: 32, reset: 0x00000001, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSRAMLPEN
rw
Toggle fields

SYSRAMLPEN

Bit 0: SYSRAMLPEN.

MC_MLAHBLPENSETR

This register is used by the MCU in order to set the PERxLPEN bit of the corresponding peripheral.

Offset: 0xbb8, size: 32, reset: 0x00000017, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMLPEN
rw 		SRAM34LPEN
rw 		SRAM2LPEN
rw 		SRAM1LPEN
rw
Toggle fields

SRAM1LPEN

Bit 0: SRAM1LPEN.

SRAM2LPEN

Bit 1: SRAM2LPEN.

SRAM34LPEN

Bit 2: SRAM34LPEN.

RETRAMLPEN

Bit 4: RETRAMLPEN.

MC_MLAHBLPENCLRR

This register is used by the MCU in order to clear the PERxLPEN bit of the corresponding peripheral.

Offset: 0xbbc, size: 32, reset: 0x00000017, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RETRAMLPEN
rw 		SRAM34LPEN
rw 		SRAM2LPEN
rw 		SRAM1LPEN
rw
Toggle fields

SRAM1LPEN

Bit 0: SRAM1LPEN.

SRAM2LPEN

Bit 1: SRAM2LPEN.

SRAM34LPEN

Bit 2: SRAM34LPEN.

RETRAMLPEN

Bit 4: RETRAMLPEN.

MC_RSTSCLRR

This register is used by the MCU to check the reset source.

Offset: 0xc00, size: 32, reset: 0x00000015, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WWDG1RSTF
rw 		IWDG2RSTF
rw 		IWDG1RSTF
rw 		MCSYSRSTF
rw 		MPSYSRSTF
rw 		MCURSTF
rw 		VCORERSTF
rw 		HCSSRSTF
rw 		PADRSTF
rw 		BORRSTF
rw 		PORRSTF
rw
Toggle fields

PORRSTF

Bit 0: PORRSTF.

BORRSTF

Bit 1: BORRSTF.

PADRSTF

Bit 2: PADRSTF.

HCSSRSTF

Bit 3: HCSSRSTF.

VCORERSTF

Bit 4: VCORERSTF.

MCURSTF

Bit 5: MCURSTF.

MPSYSRSTF

Bit 6: MPSYSRSTF.

MCSYSRSTF

Bit 7: MCSYSRSTF.

IWDG1RSTF

Bit 8: IWDG1RSTF.

IWDG2RSTF

Bit 9: IWDG2RSTF.

WWDG1RSTF

Bit 10: WWDG1RSTF.

MC_CIER

This register shall be used by the MCU to control the interrupt source enable. Refer to Section10.5: RCC interrupts for more details.

Offset: 0xc14, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPIE
rw 		LSECSSIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4DYIE
rw 		PLL3DYIE
rw 		PLL2DYIE
rw 		PLL1DYIE
rw 		CSIRDYIE
rw 		HSERDYIE
rw 		HSIRDYIE
rw 		LSERDYIE
rw 		LSIRDYIE
rw
Toggle fields

LSIRDYIE

Bit 0: LSIRDYIE.

LSERDYIE

Bit 1: LSERDYIE.

HSIRDYIE

Bit 2: HSIRDYIE.

HSERDYIE

Bit 3: HSERDYIE.

CSIRDYIE

Bit 4: CSIRDYIE.

PLL1DYIE

Bit 8: PLL1DYIE.

PLL2DYIE

Bit 9: PLL2DYIE.

PLL3DYIE

Bit 10: PLL3DYIE.

PLL4DYIE

Bit 11: PLL4DYIE.

LSECSSIE

Bit 16: LSECSSIE.

WKUPIE

Bit 20: WKUPIE.

MC_CIFR

This register shall be used by the MCU in order to read and clear the interrupt flags.

Offset: 0xc18, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUPF
rw 		LSECSSF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL4DYF
rw 		PLL3DYF
rw 		PLL2DYF
rw 		PLL1DYF
rw 		CSIRDYF
rw 		HSERDYF
rw 		HSIRDYF
rw 		LSERDYF
rw 		LSIRDYF
rw
Toggle fields

LSIRDYF

Bit 0: LSIRDYF.

LSERDYF

Bit 1: LSERDYF.

HSIRDYF

Bit 2: HSIRDYF.

HSERDYF

Bit 3: HSERDYF.

CSIRDYF

Bit 4: CSIRDYF.

PLL1DYF

Bit 8: PLL1DYF.

PLL2DYF

Bit 9: PLL2DYF.

PLL3DYF

Bit 10: PLL3DYF.

PLL4DYF

Bit 11: PLL4DYF.

LSECSSF

Bit 16: LSECSSF.

WKUPF

Bit 20: WKUPF.

VERR

This register gives the IP version

Offset: 0xff4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IDR

This register gives the unique identifier of the RCC

Offset: 0xff8, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

This register gives the decoding space, which is for the RCC of 4 kB.

Offset: 0xffc, size: 32, reset: 0xA3C5DD04, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

RNG1

0x54003000: RNG1

8/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CED
rw 		IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: RNGEN.

IE

Bit 3: IE.

CED

Bit 5: CED.

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: DRDY.

CECS

Bit 1: CECS.

SECS

Bit 2: SECS.

CEIS

Bit 5: CEIS.

SEIS

Bit 6: SEIS.

DR

The RNG_DR register is a read-only register.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: RNDATA.

HWCFGR

RNG hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000006, access: read-only

Toggle fields

VERR

RNG version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

RNG identification register

Offset: 0x3f8, size: 32, reset: 0x00170041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

RNG size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

RNG2

0x4c003000: RNG1

8/13 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 SR
0x8 DR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

RNG control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CED
rw 		IE
rw 		RNGEN
rw
Toggle fields

RNGEN

Bit 2: RNGEN.

IE

Bit 3: IE.

CED

Bit 5: CED.

SR

RNG status register

Offset: 0x4, size: 32, reset: 0x00000000, access: Unspecified

3/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEIS
rw 		CEIS
rw 		SECS
r 		CECS
r 		DRDY
r
Toggle fields

DRDY

Bit 0: DRDY.

CECS

Bit 1: CECS.

SECS

Bit 2: SECS.

CEIS

Bit 5: CEIS.

SEIS

Bit 6: SEIS.

DR

The RNG_DR register is a read-only register.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA
r
Toggle fields

RNDATA

Bits 0-31: RNDATA.

HWCFGR

RNG hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000006, access: read-only

Toggle fields

VERR

RNG version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

RNG identification register

Offset: 0x3f8, size: 32, reset: 0x00170041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

RNG size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

RTC

0x5c004000: RTC

139/150 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 TR
0x4 DR
0x8 SSR
0xc ICSR
0x10 PRER
0x14 WUTR
0x18 CR
0x20 SMCR
0x24 WPR
0x28 CALR
0x2c SHIFTR
0x30 TSTR
0x34 TSDR
0x38 TSSSR
0x40 ALRM[A]R
0x44 ALRM[A]SSR
0x48 ALRM[B]R
0x4c ALRM[B]SSR
0x50 SR
0x54 MISR
0x58 SMISR
0x5c SCR
0x60 CFGR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

TR

The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: SU.

Allowed values: 0x0-0xf

ST

Bits 4-6: ST.

Allowed values: 0x0-0x7

MNU

Bits 8-11: MNU.

Allowed values: 0x0-0xf

MNT

Bits 12-14: MNT.

Allowed values: 0x0-0x7

HU

Bits 16-19: HU.

Allowed values: 0x0-0xf

HT

Bits 20-21: HT.

Allowed values: 0x0-0x3

PM

Bit 22: PM.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

DR

The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page1830 and Reading the calendar on page1831. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x4, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: DU.

Allowed values: 0x0-0xf

DT

Bits 4-5: DT.

Allowed values: 0x0-0x3

MU

Bits 8-11: MU.

Allowed values: 0x0-0xf

MT

Bit 12: MT.

Allowed values: 0x0-0x1

WDU

Bits 13-15: WDU.

Allowed values: 0x1-0x7

YU

Bits 16-19: YU.

Allowed values: 0x0-0xf

YT

Bits 20-23: YT.

Allowed values: 0x0-0xf

SSR

RTC sub second register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

Allowed values: 0x0-0xffff

ICSR

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INIT
rw 		INITF
r 		RSF
r/w0c 		INITS
r 		SHPF
r 		WUTWF
r 		ALR[B]WF
r 		ALR[A]WF
r
Toggle fields

ALR[A]WF

Bit 0: Alarm A write flag.

ALR[B]WF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: WUTWF.

Allowed values:
0: UpdateNotAllowed: Wakeup timer configuration update not allowed
1: UpdateAllowed: Wakeup timer configuration update allowed

SHPF

Bit 3: SHPF.

Allowed values:
0: NoShiftPending: No shift operation is pending
1: ShiftPending: A shift operation is pending

INITS

Bit 4: INITS.

Allowed values:
0: NotInitalized: Calendar has not been initialized
1: Initalized: Calendar has been initialized

RSF

Bit 5: RSF.

Allowed values:
0: NotSynced: Calendar shadow registers not yet synchronized
1: Synced: Calendar shadow registers synchronized

INITF

Bit 6: INITF.

Allowed values:
0: NotAllowed: Calendar registers update is not allowed
1: Allowed: Calendar registers update is allowed

INIT

Bit 7: INIT.

Allowed values:
0: FreeRunningMode: Free running mode
1: InitMode: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

RECALPF

Bit 16: RECALPF.

Allowed values:
1: Pending: The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0

PRER

This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page1830. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x10, size: 32, reset: 0x007F00FF, access: read-write

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PREDIV_A
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV_S
rw
Toggle fields

PREDIV_S

Bits 0-14: PREDIV_S.

Allowed values: 0x0-0x7fff

PREDIV_A

Bits 16-22: PREDIV_A.

Allowed values: 0x0-0x7f

WUTR

This register can be written only when WUTWF is set to 1 in RTC_ICSR. This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x14, size: 32, reset: 0x0000FFFF, access: read-write

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT
rw
Toggle fields

WUT

Bits 0-15: WUT.

Allowed values: 0x0-0xffff

CR

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be globally protected, or each bit of this register can be individually protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x18, size: 32, reset: 0x00000000, access: Unspecified

26/26 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUT2EN
rw 		TAMPALRM_TYPE
rw 		TAMPALRM_PU
rw 		TAMPOE
rw 		TAMPTS
rw 		ITSE
rw 		COE
rw 		OSEL
rw 		POL
rw 		COSEL
rw 		BKP
rw 		SUB1H
w 		ADD1H
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIE
rw 		WUTIE
rw 		ALR[B]IE
rw 		ALR[A]IE
rw 		TSE
rw 		WUTE
rw 		ALR[B]E
rw 		ALR[A]E
rw 		FMT
rw 		BYPSHAD
rw 		REFCKON
rw 		TSEDGE
rw 		WUCKSEL
rw
Toggle fields

WUCKSEL

Bits 0-2: WUCKSEL.

Allowed values:
0: Div16: RTC/16 clock is selected
1: Div8: RTC/8 clock is selected
2: Div4: RTC/4 clock is selected
3: Div2: RTC/2 clock is selected
4: ClockSpare: ck_spre (usually 1 Hz) clock is selected
6: ClockSpareWithOffset: ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value

TSEDGE

Bit 3: TSEDGE.

Allowed values:
0: RisingEdge: RTC_TS input rising edge generates a time-stamp event
1: FallingEdge: RTC_TS input falling edge generates a time-stamp event

REFCKON

Bit 4: REFCKON.

Allowed values:
0: Disabled: RTC_REFIN detection disabled
1: Enabled: RTC_REFIN detection enabled

BYPSHAD

Bit 5: BYPSHAD.

Allowed values:
0: ShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles
1: BypassShadowReg: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters

FMT

Bit 6: FMT.

Allowed values:
0: TwentyFourHour: 24 hour/day format
1: AmPm: AM/PM hour format

ALR[A]E

Bit 8: Alarm A enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

ALR[B]E

Bit 9: Alarm B enable.

Allowed values:
0: Disabled: Alarm disabled
1: Enabled: Alarm enabled

WUTE

Bit 10: WUTE.

Allowed values:
0: Disabled: Wakeup timer disabled
1: Enabled: Wakeup timer enabled

TSE

Bit 11: TSE.

Allowed values:
0: Disabled: Timestamp disabled
1: Enabled: Timestamp enabled

ALR[A]IE

Bit 12: Alarm A interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

ALR[B]IE

Bit 13: Alarm B interrupt enable.

Allowed values:
0: Disabled: Alarm Interrupt disabled
1: Enabled: Alarm Interrupt enabled

WUTIE

Bit 14: WUTIE.

Allowed values:
0: Disabled: Wakeup timer interrupt disabled
1: Enabled: Wakeup timer interrupt enabled

TSIE

Bit 15: TSIE.

Allowed values:
0: Disabled: Time-stamp Interrupt disabled
1: Enabled: Time-stamp Interrupt enabled

ADD1H

Bit 16: ADD1H.

Allowed values:
1: Add1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode

SUB1H

Bit 17: SUB1H.

Allowed values:
1: Sub1: Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode

BKP

Bit 18: BKP.

Allowed values:
0: DSTNotChanged: Daylight Saving Time change has not been performed
1: DSTChanged: Daylight Saving Time change has been performed

COSEL

Bit 19: COSEL.

Allowed values:
0: CalFreq_512Hz: Calibration output is 512 Hz (with default prescaler setting)
1: CalFreq_1Hz: Calibration output is 1 Hz (with default prescaler setting)

POL

Bit 20: POL.

Allowed values:
0: High: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: Low: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

OSEL

Bits 21-22: OSEL.

Allowed values:
0: Disabled: Output disabled
1: AlarmA: Alarm A output enabled
2: AlarmB: Alarm B output enabled
3: Wakeup: Wakeup output enabled

COE

Bit 23: COE.

Allowed values:
0: Disabled: Calibration output disabled
1: Enabled: Calibration output enabled

ITSE

Bit 24: ITSE.

Allowed values:
0: Disabled: Internal event timestamp disabled
1: Enabled: Internal event timestamp enabled

TAMPTS

Bit 25: TAMPTS.

Allowed values:
0: Disabled: Tamper detection event does not cause a RTC timestamp to be saved
1: Enabled: Save RTC timestamp on tamper detection event

TAMPOE

Bit 26: TAMPOE.

Allowed values:
0: Disabled: The tamper flag is not routed on TAMPALRM
1: Enabled: The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL

TAMPALRM_PU

Bit 29: TAMPALRM_PU.

Allowed values:
0: NoPullUp: No pull-up is applied on TAMPALRM output
1: PullUp: A pull-up is applied on TAMPALRM output

TAMPALRM_TYPE

Bit 30: TAMPALRM_TYPE.

Allowed values:
0: PushPull: TAMPALRM is push-pull output
1: OpenDrain: TAMPALRM is open-drain output

OUT2EN

Bit 31: OUT2EN.

Allowed values:
0: Disabled: RTC output 2 disable
1: Enabled: RTC output 2 enable

SMCR

This register can be written only when the APB access is secure.

Offset: 0x20, size: 32, reset: 0x0000E00F, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DECPROT
rw 		INITDPROT
rw 		CALDPROT
rw 		TSDPROT
rw 		WUTDPROT
rw 		ALRBDPROT
rw 		ALRADPROT
rw
Toggle fields

ALRADPROT

Bit 0: ALRADPROT.

ALRBDPROT

Bit 1: ALRBDPROT.

WUTDPROT

Bit 2: WUTDPROT.

TSDPROT

Bit 3: TSDPROT.

CALDPROT

Bit 13: CALDPROT.

INITDPROT

Bit 14: INITDPROT.

DECPROT

Bit 15: DECPROT.

WPR

RTC write protection register

Offset: 0x24, size: 32, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
w
Toggle fields

KEY

Bits 0-7: KEY.

Allowed values:
0: Activate: Activate write protection (any value that is not the keys)
83: Deactivate2: Key 2
202: Deactivate1: Key 1

CALR

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be write-protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

4/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALP
rw 		CALW8
rw 		CALW16
rw 		CALM
rw
Toggle fields

CALM

Bits 0-8: CALM.

Allowed values: 0x0-0x1ff

CALW16

Bit 13: CALW16.

Allowed values:
1: SixteenSeconds: When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1

CALW8

Bit 14: CALW8.

Allowed values:
1: EightSeconds: When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected

CALP

Bit 15: CALP.

Allowed values:
0: NoChange: No RTCCLK pulses are added
1: IncreaseFreq: One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)

SHIFTR

This register is write protected. The write access procedure is described in RTC register write protection on page1830. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x2c, size: 32, reset: 0x00000000, access: write-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUBFS
w
Toggle fields

SUBFS

Bits 0-14: SUBFS.

Allowed values: 0x0-0x7fff

ADD1S

Bit 31: ADD1S.

Allowed values:
1: Add1: Add one second to the clock/calendar

TSTR

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MNT
rw 		MNU
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: SU.

Allowed values: 0x0-0xf

ST

Bits 4-6: ST.

Allowed values: 0x0-0x7

MNU

Bits 8-11: MNU.

Allowed values: 0x0-0xf

MNT

Bits 12-14: MNT.

Allowed values: 0x0-0x7

HU

Bits 16-19: HU.

Allowed values: 0x0-0xf

HT

Bits 20-21: HT.

Allowed values: 0x0-0x3

PM

Bit 22: PM.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

TSDR

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x34, size: 32, reset: 0x00002101, access: read-write

7/7 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
YT
rw 		YU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU
rw 		MT
rw 		MU
rw 		DT
rw 		DU
rw
Toggle fields

DU

Bits 0-3: DU.

Allowed values: 0x0-0xf

DT

Bits 4-5: DT.

Allowed values: 0x0-0x3

MU

Bits 8-11: MU.

Allowed values: 0x0-0xf

MT

Bit 12: MT.

Allowed values: 0x0-0x1

WDU

Bits 13-15: WDU.

Allowed values: 0x1-0x7

YU

Bits 16-19: YU.

Allowed values: 0x0-0xf

YT

Bits 20-23: YT.

Allowed values: 0x0-0xf

TSSSR

The content of this register is valid only when TSF is set to 1 in RTC_SR. It is cleared when the TSF bit is reset. This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
r
Toggle fields

SS

Bits 0-15: SS.

Allowed values: 0x0-0xffff

ALRM[A]R

Alarm A register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: PM.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: WDSEL.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[A]SSR

Alarm A sub-second register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: SS.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: MASKSS.

ALRM[B]R

Alarm B register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

14/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4
rw 		WDSEL
rw 		DT
rw 		DU
rw 		MSK3
rw 		PM
rw 		HT
rw 		HU
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2
rw 		MNT
rw 		MNU
rw 		MSK1
rw 		ST
rw 		SU
rw
Toggle fields

SU

Bits 0-3: Second units in BCD format.

Allowed values: 0x0-0xf

ST

Bits 4-6: Second tens in BCD format.

Allowed values: 0x0-0x7

MSK1

Bit 7: Alarm seconds mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

MNU

Bits 8-11: Minute units in BCD format.

Allowed values: 0x0-0xf

MNT

Bits 12-14: Minute tens in BCD format.

Allowed values: 0x0-0x7

MSK2

Bit 15: Alarm minutes mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

HU

Bits 16-19: Hour units in BCD format.

Allowed values: 0x0-0xf

HT

Bits 20-21: Hour tens in BCD format.

Allowed values: 0x0-0x3

PM

Bit 22: PM.

Allowed values:
0: AM: AM or 24-hour format
1: PM: PM

MSK3

Bit 23: Alarm hours mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

DU

Bits 24-27: Date units or day in BCD format.

Allowed values: 0x0-0xf

DT

Bits 28-29: Date tens in BCD format.

Allowed values: 0x0-0x3

WDSEL

Bit 30: WDSEL.

Allowed values:
0: DateUnits: DU[3:0] represents the date units
1: WeekDay: DU[3:0] represents the week day. DT[1:0] is don’t care.

MSK4

Bit 31: Alarm date mask.

Allowed values:
0: Mask: Alarm set if the date/day match
1: NotMask: Date/day don’t care in Alarm comparison

ALRM[B]SSR

Alarm B sub-second register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASKSS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS
rw
Toggle fields

SS

Bits 0-14: SS.

Allowed values: 0x0-0x7fff

MASKSS

Bits 24-27: MASKSS.

SR

This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSF
r 		TSOVF
r 		TSF
r 		WUTF
r 		ALR[B]F
r 		ALR[A]F
r
Toggle fields

ALR[A]F

Bit 0: Alarm A flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

ALR[B]F

Bit 1: Alarm B flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR)

WUTF

Bit 2: WUTF.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSF

Bit 3: TSF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVF

Bit 4: TSOVF.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSF

Bit 5: ITSF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

MISR

RTC non-secure masked interrupt status register

Offset: 0x54, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALR[B]MF
r 		ALR[A]MF
r
Toggle fields

ALR[A]MF

Bit 0: Alarm A masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

ALR[B]MF

Bit 1: Alarm B masked flag.

Allowed values:
1: Match: This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR)

WUTMF

Bit 2: WUTMF.

Allowed values:
1: Zero: This flag is set by hardware when the wakeup auto-reload counter reaches 0

TSMF

Bit 3: TSMF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a time-stamp event occurs

TSOVMF

Bit 4: TSOVMF.

Allowed values:
1: Overflow: This flag is set by hardware when a time-stamp event occurs while TSF is already set

ITSMF

Bit 5: ITSMF.

Allowed values:
1: TimestampEvent: This flag is set by hardware when a timestamp on the internal event occurs

SMISR

This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITSMF
r 		TSOVMF
r 		TSMF
r 		WUTMF
r 		ALRBMF
r 		ALRAMF
r
Toggle fields

ALRAMF

Bit 0: ALRAMF.

ALRBMF

Bit 1: ALRBMF.

WUTMF

Bit 2: WUTMF.

TSMF

Bit 3: TSMF.

TSOVMF

Bit 4: TSOVMF.

ITSMF

Bit 5: ITSMF.

SCR

This register can be protected against non-secure access. Refer to Section50.3.4: RTC secure protection modes.

Offset: 0x5c, size: 32, reset: 0x00000000, access: write-only

6/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CITSF
w 		CTSOVF
w 		CTSF
w 		CWUTF
w 		CALRBF
w 		CALRAF
w
Toggle fields

CALRAF

Bit 0: CALRAF.

Allowed values:
1: Clear: Clear interrupt flag

CALRBF

Bit 1: CALRBF.

Allowed values:
1: Clear: Clear interrupt flag

CWUTF

Bit 2: CWUTF.

Allowed values:
1: Clear: Clear interrupt flag

CTSF

Bit 3: CTSF.

Allowed values:
1: Clear: Clear interrupt flag

CTSOVF

Bit 4: CTSOVF.

Allowed values:
1: Clear: Clear interrupt flag

CITSF

Bit 5: CITSF.

Allowed values:
1: Clear: Clear interrupt flag

CFGR

RTC configuration register

Offset: 0x60, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSCOEN
rw 		OUT2_RMP
rw
Toggle fields

OUT2_RMP

Bit 0: OUT2_RMP.

LSCOEN

Bits 1-2: LSCOEN.

HWCFGR

RTC hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x01031111, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TRUST_ZONE
r 		OPTIONREG_OUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMESTAMP
r 		SMOOTH_CALIB
r 		WAKEUP
r 		ALARMB
r
Toggle fields

ALARMB

Bits 0-3: ALARMB.

WAKEUP

Bits 4-7: WAKEUP.

SMOOTH_CALIB

Bits 8-11: SMOOTH_CALIB.

TIMESTAMP

Bits 12-15: TIMESTAMP.

OPTIONREG_OUT

Bits 16-23: OPTIONREG_OUT.

TRUST_ZONE

Bits 24-27: TRUST_ZONE.

VERR

RTC version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

RTC identification register

Offset: 0x3f8, size: 32, reset: 0x00120033, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

RTC size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SAI1

0x4400a000: SAI1 register block

25/129 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 ACR1
0x8 ACR2
0xc AFRCR
0x10 ASLOTR
0x14 AIM
0x18 ASR
0x1c ACLRFR
0x20 ADR
0x24 BCR1
0x28 BCR2
0x2c BFRCR
0x30 BSLOTR
0x34 BIM
0x38 BSR
0x3c BCLRFR
0x40 BDR
0x44 PDMCR
0x48 PDMDLY
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: SYNCIN.

SYNCOUT

Bits 4-5: SYNCOUT.

ACR1

Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

ACR2

Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

AFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

ASLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

AIM

Interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

ASR

Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

ACLRFR

Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

ADR

Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

BCR1

Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

BCR2

Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

BFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

BSLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

BIM

Interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

BSR

Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

BCLRFR

Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

BDR

Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN4
rw 		CKEN3
rw 		CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDMEN.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: CKEN1.

CKEN2

Bit 9: CKEN2.

CKEN3

Bit 10: CKEN3.

CKEN4

Bit 11: CKEN4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM4R
rw 		DLYM4L
rw 		DLYM3R
rw 		DLYM3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM2R
rw 		DLYM2L
rw 		DLYM1R
rw 		DLYM1L
rw
Toggle fields

DLYM1L

Bits 0-2: DLYM1L.

DLYM1R

Bits 4-6: DLYM1R.

DLYM2L

Bits 8-10: DLYM2L.

DLYM2R

Bits 12-14: DLYM2R.

DLYM3L

Bits 16-18: DLYM3L.

DLYM3R

Bits 20-22: DLYM3R.

DLYM4L

Bits 24-26: DLYM4L.

DLYM4R

Bits 28-30: DLYM4R.

HWCFGR

SAI hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000108, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTION_REGOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTION_REGOUT
r 		SPDIF_PDM
r 		FIFO_SIZE
r
Toggle fields

FIFO_SIZE

Bits 0-7: FIFO_SIZE.

SPDIF_PDM

Bits 8-11: SPDIF_PDM.

OPTION_REGOUT

Bits 12-19: OPTION_REGOUT.

VERR

SAI version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SAI identification register

Offset: 0x3f8, size: 32, reset: 0x00130031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SAI size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SAI2

0x4400b000: SAI1 register block

25/129 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 ACR1
0x8 ACR2
0xc AFRCR
0x10 ASLOTR
0x14 AIM
0x18 ASR
0x1c ACLRFR
0x20 ADR
0x24 BCR1
0x28 BCR2
0x2c BFRCR
0x30 BSLOTR
0x34 BIM
0x38 BSR
0x3c BCLRFR
0x40 BDR
0x44 PDMCR
0x48 PDMDLY
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: SYNCIN.

SYNCOUT

Bits 4-5: SYNCOUT.

ACR1

Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

ACR2

Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

AFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

ASLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

AIM

Interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

ASR

Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

ACLRFR

Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

ADR

Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

BCR1

Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

BCR2

Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

BFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

BSLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

BIM

Interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

BSR

Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

BCLRFR

Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

BDR

Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN4
rw 		CKEN3
rw 		CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDMEN.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: CKEN1.

CKEN2

Bit 9: CKEN2.

CKEN3

Bit 10: CKEN3.

CKEN4

Bit 11: CKEN4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM4R
rw 		DLYM4L
rw 		DLYM3R
rw 		DLYM3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM2R
rw 		DLYM2L
rw 		DLYM1R
rw 		DLYM1L
rw
Toggle fields

DLYM1L

Bits 0-2: DLYM1L.

DLYM1R

Bits 4-6: DLYM1R.

DLYM2L

Bits 8-10: DLYM2L.

DLYM2R

Bits 12-14: DLYM2R.

DLYM3L

Bits 16-18: DLYM3L.

DLYM3R

Bits 20-22: DLYM3R.

DLYM4L

Bits 24-26: DLYM4L.

DLYM4R

Bits 28-30: DLYM4R.

HWCFGR

SAI hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000108, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTION_REGOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTION_REGOUT
r 		SPDIF_PDM
r 		FIFO_SIZE
r
Toggle fields

FIFO_SIZE

Bits 0-7: FIFO_SIZE.

SPDIF_PDM

Bits 8-11: SPDIF_PDM.

OPTION_REGOUT

Bits 12-19: OPTION_REGOUT.

VERR

SAI version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SAI identification register

Offset: 0x3f8, size: 32, reset: 0x00130031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SAI size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SAI3

0x4400c000: SAI1 register block

25/129 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 ACR1
0x8 ACR2
0xc AFRCR
0x10 ASLOTR
0x14 AIM
0x18 ASR
0x1c ACLRFR
0x20 ADR
0x24 BCR1
0x28 BCR2
0x2c BFRCR
0x30 BSLOTR
0x34 BIM
0x38 BSR
0x3c BCLRFR
0x40 BDR
0x44 PDMCR
0x48 PDMDLY
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: SYNCIN.

SYNCOUT

Bits 4-5: SYNCOUT.

ACR1

Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

ACR2

Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

AFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

ASLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

AIM

Interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

ASR

Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

ACLRFR

Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

ADR

Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

BCR1

Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

BCR2

Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

BFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

BSLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

BIM

Interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

BSR

Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

BCLRFR

Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

BDR

Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN4
rw 		CKEN3
rw 		CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDMEN.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: CKEN1.

CKEN2

Bit 9: CKEN2.

CKEN3

Bit 10: CKEN3.

CKEN4

Bit 11: CKEN4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM4R
rw 		DLYM4L
rw 		DLYM3R
rw 		DLYM3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM2R
rw 		DLYM2L
rw 		DLYM1R
rw 		DLYM1L
rw
Toggle fields

DLYM1L

Bits 0-2: DLYM1L.

DLYM1R

Bits 4-6: DLYM1R.

DLYM2L

Bits 8-10: DLYM2L.

DLYM2R

Bits 12-14: DLYM2R.

DLYM3L

Bits 16-18: DLYM3L.

DLYM3R

Bits 20-22: DLYM3R.

DLYM4L

Bits 24-26: DLYM4L.

DLYM4R

Bits 28-30: DLYM4R.

HWCFGR

SAI hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000108, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTION_REGOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTION_REGOUT
r 		SPDIF_PDM
r 		FIFO_SIZE
r
Toggle fields

FIFO_SIZE

Bits 0-7: FIFO_SIZE.

SPDIF_PDM

Bits 8-11: SPDIF_PDM.

OPTION_REGOUT

Bits 12-19: OPTION_REGOUT.

VERR

SAI version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SAI identification register

Offset: 0x3f8, size: 32, reset: 0x00130031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SAI size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SAI4

0x50027000: SAI1 register block

25/129 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 GCR
0x4 ACR1
0x8 ACR2
0xc AFRCR
0x10 ASLOTR
0x14 AIM
0x18 ASR
0x1c ACLRFR
0x20 ADR
0x24 BCR1
0x28 BCR2
0x2c BFRCR
0x30 BSLOTR
0x34 BIM
0x38 BSR
0x3c BCLRFR
0x40 BDR
0x44 PDMCR
0x48 PDMDLY
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

GCR

Global configuration register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCOUT
rw 		SYNCIN
rw
Toggle fields

SYNCIN

Bits 0-1: SYNCIN.

SYNCOUT

Bits 4-5: SYNCOUT.

ACR1

Configuration register 1

Offset: 0x4, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

ACR2

Configuration register 2

Offset: 0x8, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

AFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0xc, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

ASLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

AIM

Interrupt mask register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

ASR

Status register

Offset: 0x18, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

ACLRFR

Clear flag register

Offset: 0x1c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

ADR

Data register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

BCR1

Configuration register 1

Offset: 0x24, size: 32, reset: 0x00000040, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKEN
rw 		OSR
rw 		MCKDIV
rw 		NODIV
rw 		DMAEN
rw 		SAIEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTDRIV
rw 		MONO
rw 		SYNCEN
rw 		CKSTR
rw 		LSBFIRST
rw 		DS
rw 		PRTCFG
rw 		MODE
rw
Toggle fields

MODE

Bits 0-1: MODE.

PRTCFG

Bits 2-3: PRTCFG.

DS

Bits 5-7: DS.

LSBFIRST

Bit 8: LSBFIRST.

CKSTR

Bit 9: CKSTR.

SYNCEN

Bits 10-11: SYNCEN.

MONO

Bit 12: MONO.

OUTDRIV

Bit 13: OUTDRIV.

SAIEN

Bit 16: SAIEN.

DMAEN

Bit 17: DMAEN.

NODIV

Bit 19: NODIV.

MCKDIV

Bits 20-25: MCKDIV.

OSR

Bit 26: OSR.

MCKEN

Bit 27: MCKEN.

BCR2

Configuration register 2

Offset: 0x28, size: 32, reset: 0x00000000, access: Unspecified

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP
rw 		CPL
rw 		MUTECNT
rw 		MUTEVAL
rw 		MUTE
rw 		TRIS
rw 		FFLUSH
w 		FTH
rw
Toggle fields

FTH

Bits 0-2: FTH.

FFLUSH

Bit 3: FFLUSH.

TRIS

Bit 4: TRIS.

MUTE

Bit 5: MUTE.

MUTEVAL

Bit 6: MUTEVAL.

MUTECNT

Bits 7-12: MUTECNT.

CPL

Bit 13: CPL.

COMP

Bits 14-15: COMP.

BFRCR

This register has no meaning in and SPDIF audio protocol

Offset: 0x2c, size: 32, reset: 0x00000007, access: Unspecified

1/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FSOFF
rw 		FSPOL
rw 		FSDEF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FSALL
rw 		FRL
rw
Toggle fields

FRL

Bits 0-7: FRL.

FSALL

Bits 8-14: FSALL.

FSDEF

Bit 16: FSDEF.

FSPOL

Bit 17: FSPOL.

FSOFF

Bit 18: FSOFF.

BSLOTR

This register has no meaning in and SPDIF audio protocol

Offset: 0x30, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SLOTEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NBSLOT
rw 		SLOTSZ
rw 		FBOFF
rw
Toggle fields

FBOFF

Bits 0-4: FBOFF.

SLOTSZ

Bits 6-7: SLOTSZ.

NBSLOT

Bits 8-11: NBSLOT.

SLOTEN

Bits 16-31: SLOTEN.

BIM

Interrupt mask register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDETIE
rw 		AFSDETIE
rw 		CNRDYIE
rw 		FREQIE
rw 		WCKCFGIE
rw 		MUTEDETIE
rw 		OVRUDRIE
rw
Toggle fields

OVRUDRIE

Bit 0: OVRUDRIE.

MUTEDETIE

Bit 1: MUTEDETIE.

WCKCFGIE

Bit 2: WCKCFGIE.

FREQIE

Bit 3: FREQIE.

CNRDYIE

Bit 4: CNRDYIE.

AFSDETIE

Bit 5: AFSDETIE.

LFSDETIE

Bit 6: LFSDETIE.

BSR

Status register

Offset: 0x38, size: 32, reset: 0x00000008, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLVL
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSDET
r 		AFSDET
r 		CNRDY
r 		FREQ
r 		WCKCFG
r 		MUTEDET
r 		OVRUDR
r
Toggle fields

OVRUDR

Bit 0: OVRUDR.

MUTEDET

Bit 1: MUTEDET.

WCKCFG

Bit 2: WCKCFG.

FREQ

Bit 3: FREQ.

CNRDY

Bit 4: CNRDY.

AFSDET

Bit 5: AFSDET.

LFSDET

Bit 6: LFSDET.

FLVL

Bits 16-18: FLVL.

BCLRFR

Clear flag register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLFSDET
w 		CAFSDET
w 		CCNRDY
w 		CWCKCFG
w 		CMUTEDET
w 		COVRUDR
w
Toggle fields

COVRUDR

Bit 0: COVRUDR.

CMUTEDET

Bit 1: CMUTEDET.

CWCKCFG

Bit 2: CWCKCFG.

CCNRDY

Bit 4: CCNRDY.

CAFSDET

Bit 5: CAFSDET.

CLFSDET

Bit 6: CLFSDET.

BDR

Data register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
rw
Toggle fields

DATA

Bits 0-31: DATA.

PDMCR

PDM control register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKEN4
rw 		CKEN3
rw 		CKEN2
rw 		CKEN1
rw 		MICNBR
rw 		PDMEN
rw
Toggle fields

PDMEN

Bit 0: PDMEN.

MICNBR

Bits 4-5: MICNBR.

CKEN1

Bit 8: CKEN1.

CKEN2

Bit 9: CKEN2.

CKEN3

Bit 10: CKEN3.

CKEN4

Bit 11: CKEN4.

PDMDLY

PDM delay register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLYM4R
rw 		DLYM4L
rw 		DLYM3R
rw 		DLYM3L
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLYM2R
rw 		DLYM2L
rw 		DLYM1R
rw 		DLYM1L
rw
Toggle fields

DLYM1L

Bits 0-2: DLYM1L.

DLYM1R

Bits 4-6: DLYM1R.

DLYM2L

Bits 8-10: DLYM2L.

DLYM2R

Bits 12-14: DLYM2R.

DLYM3L

Bits 16-18: DLYM3L.

DLYM3R

Bits 20-22: DLYM3R.

DLYM4L

Bits 24-26: DLYM4L.

DLYM4R

Bits 28-30: DLYM4R.

HWCFGR

SAI hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000108, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTION_REGOUT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTION_REGOUT
r 		SPDIF_PDM
r 		FIFO_SIZE
r
Toggle fields

FIFO_SIZE

Bits 0-7: FIFO_SIZE.

SPDIF_PDM

Bits 8-11: SPDIF_PDM.

OPTION_REGOUT

Bits 12-19: OPTION_REGOUT.

VERR

SAI version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SAI identification register

Offset: 0x3f8, size: 32, reset: 0x00130031, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SAI size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SDMMC1

0x58005000: SDMMC1

39/144 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASER
0x64 IDMALAR
0x68 IDMABAR
0x80 FIFOR0
0x84 FIFOR1
0x88 FIFOR2
0x8c FIFOR3
0x90 FIFOR4
0x94 FIFOR5
0x98 FIFOR6
0x9c FIFOR7
0xa0 FIFOR8
0xa4 FIFOR9
0xa8 FIFOR10
0xac FIFOR11
0xb0 FIFOR12
0xb4 FIFOR13
0xb8 FIFOR14
0xbc FIFOR15
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw 		VSWITCHEN
rw 		VSWITCH
rw 		PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: PWRCTRL.

VSWITCH

Bit 2: VSWITCH.

VSWITCHEN

Bit 3: VSWITCHEN.

DIRPOL

Bit 4: DIRPOL.

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw 		BUSSPEED
rw 		DDR
rw 		HWFC_EN
rw 		NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw 		PWRSAV
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: CLKDIV.

PWRSAV

Bit 12: PWRSAV.

WIDBUS

Bits 14-15: WIDBUS.

NEGEDGE

Bit 16: NEGEDGE.

HWFC_EN

Bit 17: HWFC_EN.

DDR

Bit 18: DDR.

BUSSPEED

Bit 19: BUSSPEED.

SELCLKRX

Bits 20-21: SELCLKRX.

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: CMDARG.

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw 		BOOTMODE
rw 		DTHOLD
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDSTOP
rw 		CMDTRANS
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: CMDINDEX.

CMDTRANS

Bit 6: CMDTRANS.

CMDSTOP

Bit 7: CMDSTOP.

WAITRESP

Bits 8-9: WAITRESP.

WAITINT

Bit 10: WAITINT.

WAITPEND

Bit 11: WAITPEND.

CPSMEN

Bit 12: CPSMEN.

DTHOLD

Bit 13: DTHOLD.

BOOTMODE

Bit 14: BOOTMODE.

BOOTEN

Bit 15: BOOTEN.

CMDSUSPEND

Bit 16: CMDSUSPEND.

RESPCMDR

The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: RESPCMD.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: CARDSTATUS1.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: CARDSTATUS2.

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: CARDSTATUS3.

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: CARDSTATUS4.

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: DATATIME.

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: DATALENGTH.

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw 		BOOTACKEN
rw 		SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: DTDIR.

DTMODE

Bits 2-3: DTMODE.

DBLOCKSIZE

Bits 4-7: DBLOCKSIZE.

RWSTART

Bit 8: RWSTART.

RWSTOP

Bit 9: RWSTOP.

RWMOD

Bit 10: RWMOD.

SDIOEN

Bit 11: SDIOEN.

BOOTACKEN

Bit 12: BOOTACKEN.

FIFORST

Bit 13: FIFORST.

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: DATACOUNT.

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTC
r 		IDMATE
r 		CKSTOP
r 		VSWEND
r 		ACKTIMEOUT
r 		ACKFAIL
r 		SDIOIT
r 		BUSYD0END
r 		BUSYD0
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		CPSMACT
r 		DPSMACT
r 		DABORT
r 		DBCKEND
r 		DHOLD
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: CCRCFAIL.

DCRCFAIL

Bit 1: DCRCFAIL.

CTIMEOUT

Bit 2: CTIMEOUT.

DTIMEOUT

Bit 3: DTIMEOUT.

TXUNDERR

Bit 4: TXUNDERR.

RXOVERR

Bit 5: RXOVERR.

CMDREND

Bit 6: CMDREND.

CMDSENT

Bit 7: CMDSENT.

DATAEND

Bit 8: DATAEND.

DHOLD

Bit 9: DHOLD.

DBCKEND

Bit 10: DBCKEND.

DABORT

Bit 11: DABORT.

DPSMACT

Bit 12: DPSMACT.

CPSMACT

Bit 13: CPSMACT.

TXFIFOHE

Bit 14: TXFIFOHE.

RXFIFOHF

Bit 15: RXFIFOHF.

TXFIFOF

Bit 16: TXFIFOF.

RXFIFOF

Bit 17: RXFIFOF.

TXFIFOE

Bit 18: TXFIFOE.

RXFIFOE

Bit 19: RXFIFOE.

BUSYD0

Bit 20: BUSYD0.

BUSYD0END

Bit 21: BUSYD0END.

SDIOIT

Bit 22: SDIOIT.

ACKFAIL

Bit 23: ACKFAIL.

ACKTIMEOUT

Bit 24: ACKTIMEOUT.

VSWEND

Bit 25: VSWEND.

CKSTOP

Bit 26: CKSTOP.

IDMATE

Bit 27: IDMATE.

IDMABTC

Bit 28: IDMABTC.

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCC
rw 		IDMATEC
rw 		CKSTOPC
rw 		VSWENDC
rw 		ACKTIMEOUTC
rw 		ACKFAILC
rw 		SDIOITC
rw 		BUSYD0ENDC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DABORTC
rw 		DBCKENDC
rw 		DHOLDC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAILC.

DCRCFAILC

Bit 1: DCRCFAILC.

CTIMEOUTC

Bit 2: CTIMEOUTC.

DTIMEOUTC

Bit 3: DTIMEOUTC.

TXUNDERRC

Bit 4: TXUNDERRC.

RXOVERRC

Bit 5: RXOVERRC.

CMDRENDC

Bit 6: CMDRENDC.

CMDSENTC

Bit 7: CMDSENTC.

DATAENDC

Bit 8: DATAENDC.

DHOLDC

Bit 9: DHOLDC.

DBCKENDC

Bit 10: DBCKENDC.

DABORTC

Bit 11: DABORTC.

BUSYD0ENDC

Bit 21: BUSYD0ENDC.

SDIOITC

Bit 22: SDIOITC.

ACKFAILC

Bit 23: ACKFAILC.

ACKTIMEOUTC

Bit 24: ACKTIMEOUTC.

VSWENDC

Bit 25: VSWENDC.

CKSTOPC

Bit 26: CKSTOPC.

IDMATEC

Bit 27: IDMATEC.

IDMABTCC

Bit 28: IDMABTCC.

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCIE
rw 		CKSTOPIE
rw 		VSWENDIE
rw 		ACKTIMEOUTIE
rw 		ACKFAILIE
rw 		SDIOITIE
rw 		BUSYD0ENDIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		DABORTIE
rw 		DBCKENDIE
rw 		DHOLDIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: CCRCFAILIE.

DCRCFAILIE

Bit 1: DCRCFAILIE.

CTIMEOUTIE

Bit 2: CTIMEOUTIE.

DTIMEOUTIE

Bit 3: DTIMEOUTIE.

TXUNDERRIE

Bit 4: TXUNDERRIE.

RXOVERRIE

Bit 5: RXOVERRIE.

CMDRENDIE

Bit 6: CMDRENDIE.

CMDSENTIE

Bit 7: CMDSENTIE.

DATAENDIE

Bit 8: DATAENDIE.

DHOLDIE

Bit 9: DHOLDIE.

DBCKENDIE

Bit 10: DBCKENDIE.

DABORTIE

Bit 11: DABORTIE.

TXFIFOHEIE

Bit 14: TXFIFOHEIE.

RXFIFOHFIE

Bit 15: RXFIFOHFIE.

RXFIFOFIE

Bit 17: RXFIFOFIE.

TXFIFOEIE

Bit 18: TXFIFOEIE.

BUSYD0ENDIE

Bit 21: BUSYD0ENDIE.

SDIOITIE

Bit 22: SDIOITIE.

ACKFAILIE

Bit 23: ACKFAILIE.

ACKTIMEOUTIE

Bit 24: ACKTIMEOUTIE.

VSWENDIE

Bit 25: VSWENDIE.

CKSTOPIE

Bit 26: CKSTOPIE.

IDMABTCIE

Bit 28: IDMABTCIE.

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: ACKTIME.

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABMODE
rw 		IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMAEN.

IDMABMODE

Bit 1: IDMABMODE.

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-16: IDMABNDT.

IDMABASER

The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE
rw
Toggle fields

IDMABASE

Bits 0-31: IDMABASE.

IDMALAR

SDMMC IDMA linked list address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ULA
rw 		ULS
rw 		ABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMALA
rw
Toggle fields

IDMALA

Bits 2-15: IDMALA.

ABR

Bit 29: ABR.

ULS

Bit 30: ULS.

ULA

Bit 31: ULA.

IDMABAR

SDMMC IDMA linked list memory base register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABA
rw
Toggle fields

IDMABA

Bits 2-31: IDMABA.

FIFOR0

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR1

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR2

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR3

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR4

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR5

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR6

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR7

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR8

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR9

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR10

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR11

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR12

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR13

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR14

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR15

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

VERR

SDMMC version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SDMMC identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: IP_ID.

SIDR

SDMMC size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SDMMC2

0x58007000: SDMMC1

39/144 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASER
0x64 IDMALAR
0x68 IDMABAR
0x80 FIFOR0
0x84 FIFOR1
0x88 FIFOR2
0x8c FIFOR3
0x90 FIFOR4
0x94 FIFOR5
0x98 FIFOR6
0x9c FIFOR7
0xa0 FIFOR8
0xa4 FIFOR9
0xa8 FIFOR10
0xac FIFOR11
0xb0 FIFOR12
0xb4 FIFOR13
0xb8 FIFOR14
0xbc FIFOR15
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw 		VSWITCHEN
rw 		VSWITCH
rw 		PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: PWRCTRL.

VSWITCH

Bit 2: VSWITCH.

VSWITCHEN

Bit 3: VSWITCHEN.

DIRPOL

Bit 4: DIRPOL.

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw 		BUSSPEED
rw 		DDR
rw 		HWFC_EN
rw 		NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw 		PWRSAV
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: CLKDIV.

PWRSAV

Bit 12: PWRSAV.

WIDBUS

Bits 14-15: WIDBUS.

NEGEDGE

Bit 16: NEGEDGE.

HWFC_EN

Bit 17: HWFC_EN.

DDR

Bit 18: DDR.

BUSSPEED

Bit 19: BUSSPEED.

SELCLKRX

Bits 20-21: SELCLKRX.

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: CMDARG.

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw 		BOOTMODE
rw 		DTHOLD
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDSTOP
rw 		CMDTRANS
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: CMDINDEX.

CMDTRANS

Bit 6: CMDTRANS.

CMDSTOP

Bit 7: CMDSTOP.

WAITRESP

Bits 8-9: WAITRESP.

WAITINT

Bit 10: WAITINT.

WAITPEND

Bit 11: WAITPEND.

CPSMEN

Bit 12: CPSMEN.

DTHOLD

Bit 13: DTHOLD.

BOOTMODE

Bit 14: BOOTMODE.

BOOTEN

Bit 15: BOOTEN.

CMDSUSPEND

Bit 16: CMDSUSPEND.

RESPCMDR

The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: RESPCMD.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: CARDSTATUS1.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: CARDSTATUS2.

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: CARDSTATUS3.

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: CARDSTATUS4.

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: DATATIME.

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: DATALENGTH.

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw 		BOOTACKEN
rw 		SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: DTDIR.

DTMODE

Bits 2-3: DTMODE.

DBLOCKSIZE

Bits 4-7: DBLOCKSIZE.

RWSTART

Bit 8: RWSTART.

RWSTOP

Bit 9: RWSTOP.

RWMOD

Bit 10: RWMOD.

SDIOEN

Bit 11: SDIOEN.

BOOTACKEN

Bit 12: BOOTACKEN.

FIFORST

Bit 13: FIFORST.

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: DATACOUNT.

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTC
r 		IDMATE
r 		CKSTOP
r 		VSWEND
r 		ACKTIMEOUT
r 		ACKFAIL
r 		SDIOIT
r 		BUSYD0END
r 		BUSYD0
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		CPSMACT
r 		DPSMACT
r 		DABORT
r 		DBCKEND
r 		DHOLD
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: CCRCFAIL.

DCRCFAIL

Bit 1: DCRCFAIL.

CTIMEOUT

Bit 2: CTIMEOUT.

DTIMEOUT

Bit 3: DTIMEOUT.

TXUNDERR

Bit 4: TXUNDERR.

RXOVERR

Bit 5: RXOVERR.

CMDREND

Bit 6: CMDREND.

CMDSENT

Bit 7: CMDSENT.

DATAEND

Bit 8: DATAEND.

DHOLD

Bit 9: DHOLD.

DBCKEND

Bit 10: DBCKEND.

DABORT

Bit 11: DABORT.

DPSMACT

Bit 12: DPSMACT.

CPSMACT

Bit 13: CPSMACT.

TXFIFOHE

Bit 14: TXFIFOHE.

RXFIFOHF

Bit 15: RXFIFOHF.

TXFIFOF

Bit 16: TXFIFOF.

RXFIFOF

Bit 17: RXFIFOF.

TXFIFOE

Bit 18: TXFIFOE.

RXFIFOE

Bit 19: RXFIFOE.

BUSYD0

Bit 20: BUSYD0.

BUSYD0END

Bit 21: BUSYD0END.

SDIOIT

Bit 22: SDIOIT.

ACKFAIL

Bit 23: ACKFAIL.

ACKTIMEOUT

Bit 24: ACKTIMEOUT.

VSWEND

Bit 25: VSWEND.

CKSTOP

Bit 26: CKSTOP.

IDMATE

Bit 27: IDMATE.

IDMABTC

Bit 28: IDMABTC.

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCC
rw 		IDMATEC
rw 		CKSTOPC
rw 		VSWENDC
rw 		ACKTIMEOUTC
rw 		ACKFAILC
rw 		SDIOITC
rw 		BUSYD0ENDC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DABORTC
rw 		DBCKENDC
rw 		DHOLDC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAILC.

DCRCFAILC

Bit 1: DCRCFAILC.

CTIMEOUTC

Bit 2: CTIMEOUTC.

DTIMEOUTC

Bit 3: DTIMEOUTC.

TXUNDERRC

Bit 4: TXUNDERRC.

RXOVERRC

Bit 5: RXOVERRC.

CMDRENDC

Bit 6: CMDRENDC.

CMDSENTC

Bit 7: CMDSENTC.

DATAENDC

Bit 8: DATAENDC.

DHOLDC

Bit 9: DHOLDC.

DBCKENDC

Bit 10: DBCKENDC.

DABORTC

Bit 11: DABORTC.

BUSYD0ENDC

Bit 21: BUSYD0ENDC.

SDIOITC

Bit 22: SDIOITC.

ACKFAILC

Bit 23: ACKFAILC.

ACKTIMEOUTC

Bit 24: ACKTIMEOUTC.

VSWENDC

Bit 25: VSWENDC.

CKSTOPC

Bit 26: CKSTOPC.

IDMATEC

Bit 27: IDMATEC.

IDMABTCC

Bit 28: IDMABTCC.

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCIE
rw 		CKSTOPIE
rw 		VSWENDIE
rw 		ACKTIMEOUTIE
rw 		ACKFAILIE
rw 		SDIOITIE
rw 		BUSYD0ENDIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		DABORTIE
rw 		DBCKENDIE
rw 		DHOLDIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: CCRCFAILIE.

DCRCFAILIE

Bit 1: DCRCFAILIE.

CTIMEOUTIE

Bit 2: CTIMEOUTIE.

DTIMEOUTIE

Bit 3: DTIMEOUTIE.

TXUNDERRIE

Bit 4: TXUNDERRIE.

RXOVERRIE

Bit 5: RXOVERRIE.

CMDRENDIE

Bit 6: CMDRENDIE.

CMDSENTIE

Bit 7: CMDSENTIE.

DATAENDIE

Bit 8: DATAENDIE.

DHOLDIE

Bit 9: DHOLDIE.

DBCKENDIE

Bit 10: DBCKENDIE.

DABORTIE

Bit 11: DABORTIE.

TXFIFOHEIE

Bit 14: TXFIFOHEIE.

RXFIFOHFIE

Bit 15: RXFIFOHFIE.

RXFIFOFIE

Bit 17: RXFIFOFIE.

TXFIFOEIE

Bit 18: TXFIFOEIE.

BUSYD0ENDIE

Bit 21: BUSYD0ENDIE.

SDIOITIE

Bit 22: SDIOITIE.

ACKFAILIE

Bit 23: ACKFAILIE.

ACKTIMEOUTIE

Bit 24: ACKTIMEOUTIE.

VSWENDIE

Bit 25: VSWENDIE.

CKSTOPIE

Bit 26: CKSTOPIE.

IDMABTCIE

Bit 28: IDMABTCIE.

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: ACKTIME.

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABMODE
rw 		IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMAEN.

IDMABMODE

Bit 1: IDMABMODE.

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-16: IDMABNDT.

IDMABASER

The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE
rw
Toggle fields

IDMABASE

Bits 0-31: IDMABASE.

IDMALAR

SDMMC IDMA linked list address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ULA
rw 		ULS
rw 		ABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMALA
rw
Toggle fields

IDMALA

Bits 2-15: IDMALA.

ABR

Bit 29: ABR.

ULS

Bit 30: ULS.

ULA

Bit 31: ULA.

IDMABAR

SDMMC IDMA linked list memory base register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABA
rw
Toggle fields

IDMABA

Bits 2-31: IDMABA.

FIFOR0

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR1

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR2

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR3

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR4

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR5

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR6

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR7

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR8

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR9

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR10

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR11

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR12

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR13

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR14

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR15

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

VERR

SDMMC version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SDMMC identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: IP_ID.

SIDR

SDMMC size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SDMMC3

0x48004000: SDMMC1

39/144 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 POWER
0x4 CLKCR
0x8 ARGR
0xc CMDR
0x10 RESPCMDR
0x14 RESP1R
0x18 RESP2R
0x1c RESP3R
0x20 RESP4R
0x24 DTIMER
0x28 DLENR
0x2c DCTRL
0x30 DCNTR
0x34 STAR
0x38 ICR
0x3c MASKR
0x40 ACKTIMER
0x50 IDMACTRLR
0x54 IDMABSIZER
0x58 IDMABASER
0x64 IDMALAR
0x68 IDMABAR
0x80 FIFOR0
0x84 FIFOR1
0x88 FIFOR2
0x8c FIFOR3
0x90 FIFOR4
0x94 FIFOR5
0x98 FIFOR6
0x9c FIFOR7
0xa0 FIFOR8
0xa4 FIFOR9
0xa8 FIFOR10
0xac FIFOR11
0xb0 FIFOR12
0xb4 FIFOR13
0xb8 FIFOR14
0xbc FIFOR15
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

POWER

SDMMC power control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIRPOL
rw 		VSWITCHEN
rw 		VSWITCH
rw 		PWRCTRL
rw
Toggle fields

PWRCTRL

Bits 0-1: PWRCTRL.

VSWITCH

Bit 2: VSWITCH.

VSWITCHEN

Bit 3: VSWITCHEN.

DIRPOL

Bit 4: DIRPOL.

CLKCR

The SDMMC_CLKCR register controls the SDMMC_CK output clock, the sdmmc_rx_ck receive clock, and the bus width.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SELCLKRX
rw 		BUSSPEED
rw 		DDR
rw 		HWFC_EN
rw 		NEGEDGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDBUS
rw 		PWRSAV
rw 		CLKDIV
rw
Toggle fields

CLKDIV

Bits 0-9: CLKDIV.

PWRSAV

Bit 12: PWRSAV.

WIDBUS

Bits 14-15: WIDBUS.

NEGEDGE

Bit 16: NEGEDGE.

HWFC_EN

Bit 17: HWFC_EN.

DDR

Bit 18: DDR.

BUSSPEED

Bit 19: BUSSPEED.

SELCLKRX

Bits 20-21: SELCLKRX.

ARGR

The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARG
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARG
rw
Toggle fields

CMDARG

Bits 0-31: CMDARG.

CMDR

The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDSUSPEND
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOTEN
rw 		BOOTMODE
rw 		DTHOLD
rw 		CPSMEN
rw 		WAITPEND
rw 		WAITINT
rw 		WAITRESP
rw 		CMDSTOP
rw 		CMDTRANS
rw 		CMDINDEX
rw
Toggle fields

CMDINDEX

Bits 0-5: CMDINDEX.

CMDTRANS

Bit 6: CMDTRANS.

CMDSTOP

Bit 7: CMDSTOP.

WAITRESP

Bits 8-9: WAITRESP.

WAITINT

Bit 10: WAITINT.

WAITPEND

Bit 11: WAITPEND.

CPSMEN

Bit 12: CPSMEN.

DTHOLD

Bit 13: DTHOLD.

BOOTMODE

Bit 14: BOOTMODE.

BOOTEN

Bit 15: BOOTEN.

CMDSUSPEND

Bit 16: CMDSUSPEND.

RESPCMDR

The SDMMC_RESPCMDR register contains the command index field of the last command response received. If the command response transmission does not contain the command index field (long or OCR response), the RESPCMD field is unknown, although it must contain 111111b (the value of the reserved field from the response).

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESPCMD
r
Toggle fields

RESPCMD

Bits 0-5: RESPCMD.

RESP1R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS1
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS1
r
Toggle fields

CARDSTATUS1

Bits 0-31: CARDSTATUS1.

RESP2R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS2
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS2
r
Toggle fields

CARDSTATUS2

Bits 0-31: CARDSTATUS2.

RESP3R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS3
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS3
r
Toggle fields

CARDSTATUS3

Bits 0-31: CARDSTATUS3.

RESP4R

The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CARDSTATUS4
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CARDSTATUS4
r
Toggle fields

CARDSTATUS4

Bits 0-31: CARDSTATUS4.

DTIMER

The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATATIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATATIME
rw
Toggle fields

DATATIME

Bits 0-31: DATATIME.

DLENR

The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts.

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATALENGTH
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATALENGTH
rw
Toggle fields

DATALENGTH

Bits 0-24: DATALENGTH.

DCTRL

The SDMMC_DCTRL register control the data path state machine (DPSM).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFORST
rw 		BOOTACKEN
rw 		SDIOEN
rw 		RWMOD
rw 		RWSTOP
rw 		RWSTART
rw 		DBLOCKSIZE
rw 		DTMODE
rw 		DTDIR
rw 		DTEN
rw
Toggle fields

DTEN

Bit 0: DTEN.

DTDIR

Bit 1: DTDIR.

DTMODE

Bits 2-3: DTMODE.

DBLOCKSIZE

Bits 4-7: DBLOCKSIZE.

RWSTART

Bit 8: RWSTART.

RWSTOP

Bit 9: RWSTOP.

RWMOD

Bit 10: RWMOD.

SDIOEN

Bit 11: SDIOEN.

BOOTACKEN

Bit 12: BOOTACKEN.

FIFORST

Bit 13: FIFORST.

DCNTR

The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATACOUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATACOUNT
r
Toggle fields

DATACOUNT

Bits 0-24: DATACOUNT.

STAR

The SDMMC_STAR register is a read-only register. It contains two types of flag: Static flags (bits [28, 21, 11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR) Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

29/29 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTC
r 		IDMATE
r 		CKSTOP
r 		VSWEND
r 		ACKTIMEOUT
r 		ACKFAIL
r 		SDIOIT
r 		BUSYD0END
r 		BUSYD0
r 		RXFIFOE
r 		TXFIFOE
r 		RXFIFOF
r 		TXFIFOF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHF
r 		TXFIFOHE
r 		CPSMACT
r 		DPSMACT
r 		DABORT
r 		DBCKEND
r 		DHOLD
r 		DATAEND
r 		CMDSENT
r 		CMDREND
r 		RXOVERR
r 		TXUNDERR
r 		DTIMEOUT
r 		CTIMEOUT
r 		DCRCFAIL
r 		CCRCFAIL
r
Toggle fields

CCRCFAIL

Bit 0: CCRCFAIL.

DCRCFAIL

Bit 1: DCRCFAIL.

CTIMEOUT

Bit 2: CTIMEOUT.

DTIMEOUT

Bit 3: DTIMEOUT.

TXUNDERR

Bit 4: TXUNDERR.

RXOVERR

Bit 5: RXOVERR.

CMDREND

Bit 6: CMDREND.

CMDSENT

Bit 7: CMDSENT.

DATAEND

Bit 8: DATAEND.

DHOLD

Bit 9: DHOLD.

DBCKEND

Bit 10: DBCKEND.

DABORT

Bit 11: DABORT.

DPSMACT

Bit 12: DPSMACT.

CPSMACT

Bit 13: CPSMACT.

TXFIFOHE

Bit 14: TXFIFOHE.

RXFIFOHF

Bit 15: RXFIFOHF.

TXFIFOF

Bit 16: TXFIFOF.

RXFIFOF

Bit 17: RXFIFOF.

TXFIFOE

Bit 18: TXFIFOE.

RXFIFOE

Bit 19: RXFIFOE.

BUSYD0

Bit 20: BUSYD0.

BUSYD0END

Bit 21: BUSYD0END.

SDIOIT

Bit 22: SDIOIT.

ACKFAIL

Bit 23: ACKFAIL.

ACKTIMEOUT

Bit 24: ACKTIMEOUT.

VSWEND

Bit 25: VSWEND.

CKSTOP

Bit 26: CKSTOP.

IDMATE

Bit 27: IDMATE.

IDMABTC

Bit 28: IDMABTC.

ICR

The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register.

Offset: 0x38, size: 32, reset: 0x00000000, access: read-write

0/20 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCC
rw 		IDMATEC
rw 		CKSTOPC
rw 		VSWENDC
rw 		ACKTIMEOUTC
rw 		ACKFAILC
rw 		SDIOITC
rw 		BUSYD0ENDC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DABORTC
rw 		DBCKENDC
rw 		DHOLDC
rw 		DATAENDC
rw 		CMDSENTC
rw 		CMDRENDC
rw 		RXOVERRC
rw 		TXUNDERRC
rw 		DTIMEOUTC
rw 		CTIMEOUTC
rw 		DCRCFAILC
rw 		CCRCFAILC
rw
Toggle fields

CCRCFAILC

Bit 0: CCRCFAILC.

DCRCFAILC

Bit 1: DCRCFAILC.

CTIMEOUTC

Bit 2: CTIMEOUTC.

DTIMEOUTC

Bit 3: DTIMEOUTC.

TXUNDERRC

Bit 4: TXUNDERRC.

RXOVERRC

Bit 5: RXOVERRC.

CMDRENDC

Bit 6: CMDRENDC.

CMDSENTC

Bit 7: CMDSENTC.

DATAENDC

Bit 8: DATAENDC.

DHOLDC

Bit 9: DHOLDC.

DBCKENDC

Bit 10: DBCKENDC.

DABORTC

Bit 11: DABORTC.

BUSYD0ENDC

Bit 21: BUSYD0ENDC.

SDIOITC

Bit 22: SDIOITC.

ACKFAILC

Bit 23: ACKFAILC.

ACKTIMEOUTC

Bit 24: ACKTIMEOUTC.

VSWENDC

Bit 25: VSWENDC.

CKSTOPC

Bit 26: CKSTOPC.

IDMATEC

Bit 27: IDMATEC.

IDMABTCC

Bit 28: IDMABTCC.

MASKR

The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1.

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-write

0/23 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABTCIE
rw 		CKSTOPIE
rw 		VSWENDIE
rw 		ACKTIMEOUTIE
rw 		ACKFAILIE
rw 		SDIOITIE
rw 		BUSYD0ENDIE
rw 		TXFIFOEIE
rw 		RXFIFOFIE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFOHFIE
rw 		TXFIFOHEIE
rw 		DABORTIE
rw 		DBCKENDIE
rw 		DHOLDIE
rw 		DATAENDIE
rw 		CMDSENTIE
rw 		CMDRENDIE
rw 		RXOVERRIE
rw 		TXUNDERRIE
rw 		DTIMEOUTIE
rw 		CTIMEOUTIE
rw 		DCRCFAILIE
rw 		CCRCFAILIE
rw
Toggle fields

CCRCFAILIE

Bit 0: CCRCFAILIE.

DCRCFAILIE

Bit 1: DCRCFAILIE.

CTIMEOUTIE

Bit 2: CTIMEOUTIE.

DTIMEOUTIE

Bit 3: DTIMEOUTIE.

TXUNDERRIE

Bit 4: TXUNDERRIE.

RXOVERRIE

Bit 5: RXOVERRIE.

CMDRENDIE

Bit 6: CMDRENDIE.

CMDSENTIE

Bit 7: CMDSENTIE.

DATAENDIE

Bit 8: DATAENDIE.

DHOLDIE

Bit 9: DHOLDIE.

DBCKENDIE

Bit 10: DBCKENDIE.

DABORTIE

Bit 11: DABORTIE.

TXFIFOHEIE

Bit 14: TXFIFOHEIE.

RXFIFOHFIE

Bit 15: RXFIFOHFIE.

RXFIFOFIE

Bit 17: RXFIFOFIE.

TXFIFOEIE

Bit 18: TXFIFOEIE.

BUSYD0ENDIE

Bit 21: BUSYD0ENDIE.

SDIOITIE

Bit 22: SDIOITIE.

ACKFAILIE

Bit 23: ACKFAILIE.

ACKTIMEOUTIE

Bit 24: ACKTIMEOUTIE.

VSWENDIE

Bit 25: VSWENDIE.

CKSTOPIE

Bit 26: CKSTOPIE.

IDMABTCIE

Bit 28: IDMABTCIE.

ACKTIMER

The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set.

Offset: 0x40, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACKTIME
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACKTIME
rw
Toggle fields

ACKTIME

Bits 0-24: ACKTIME.

IDMACTRLR

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABMODE
rw 		IDMAEN
rw
Toggle fields

IDMAEN

Bit 0: IDMAEN.

IDMABMODE

Bit 1: IDMABMODE.

IDMABSIZER

The SDMMC_IDMABSIZER register contains the buffer size when in linked list configuration.

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABNDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABNDT
rw
Toggle fields

IDMABNDT

Bits 5-16: IDMABNDT.

IDMABASER

The SDMMC_IDMABASER register contains the memory buffer base address in single buffer configuration and linked list configuration.

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABASE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABASE
rw
Toggle fields

IDMABASE

Bits 0-31: IDMABASE.

IDMALAR

SDMMC IDMA linked list address register

Offset: 0x64, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ULA
rw 		ULS
rw 		ABR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMALA
rw
Toggle fields

IDMALA

Bits 2-15: IDMALA.

ABR

Bit 29: ABR.

ULS

Bit 30: ULS.

ULA

Bit 31: ULA.

IDMABAR

SDMMC IDMA linked list memory base register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IDMABA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IDMABA
rw
Toggle fields

IDMABA

Bits 2-31: IDMABA.

FIFOR0

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x80, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR1

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x84, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR2

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x88, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR3

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x8c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR4

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x90, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR5

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x94, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR6

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x98, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR7

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0x9c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR8

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR9

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR10

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xa8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR11

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xac, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR12

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR13

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR14

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xb8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

FIFOR15

The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO. The FIFO register interface takes care of correct data alignment inside the FIFO, the FIFO register address used by the CPU does matter. When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated.

Offset: 0xbc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIFODATA
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFODATA
rw
Toggle fields

FIFODATA

Bits 0-31: FIFODATA.

VERR

SDMMC version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SDMMC identification register

Offset: 0x3f8, size: 32, reset: 0x00140022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP_ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP_ID
r
Toggle fields

IP_ID

Bits 0-31: IP_ID.

SIDR

SDMMC size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPDIFRX

0x4000d000: SPDIFRX

25/51 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR
0x4 IMR
0x8 SR
0xc IFCR
0x10 FMT0_DR
0x14 CSR
0x18 DIR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

Control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKSBKPEN
rw 		CKSEN
rw 		INSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WFA
rw 		NBTR
rw 		CHSEL
rw 		CBDMAEN
rw 		PTMSK
rw 		CUMSK
rw 		VMSK
rw 		PMSK
rw 		DRFMT
rw 		RXSTEO
rw 		RXDMAEN
rw 		SPDIFRXEN
rw
Toggle fields

SPDIFRXEN

Bits 0-1: SPDIFRXEN.

RXDMAEN

Bit 2: RXDMAEN.

RXSTEO

Bit 3: RXSTEO.

DRFMT

Bits 4-5: DRFMT.

PMSK

Bit 6: PMSK.

VMSK

Bit 7: VMSK.

CUMSK

Bit 8: CUMSK.

PTMSK

Bit 9: PTMSK.

CBDMAEN

Bit 10: CBDMAEN.

CHSEL

Bit 11: CHSEL.

NBTR

Bits 12-13: NBTR.

WFA

Bit 14: WFA.

INSEL

Bits 16-18: INSEL.

CKSEN

Bit 20: CKSEN.

CKSBKPEN

Bit 21: CKSBKPEN.

IMR

Interrupt mask register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFEIE
rw 		SYNCDIE
rw 		SBLKIE
rw 		OVRIE
rw 		PERRIE
rw 		CSRNEIE
rw 		RXNEIE
rw
Toggle fields

RXNEIE

Bit 0: RXNEIE.

CSRNEIE

Bit 1: CSRNEIE.

PERRIE

Bit 2: PERRIE.

OVRIE

Bit 3: OVRIE.

SBLKIE

Bit 4: SBLKIE.

SYNCDIE

Bit 5: SYNCDIE.

IFEIE

Bit 6: IFEIE.

SR

Status register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-only

10/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WIDTH5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TERR
r 		SERR
r 		FERR
r 		SYNCD
r 		SBD
r 		OVR
r 		PERR
r 		CSRNE
r 		RXNE
r
Toggle fields

RXNE

Bit 0: RXNE.

CSRNE

Bit 1: CSRNE.

PERR

Bit 2: PERR.

OVR

Bit 3: OVR.

SBD

Bit 4: SBD.

SYNCD

Bit 5: SYNCD.

FERR

Bit 6: FERR.

SERR

Bit 7: SERR.

TERR

Bit 8: TERR.

WIDTH5

Bits 16-30: WIDTH5.

IFCR

Interrupt flag clear register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNCDCF
w 		SBDCF
w 		OVRCF
w 		PERRCF
w
Toggle fields

PERRCF

Bit 2: PERRCF.

OVRCF

Bit 3: OVRCF.

SBDCF

Bit 4: SBDCF.

SYNCDCF

Bit 5: SYNCDCF.

FMT0_DR

This register can take 3 different formats according to DRFMT. Here is the format when DRFMT = 00:

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

6/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PT
r 		C
r 		U
r 		V
r 		PE
r 		DR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR
r
Toggle fields

DR

Bits 0-23: DR.

PE

Bit 24: PE.

V

Bit 25: V.

U

Bit 26: U.

C

Bit 27: C.

PT

Bits 28-29: PT.

CSR

Channel status register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SOB
r 		CS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USR
r
Toggle fields

USR

Bits 0-15: USR.

CS

Bits 16-23: CS.

SOB

Bit 24: SOB.

DIR

Debug information register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TLO
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
THI
r
Toggle fields

THI

Bits 0-12: THI.

TLO

Bits 16-28: TLO.

VERR

SPDIFRX version register

Offset: 0x3f4, size: 32, reset: 0x00000012, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPDIFRX identification register

Offset: 0x3f8, size: 32, reset: 0x00130041, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPDIFRX size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPI1

0x44004000: SPI1

32/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SPI2S_CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 SPI2S_IER
0x14 SPI2S_SR
0x18 SPI2S_IFCR
0x20 SPI2S_TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x30 SPI2S_RXDR
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
0x3f0 I2S_HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

SPI2S_CR1

SPI/I2S control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw 		RCRCINI
rw 		CRC33_17
rw 		SSI
rw 		HDDIR
rw 		CSUSP
w 		CSTART
rw 		MASRX
rw 		SPE
rw
Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

SPI control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: TSIZE.

TSER

Bits 16-31: TSER.

CFG1

Content of this register is write protected when SPI is enabled

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw 		CRCEN
rw 		CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw 		RXDMAEN
rw 		UDRDET
rw 		UDRCFG
rw 		FTHLV
rw 		DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: DSIZE.

FTHLV

Bits 5-8: FTHLV.

UDRCFG

Bits 9-10: UDRCFG.

UDRDET

Bits 11-12: UDRDET.

RXDMAEN

Bit 14: RXDMAEN.

TXDMAEN

Bit 15: TXDMAEN.

CRCSIZE

Bits 16-20: CRCSIZE.

CRCEN

Bit 22: CRCEN.

MBR

Bits 28-30: MBR.

CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw 		SSOM
rw 		SSOE
rw 		SSIOP
rw 		SSM
rw 		CPOL
rw 		CPHA
rw 		LSBFRST
rw 		MASTER
rw 		SP
rw 		COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw 		MIDI
rw 		MSSI
rw
Toggle fields

MSSI

Bits 0-3: MSSI.

MIDI

Bits 4-7: MIDI.

IOSWP

Bit 15: IOSWP.

COMM

Bits 17-18: COMM.

SP

Bits 19-21: SP.

MASTER

Bit 22: MASTER.

LSBFRST

Bit 23: LSBFRST.

CPHA

Bit 24: CPHA.

CPOL

Bit 25: CPOL.

SSM

Bit 26: SSM.

SSIOP

Bit 28: SSIOP.

SSOE

Bit 29: SSOE.

SSOM

Bit 30: SSOM.

AFCNTR

Bit 31: AFCNTR.

SPI2S_IER

SPI/I2S interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw 		MODFIE
rw 		TIFREIE
rw 		CRCEIE
rw 		OVRIE
rw 		UDRIE
rw 		TXTFIE
rw 		EOTIE
rw 		DXPIE
rw 		TXPIE
rw 		RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXPIE.

TXPIE

Bit 1: TXPIE.

DXPIE

Bit 2: DXPIE.

EOTIE

Bit 3: EOTIE.

TXTFIE

Bit 4: TXTFIE.

UDRIE

Bit 5: UDRIE.

OVRIE

Bit 6: OVRIE.

CRCEIE

Bit 7: CRCEIE.

TIFREIE

Bit 8: TIFREIE.

MODFIE

Bit 9: MODFIE.

TSERFIE

Bit 10: TSERFIE.

SPI2S_SR

SPI/I2S status register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r 		RXPLVL
r 		TXC
r 		SUSP
r 		TSERF
r 		MODF
r 		TIFRE
r 		CRCE
r 		OVR
r 		UDR
r 		TXTF
r 		EOT
r 		DXP
r 		TXP
r 		RXP
r
Toggle fields

RXP

Bit 0: RXP.

TXP

Bit 1: TXP.

DXP

Bit 2: DXP.

EOT

Bit 3: EOT.

TXTF

Bit 4: TXTF.

UDR

Bit 5: UDR.

OVR

Bit 6: OVR.

CRCE

Bit 7: CRCE.

TIFRE

Bit 8: TIFRE.

MODF

Bit 9: MODF.

TSERF

Bit 10: TSERF.

SUSP

Bit 11: SUSP.

TXC

Bit 12: TXC.

RXPLVL

Bits 13-14: RXPLVL.

RXWNE

Bit 15: RXWNE.

CTSIZE

Bits 16-31: CTSIZE.

SPI2S_IFCR

SPI/I2S interrupt/status flags clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w 		TSERFC
w 		MODFC
w 		TIFREC
w 		CRCEC
w 		OVRC
w 		UDRC
w 		TXTFC
w 		EOTC
w
Toggle fields

EOTC

Bit 3: EOTC.

TXTFC

Bit 4: TXTFC.

UDRC

Bit 5: UDRC.

OVRC

Bit 6: OVRC.

CRCEC

Bit 7: CRCEC.

TIFREC

Bit 8: TIFREC.

MODFC

Bit 9: MODFC.

TSERFC

Bit 10: TSERFC.

SUSPC

Bit 11: SUSPC.

SPI2S_TXDR

SPI/I2S transmit data register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: TXDR.

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

SPI2S_RXDR

SPI/I2S receive data register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: RXDR.

CRCPOLY

SPI polynomial register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRCPOLY.

TXCRC

SPI transmitter CRC register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: TXCRC.

RXCRC

SPI receiver CRC register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: RXCRC.

UDRDR

SPI underrun data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: UDRDR.

I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw 		ODD
rw 		I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw 		WSINV
rw 		FIXCH
rw 		CKPOL
rw 		CHLEN
rw 		DATLEN
rw 		PCMSYNC
rw 		I2SSTD
rw 		I2SCFG
rw 		I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2SMOD.

I2SCFG

Bits 1-3: I2SCFG.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

DATLEN

Bits 8-9: DATLEN.

CHLEN

Bit 10: CHLEN.

CKPOL

Bit 11: CKPOL.

FIXCH

Bit 12: FIXCH.

WSINV

Bit 13: WSINV.

DATFMT

Bit 14: DATFMT.

I2SDIV

Bits 16-23: I2SDIV.

ODD

Bit 24: ODD.

MCKOE

Bit 25: MCKOE.

I2S_HWCFGR

SPI/I2S hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SCFG
r 		CRCCFG
r 		RXFCFG
r 		TXFCFG
r
Toggle fields

TXFCFG

Bits 0-3: TXFCFG.

RXFCFG

Bits 4-7: RXFCFG.

CRCCFG

Bits 8-11: CRCCFG.

I2SCFG

Bits 12-15: I2SCFG.

DSCFG

Bits 16-19: DSCFG.

VERR

SPI/I2S version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPI/I2S identification register

Offset: 0x3f8, size: 32, reset: 0x00130022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPI/I2S size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPI2

0x4000b000: SPI1

32/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SPI2S_CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 SPI2S_IER
0x14 SPI2S_SR
0x18 SPI2S_IFCR
0x20 SPI2S_TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x30 SPI2S_RXDR
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
0x3f0 I2S_HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

SPI2S_CR1

SPI/I2S control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw 		RCRCINI
rw 		CRC33_17
rw 		SSI
rw 		HDDIR
rw 		CSUSP
w 		CSTART
rw 		MASRX
rw 		SPE
rw
Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

SPI control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: TSIZE.

TSER

Bits 16-31: TSER.

CFG1

Content of this register is write protected when SPI is enabled

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw 		CRCEN
rw 		CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw 		RXDMAEN
rw 		UDRDET
rw 		UDRCFG
rw 		FTHLV
rw 		DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: DSIZE.

FTHLV

Bits 5-8: FTHLV.

UDRCFG

Bits 9-10: UDRCFG.

UDRDET

Bits 11-12: UDRDET.

RXDMAEN

Bit 14: RXDMAEN.

TXDMAEN

Bit 15: TXDMAEN.

CRCSIZE

Bits 16-20: CRCSIZE.

CRCEN

Bit 22: CRCEN.

MBR

Bits 28-30: MBR.

CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw 		SSOM
rw 		SSOE
rw 		SSIOP
rw 		SSM
rw 		CPOL
rw 		CPHA
rw 		LSBFRST
rw 		MASTER
rw 		SP
rw 		COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw 		MIDI
rw 		MSSI
rw
Toggle fields

MSSI

Bits 0-3: MSSI.

MIDI

Bits 4-7: MIDI.

IOSWP

Bit 15: IOSWP.

COMM

Bits 17-18: COMM.

SP

Bits 19-21: SP.

MASTER

Bit 22: MASTER.

LSBFRST

Bit 23: LSBFRST.

CPHA

Bit 24: CPHA.

CPOL

Bit 25: CPOL.

SSM

Bit 26: SSM.

SSIOP

Bit 28: SSIOP.

SSOE

Bit 29: SSOE.

SSOM

Bit 30: SSOM.

AFCNTR

Bit 31: AFCNTR.

SPI2S_IER

SPI/I2S interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw 		MODFIE
rw 		TIFREIE
rw 		CRCEIE
rw 		OVRIE
rw 		UDRIE
rw 		TXTFIE
rw 		EOTIE
rw 		DXPIE
rw 		TXPIE
rw 		RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXPIE.

TXPIE

Bit 1: TXPIE.

DXPIE

Bit 2: DXPIE.

EOTIE

Bit 3: EOTIE.

TXTFIE

Bit 4: TXTFIE.

UDRIE

Bit 5: UDRIE.

OVRIE

Bit 6: OVRIE.

CRCEIE

Bit 7: CRCEIE.

TIFREIE

Bit 8: TIFREIE.

MODFIE

Bit 9: MODFIE.

TSERFIE

Bit 10: TSERFIE.

SPI2S_SR

SPI/I2S status register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r 		RXPLVL
r 		TXC
r 		SUSP
r 		TSERF
r 		MODF
r 		TIFRE
r 		CRCE
r 		OVR
r 		UDR
r 		TXTF
r 		EOT
r 		DXP
r 		TXP
r 		RXP
r
Toggle fields

RXP

Bit 0: RXP.

TXP

Bit 1: TXP.

DXP

Bit 2: DXP.

EOT

Bit 3: EOT.

TXTF

Bit 4: TXTF.

UDR

Bit 5: UDR.

OVR

Bit 6: OVR.

CRCE

Bit 7: CRCE.

TIFRE

Bit 8: TIFRE.

MODF

Bit 9: MODF.

TSERF

Bit 10: TSERF.

SUSP

Bit 11: SUSP.

TXC

Bit 12: TXC.

RXPLVL

Bits 13-14: RXPLVL.

RXWNE

Bit 15: RXWNE.

CTSIZE

Bits 16-31: CTSIZE.

SPI2S_IFCR

SPI/I2S interrupt/status flags clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w 		TSERFC
w 		MODFC
w 		TIFREC
w 		CRCEC
w 		OVRC
w 		UDRC
w 		TXTFC
w 		EOTC
w
Toggle fields

EOTC

Bit 3: EOTC.

TXTFC

Bit 4: TXTFC.

UDRC

Bit 5: UDRC.

OVRC

Bit 6: OVRC.

CRCEC

Bit 7: CRCEC.

TIFREC

Bit 8: TIFREC.

MODFC

Bit 9: MODFC.

TSERFC

Bit 10: TSERFC.

SUSPC

Bit 11: SUSPC.

SPI2S_TXDR

SPI/I2S transmit data register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: TXDR.

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

SPI2S_RXDR

SPI/I2S receive data register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: RXDR.

CRCPOLY

SPI polynomial register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRCPOLY.

TXCRC

SPI transmitter CRC register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: TXCRC.

RXCRC

SPI receiver CRC register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: RXCRC.

UDRDR

SPI underrun data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: UDRDR.

I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw 		ODD
rw 		I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw 		WSINV
rw 		FIXCH
rw 		CKPOL
rw 		CHLEN
rw 		DATLEN
rw 		PCMSYNC
rw 		I2SSTD
rw 		I2SCFG
rw 		I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2SMOD.

I2SCFG

Bits 1-3: I2SCFG.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

DATLEN

Bits 8-9: DATLEN.

CHLEN

Bit 10: CHLEN.

CKPOL

Bit 11: CKPOL.

FIXCH

Bit 12: FIXCH.

WSINV

Bit 13: WSINV.

DATFMT

Bit 14: DATFMT.

I2SDIV

Bits 16-23: I2SDIV.

ODD

Bit 24: ODD.

MCKOE

Bit 25: MCKOE.

I2S_HWCFGR

SPI/I2S hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SCFG
r 		CRCCFG
r 		RXFCFG
r 		TXFCFG
r
Toggle fields

TXFCFG

Bits 0-3: TXFCFG.

RXFCFG

Bits 4-7: RXFCFG.

CRCCFG

Bits 8-11: CRCCFG.

I2SCFG

Bits 12-15: I2SCFG.

DSCFG

Bits 16-19: DSCFG.

VERR

SPI/I2S version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPI/I2S identification register

Offset: 0x3f8, size: 32, reset: 0x00130022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPI/I2S size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPI3

0x4000c000: SPI1

32/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SPI2S_CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 SPI2S_IER
0x14 SPI2S_SR
0x18 SPI2S_IFCR
0x20 SPI2S_TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x30 SPI2S_RXDR
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
0x3f0 I2S_HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

SPI2S_CR1

SPI/I2S control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw 		RCRCINI
rw 		CRC33_17
rw 		SSI
rw 		HDDIR
rw 		CSUSP
w 		CSTART
rw 		MASRX
rw 		SPE
rw
Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

SPI control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: TSIZE.

TSER

Bits 16-31: TSER.

CFG1

Content of this register is write protected when SPI is enabled

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw 		CRCEN
rw 		CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw 		RXDMAEN
rw 		UDRDET
rw 		UDRCFG
rw 		FTHLV
rw 		DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: DSIZE.

FTHLV

Bits 5-8: FTHLV.

UDRCFG

Bits 9-10: UDRCFG.

UDRDET

Bits 11-12: UDRDET.

RXDMAEN

Bit 14: RXDMAEN.

TXDMAEN

Bit 15: TXDMAEN.

CRCSIZE

Bits 16-20: CRCSIZE.

CRCEN

Bit 22: CRCEN.

MBR

Bits 28-30: MBR.

CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw 		SSOM
rw 		SSOE
rw 		SSIOP
rw 		SSM
rw 		CPOL
rw 		CPHA
rw 		LSBFRST
rw 		MASTER
rw 		SP
rw 		COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw 		MIDI
rw 		MSSI
rw
Toggle fields

MSSI

Bits 0-3: MSSI.

MIDI

Bits 4-7: MIDI.

IOSWP

Bit 15: IOSWP.

COMM

Bits 17-18: COMM.

SP

Bits 19-21: SP.

MASTER

Bit 22: MASTER.

LSBFRST

Bit 23: LSBFRST.

CPHA

Bit 24: CPHA.

CPOL

Bit 25: CPOL.

SSM

Bit 26: SSM.

SSIOP

Bit 28: SSIOP.

SSOE

Bit 29: SSOE.

SSOM

Bit 30: SSOM.

AFCNTR

Bit 31: AFCNTR.

SPI2S_IER

SPI/I2S interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw 		MODFIE
rw 		TIFREIE
rw 		CRCEIE
rw 		OVRIE
rw 		UDRIE
rw 		TXTFIE
rw 		EOTIE
rw 		DXPIE
rw 		TXPIE
rw 		RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXPIE.

TXPIE

Bit 1: TXPIE.

DXPIE

Bit 2: DXPIE.

EOTIE

Bit 3: EOTIE.

TXTFIE

Bit 4: TXTFIE.

UDRIE

Bit 5: UDRIE.

OVRIE

Bit 6: OVRIE.

CRCEIE

Bit 7: CRCEIE.

TIFREIE

Bit 8: TIFREIE.

MODFIE

Bit 9: MODFIE.

TSERFIE

Bit 10: TSERFIE.

SPI2S_SR

SPI/I2S status register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r 		RXPLVL
r 		TXC
r 		SUSP
r 		TSERF
r 		MODF
r 		TIFRE
r 		CRCE
r 		OVR
r 		UDR
r 		TXTF
r 		EOT
r 		DXP
r 		TXP
r 		RXP
r
Toggle fields

RXP

Bit 0: RXP.

TXP

Bit 1: TXP.

DXP

Bit 2: DXP.

EOT

Bit 3: EOT.

TXTF

Bit 4: TXTF.

UDR

Bit 5: UDR.

OVR

Bit 6: OVR.

CRCE

Bit 7: CRCE.

TIFRE

Bit 8: TIFRE.

MODF

Bit 9: MODF.

TSERF

Bit 10: TSERF.

SUSP

Bit 11: SUSP.

TXC

Bit 12: TXC.

RXPLVL

Bits 13-14: RXPLVL.

RXWNE

Bit 15: RXWNE.

CTSIZE

Bits 16-31: CTSIZE.

SPI2S_IFCR

SPI/I2S interrupt/status flags clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w 		TSERFC
w 		MODFC
w 		TIFREC
w 		CRCEC
w 		OVRC
w 		UDRC
w 		TXTFC
w 		EOTC
w
Toggle fields

EOTC

Bit 3: EOTC.

TXTFC

Bit 4: TXTFC.

UDRC

Bit 5: UDRC.

OVRC

Bit 6: OVRC.

CRCEC

Bit 7: CRCEC.

TIFREC

Bit 8: TIFREC.

MODFC

Bit 9: MODFC.

TSERFC

Bit 10: TSERFC.

SUSPC

Bit 11: SUSPC.

SPI2S_TXDR

SPI/I2S transmit data register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: TXDR.

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

SPI2S_RXDR

SPI/I2S receive data register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: RXDR.

CRCPOLY

SPI polynomial register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRCPOLY.

TXCRC

SPI transmitter CRC register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: TXCRC.

RXCRC

SPI receiver CRC register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: RXCRC.

UDRDR

SPI underrun data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: UDRDR.

I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw 		ODD
rw 		I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw 		WSINV
rw 		FIXCH
rw 		CKPOL
rw 		CHLEN
rw 		DATLEN
rw 		PCMSYNC
rw 		I2SSTD
rw 		I2SCFG
rw 		I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2SMOD.

I2SCFG

Bits 1-3: I2SCFG.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

DATLEN

Bits 8-9: DATLEN.

CHLEN

Bit 10: CHLEN.

CKPOL

Bit 11: CKPOL.

FIXCH

Bit 12: FIXCH.

WSINV

Bit 13: WSINV.

DATFMT

Bit 14: DATFMT.

I2SDIV

Bits 16-23: I2SDIV.

ODD

Bit 24: ODD.

MCKOE

Bit 25: MCKOE.

I2S_HWCFGR

SPI/I2S hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SCFG
r 		CRCCFG
r 		RXFCFG
r 		TXFCFG
r
Toggle fields

TXFCFG

Bits 0-3: TXFCFG.

RXFCFG

Bits 4-7: RXFCFG.

CRCCFG

Bits 8-11: CRCCFG.

I2SCFG

Bits 12-15: I2SCFG.

DSCFG

Bits 16-19: DSCFG.

VERR

SPI/I2S version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPI/I2S identification register

Offset: 0x3f8, size: 32, reset: 0x00130022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPI/I2S size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPI4

0x44005000: SPI1

32/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SPI2S_CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 SPI2S_IER
0x14 SPI2S_SR
0x18 SPI2S_IFCR
0x20 SPI2S_TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x30 SPI2S_RXDR
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
0x3f0 I2S_HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

SPI2S_CR1

SPI/I2S control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw 		RCRCINI
rw 		CRC33_17
rw 		SSI
rw 		HDDIR
rw 		CSUSP
w 		CSTART
rw 		MASRX
rw 		SPE
rw
Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

SPI control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: TSIZE.

TSER

Bits 16-31: TSER.

CFG1

Content of this register is write protected when SPI is enabled

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw 		CRCEN
rw 		CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw 		RXDMAEN
rw 		UDRDET
rw 		UDRCFG
rw 		FTHLV
rw 		DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: DSIZE.

FTHLV

Bits 5-8: FTHLV.

UDRCFG

Bits 9-10: UDRCFG.

UDRDET

Bits 11-12: UDRDET.

RXDMAEN

Bit 14: RXDMAEN.

TXDMAEN

Bit 15: TXDMAEN.

CRCSIZE

Bits 16-20: CRCSIZE.

CRCEN

Bit 22: CRCEN.

MBR

Bits 28-30: MBR.

CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw 		SSOM
rw 		SSOE
rw 		SSIOP
rw 		SSM
rw 		CPOL
rw 		CPHA
rw 		LSBFRST
rw 		MASTER
rw 		SP
rw 		COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw 		MIDI
rw 		MSSI
rw
Toggle fields

MSSI

Bits 0-3: MSSI.

MIDI

Bits 4-7: MIDI.

IOSWP

Bit 15: IOSWP.

COMM

Bits 17-18: COMM.

SP

Bits 19-21: SP.

MASTER

Bit 22: MASTER.

LSBFRST

Bit 23: LSBFRST.

CPHA

Bit 24: CPHA.

CPOL

Bit 25: CPOL.

SSM

Bit 26: SSM.

SSIOP

Bit 28: SSIOP.

SSOE

Bit 29: SSOE.

SSOM

Bit 30: SSOM.

AFCNTR

Bit 31: AFCNTR.

SPI2S_IER

SPI/I2S interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw 		MODFIE
rw 		TIFREIE
rw 		CRCEIE
rw 		OVRIE
rw 		UDRIE
rw 		TXTFIE
rw 		EOTIE
rw 		DXPIE
rw 		TXPIE
rw 		RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXPIE.

TXPIE

Bit 1: TXPIE.

DXPIE

Bit 2: DXPIE.

EOTIE

Bit 3: EOTIE.

TXTFIE

Bit 4: TXTFIE.

UDRIE

Bit 5: UDRIE.

OVRIE

Bit 6: OVRIE.

CRCEIE

Bit 7: CRCEIE.

TIFREIE

Bit 8: TIFREIE.

MODFIE

Bit 9: MODFIE.

TSERFIE

Bit 10: TSERFIE.

SPI2S_SR

SPI/I2S status register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r 		RXPLVL
r 		TXC
r 		SUSP
r 		TSERF
r 		MODF
r 		TIFRE
r 		CRCE
r 		OVR
r 		UDR
r 		TXTF
r 		EOT
r 		DXP
r 		TXP
r 		RXP
r
Toggle fields

RXP

Bit 0: RXP.

TXP

Bit 1: TXP.

DXP

Bit 2: DXP.

EOT

Bit 3: EOT.

TXTF

Bit 4: TXTF.

UDR

Bit 5: UDR.

OVR

Bit 6: OVR.

CRCE

Bit 7: CRCE.

TIFRE

Bit 8: TIFRE.

MODF

Bit 9: MODF.

TSERF

Bit 10: TSERF.

SUSP

Bit 11: SUSP.

TXC

Bit 12: TXC.

RXPLVL

Bits 13-14: RXPLVL.

RXWNE

Bit 15: RXWNE.

CTSIZE

Bits 16-31: CTSIZE.

SPI2S_IFCR

SPI/I2S interrupt/status flags clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w 		TSERFC
w 		MODFC
w 		TIFREC
w 		CRCEC
w 		OVRC
w 		UDRC
w 		TXTFC
w 		EOTC
w
Toggle fields

EOTC

Bit 3: EOTC.

TXTFC

Bit 4: TXTFC.

UDRC

Bit 5: UDRC.

OVRC

Bit 6: OVRC.

CRCEC

Bit 7: CRCEC.

TIFREC

Bit 8: TIFREC.

MODFC

Bit 9: MODFC.

TSERFC

Bit 10: TSERFC.

SUSPC

Bit 11: SUSPC.

SPI2S_TXDR

SPI/I2S transmit data register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: TXDR.

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

SPI2S_RXDR

SPI/I2S receive data register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: RXDR.

CRCPOLY

SPI polynomial register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRCPOLY.

TXCRC

SPI transmitter CRC register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: TXCRC.

RXCRC

SPI receiver CRC register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: RXCRC.

UDRDR

SPI underrun data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: UDRDR.

I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw 		ODD
rw 		I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw 		WSINV
rw 		FIXCH
rw 		CKPOL
rw 		CHLEN
rw 		DATLEN
rw 		PCMSYNC
rw 		I2SSTD
rw 		I2SCFG
rw 		I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2SMOD.

I2SCFG

Bits 1-3: I2SCFG.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

DATLEN

Bits 8-9: DATLEN.

CHLEN

Bit 10: CHLEN.

CKPOL

Bit 11: CKPOL.

FIXCH

Bit 12: FIXCH.

WSINV

Bit 13: WSINV.

DATFMT

Bit 14: DATFMT.

I2SDIV

Bits 16-23: I2SDIV.

ODD

Bit 24: ODD.

MCKOE

Bit 25: MCKOE.

I2S_HWCFGR

SPI/I2S hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SCFG
r 		CRCCFG
r 		RXFCFG
r 		TXFCFG
r
Toggle fields

TXFCFG

Bits 0-3: TXFCFG.

RXFCFG

Bits 4-7: RXFCFG.

CRCCFG

Bits 8-11: CRCCFG.

I2SCFG

Bits 12-15: I2SCFG.

DSCFG

Bits 16-19: DSCFG.

VERR

SPI/I2S version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPI/I2S identification register

Offset: 0x3f8, size: 32, reset: 0x00130022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPI/I2S size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPI5

0x44009000: SPI1

32/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SPI2S_CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 SPI2S_IER
0x14 SPI2S_SR
0x18 SPI2S_IFCR
0x20 SPI2S_TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x30 SPI2S_RXDR
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
0x3f0 I2S_HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

SPI2S_CR1

SPI/I2S control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw 		RCRCINI
rw 		CRC33_17
rw 		SSI
rw 		HDDIR
rw 		CSUSP
w 		CSTART
rw 		MASRX
rw 		SPE
rw
Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

SPI control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: TSIZE.

TSER

Bits 16-31: TSER.

CFG1

Content of this register is write protected when SPI is enabled

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw 		CRCEN
rw 		CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw 		RXDMAEN
rw 		UDRDET
rw 		UDRCFG
rw 		FTHLV
rw 		DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: DSIZE.

FTHLV

Bits 5-8: FTHLV.

UDRCFG

Bits 9-10: UDRCFG.

UDRDET

Bits 11-12: UDRDET.

RXDMAEN

Bit 14: RXDMAEN.

TXDMAEN

Bit 15: TXDMAEN.

CRCSIZE

Bits 16-20: CRCSIZE.

CRCEN

Bit 22: CRCEN.

MBR

Bits 28-30: MBR.

CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw 		SSOM
rw 		SSOE
rw 		SSIOP
rw 		SSM
rw 		CPOL
rw 		CPHA
rw 		LSBFRST
rw 		MASTER
rw 		SP
rw 		COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw 		MIDI
rw 		MSSI
rw
Toggle fields

MSSI

Bits 0-3: MSSI.

MIDI

Bits 4-7: MIDI.

IOSWP

Bit 15: IOSWP.

COMM

Bits 17-18: COMM.

SP

Bits 19-21: SP.

MASTER

Bit 22: MASTER.

LSBFRST

Bit 23: LSBFRST.

CPHA

Bit 24: CPHA.

CPOL

Bit 25: CPOL.

SSM

Bit 26: SSM.

SSIOP

Bit 28: SSIOP.

SSOE

Bit 29: SSOE.

SSOM

Bit 30: SSOM.

AFCNTR

Bit 31: AFCNTR.

SPI2S_IER

SPI/I2S interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw 		MODFIE
rw 		TIFREIE
rw 		CRCEIE
rw 		OVRIE
rw 		UDRIE
rw 		TXTFIE
rw 		EOTIE
rw 		DXPIE
rw 		TXPIE
rw 		RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXPIE.

TXPIE

Bit 1: TXPIE.

DXPIE

Bit 2: DXPIE.

EOTIE

Bit 3: EOTIE.

TXTFIE

Bit 4: TXTFIE.

UDRIE

Bit 5: UDRIE.

OVRIE

Bit 6: OVRIE.

CRCEIE

Bit 7: CRCEIE.

TIFREIE

Bit 8: TIFREIE.

MODFIE

Bit 9: MODFIE.

TSERFIE

Bit 10: TSERFIE.

SPI2S_SR

SPI/I2S status register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r 		RXPLVL
r 		TXC
r 		SUSP
r 		TSERF
r 		MODF
r 		TIFRE
r 		CRCE
r 		OVR
r 		UDR
r 		TXTF
r 		EOT
r 		DXP
r 		TXP
r 		RXP
r
Toggle fields

RXP

Bit 0: RXP.

TXP

Bit 1: TXP.

DXP

Bit 2: DXP.

EOT

Bit 3: EOT.

TXTF

Bit 4: TXTF.

UDR

Bit 5: UDR.

OVR

Bit 6: OVR.

CRCE

Bit 7: CRCE.

TIFRE

Bit 8: TIFRE.

MODF

Bit 9: MODF.

TSERF

Bit 10: TSERF.

SUSP

Bit 11: SUSP.

TXC

Bit 12: TXC.

RXPLVL

Bits 13-14: RXPLVL.

RXWNE

Bit 15: RXWNE.

CTSIZE

Bits 16-31: CTSIZE.

SPI2S_IFCR

SPI/I2S interrupt/status flags clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w 		TSERFC
w 		MODFC
w 		TIFREC
w 		CRCEC
w 		OVRC
w 		UDRC
w 		TXTFC
w 		EOTC
w
Toggle fields

EOTC

Bit 3: EOTC.

TXTFC

Bit 4: TXTFC.

UDRC

Bit 5: UDRC.

OVRC

Bit 6: OVRC.

CRCEC

Bit 7: CRCEC.

TIFREC

Bit 8: TIFREC.

MODFC

Bit 9: MODFC.

TSERFC

Bit 10: TSERFC.

SUSPC

Bit 11: SUSPC.

SPI2S_TXDR

SPI/I2S transmit data register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: TXDR.

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

SPI2S_RXDR

SPI/I2S receive data register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: RXDR.

CRCPOLY

SPI polynomial register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRCPOLY.

TXCRC

SPI transmitter CRC register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: TXCRC.

RXCRC

SPI receiver CRC register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: RXCRC.

UDRDR

SPI underrun data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: UDRDR.

I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw 		ODD
rw 		I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw 		WSINV
rw 		FIXCH
rw 		CKPOL
rw 		CHLEN
rw 		DATLEN
rw 		PCMSYNC
rw 		I2SSTD
rw 		I2SCFG
rw 		I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2SMOD.

I2SCFG

Bits 1-3: I2SCFG.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

DATLEN

Bits 8-9: DATLEN.

CHLEN

Bit 10: CHLEN.

CKPOL

Bit 11: CKPOL.

FIXCH

Bit 12: FIXCH.

WSINV

Bit 13: WSINV.

DATFMT

Bit 14: DATFMT.

I2SDIV

Bits 16-23: I2SDIV.

ODD

Bit 24: ODD.

MCKOE

Bit 25: MCKOE.

I2S_HWCFGR

SPI/I2S hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SCFG
r 		CRCCFG
r 		RXFCFG
r 		TXFCFG
r
Toggle fields

TXFCFG

Bits 0-3: TXFCFG.

RXFCFG

Bits 4-7: RXFCFG.

CRCCFG

Bits 8-11: CRCCFG.

I2SCFG

Bits 12-15: I2SCFG.

DSCFG

Bits 16-19: DSCFG.

VERR

SPI/I2S version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPI/I2S identification register

Offset: 0x3f8, size: 32, reset: 0x00130022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPI/I2S size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

SPI6

0x5c001000: SPI1

32/103 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 SPI2S_CR1
0x4 CR2
0x8 CFG1
0xc CFG2
0x10 SPI2S_IER
0x14 SPI2S_SR
0x18 SPI2S_IFCR
0x20 SPI2S_TXDR
0x20 (16-bit) TXDR16
0x20 (8-bit) TXDR8
0x30 (16-bit) RXDR16
0x30 (8-bit) RXDR8
0x30 SPI2S_RXDR
0x40 CRCPOLY
0x44 TXCRC
0x48 RXCRC
0x4c UDRDR
0x50 I2SCFGR
0x3f0 I2S_HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

SPI2S_CR1

SPI/I2S control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IOLOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCRCINI
rw 		RCRCINI
rw 		CRC33_17
rw 		SSI
rw 		HDDIR
rw 		CSUSP
w 		CSTART
rw 		MASRX
rw 		SPE
rw
Toggle fields

SPE

Bit 0: SPE.

MASRX

Bit 8: MASRX.

CSTART

Bit 9: CSTART.

CSUSP

Bit 10: CSUSP.

HDDIR

Bit 11: HDDIR.

SSI

Bit 12: SSI.

CRC33_17

Bit 13: CRC33_17.

RCRCINI

Bit 14: RCRCINI.

TCRCINI

Bit 15: TCRCINI.

IOLOCK

Bit 16: IOLOCK.

CR2

SPI control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSER
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSIZE
rw
Toggle fields

TSIZE

Bits 0-15: TSIZE.

TSER

Bits 16-31: TSER.

CFG1

Content of this register is write protected when SPI is enabled

Offset: 0x8, size: 32, reset: 0x00070007, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MBR
rw 		CRCEN
rw 		CRCSIZE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDMAEN
rw 		RXDMAEN
rw 		UDRDET
rw 		UDRCFG
rw 		FTHLV
rw 		DSIZE
rw
Toggle fields

DSIZE

Bits 0-4: DSIZE.

FTHLV

Bits 5-8: FTHLV.

UDRCFG

Bits 9-10: UDRCFG.

UDRDET

Bits 11-12: UDRDET.

RXDMAEN

Bit 14: RXDMAEN.

TXDMAEN

Bit 15: TXDMAEN.

CRCSIZE

Bits 16-20: CRCSIZE.

CRCEN

Bit 22: CRCEN.

MBR

Bits 28-30: MBR.

CFG2

The content of this register is write protected when SPI is enabled or IOLOCK bit is set at SPI2S_CR1 register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFCNTR
rw 		SSOM
rw 		SSOE
rw 		SSIOP
rw 		SSM
rw 		CPOL
rw 		CPHA
rw 		LSBFRST
rw 		MASTER
rw 		SP
rw 		COMM
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOSWP
rw 		MIDI
rw 		MSSI
rw
Toggle fields

MSSI

Bits 0-3: MSSI.

MIDI

Bits 4-7: MIDI.

IOSWP

Bit 15: IOSWP.

COMM

Bits 17-18: COMM.

SP

Bits 19-21: SP.

MASTER

Bit 22: MASTER.

LSBFRST

Bit 23: LSBFRST.

CPHA

Bit 24: CPHA.

CPOL

Bit 25: CPOL.

SSM

Bit 26: SSM.

SSIOP

Bit 28: SSIOP.

SSOE

Bit 29: SSOE.

SSOM

Bit 30: SSOM.

AFCNTR

Bit 31: AFCNTR.

SPI2S_IER

SPI/I2S interrupt enable register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSERFIE
rw 		MODFIE
rw 		TIFREIE
rw 		CRCEIE
rw 		OVRIE
rw 		UDRIE
rw 		TXTFIE
rw 		EOTIE
rw 		DXPIE
rw 		TXPIE
rw 		RXPIE
rw
Toggle fields

RXPIE

Bit 0: RXPIE.

TXPIE

Bit 1: TXPIE.

DXPIE

Bit 2: DXPIE.

EOTIE

Bit 3: EOTIE.

TXTFIE

Bit 4: TXTFIE.

UDRIE

Bit 5: UDRIE.

OVRIE

Bit 6: OVRIE.

CRCEIE

Bit 7: CRCEIE.

TIFREIE

Bit 8: TIFREIE.

MODFIE

Bit 9: MODFIE.

TSERFIE

Bit 10: TSERFIE.

SPI2S_SR

SPI/I2S status register

Offset: 0x14, size: 32, reset: 0x00001002, access: read-only

16/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTSIZE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXWNE
r 		RXPLVL
r 		TXC
r 		SUSP
r 		TSERF
r 		MODF
r 		TIFRE
r 		CRCE
r 		OVR
r 		UDR
r 		TXTF
r 		EOT
r 		DXP
r 		TXP
r 		RXP
r
Toggle fields

RXP

Bit 0: RXP.

TXP

Bit 1: TXP.

DXP

Bit 2: DXP.

EOT

Bit 3: EOT.

TXTF

Bit 4: TXTF.

UDR

Bit 5: UDR.

OVR

Bit 6: OVR.

CRCE

Bit 7: CRCE.

TIFRE

Bit 8: TIFRE.

MODF

Bit 9: MODF.

TSERF

Bit 10: TSERF.

SUSP

Bit 11: SUSP.

TXC

Bit 12: TXC.

RXPLVL

Bits 13-14: RXPLVL.

RXWNE

Bit 15: RXWNE.

CTSIZE

Bits 16-31: CTSIZE.

SPI2S_IFCR

SPI/I2S interrupt/status flags clear register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSPC
w 		TSERFC
w 		MODFC
w 		TIFREC
w 		CRCEC
w 		OVRC
w 		UDRC
w 		TXTFC
w 		EOTC
w
Toggle fields

EOTC

Bit 3: EOTC.

TXTFC

Bit 4: TXTFC.

UDRC

Bit 5: UDRC.

OVRC

Bit 6: OVRC.

CRCEC

Bit 7: CRCEC.

TIFREC

Bit 8: TIFREC.

MODFC

Bit 9: MODFC.

TSERFC

Bit 10: TSERFC.

SUSPC

Bit 11: SUSPC.

SPI2S_TXDR

SPI/I2S transmit data register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXDR
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-31: TXDR.

TXDR16

Direct 16-bit access to transmit data register

Offset: 0x20, size: 16, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-15: Transmit data register.

Allowed values: 0x0-0xffff

TXDR8

Direct 8-bit access to transmit data register

Offset: 0x20, size: 8, reset: 0x00000000, access: write-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDR
w
Toggle fields

TXDR

Bits 0-7: Transmit data register.

Allowed values: 0x0-0xff

RXDR16

Direct 16-bit access to receive data register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-15: Receive data register.

RXDR8

Direct 8-bit access to receive data register

Offset: 0x30, size: 8, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-7: Receive data register.

SPI2S_RXDR

SPI/I2S receive data register

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXDR
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDR
r
Toggle fields

RXDR

Bits 0-31: RXDR.

CRCPOLY

SPI polynomial register

Offset: 0x40, size: 32, reset: 0x00000107, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRCPOLY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY
rw
Toggle fields

CRCPOLY

Bits 0-31: CRCPOLY.

TXCRC

SPI transmitter CRC register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC
r
Toggle fields

TXCRC

Bits 0-31: TXCRC.

RXCRC

SPI receiver CRC register

Offset: 0x48, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXCRC
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC
r
Toggle fields

RXCRC

Bits 0-31: RXCRC.

UDRDR

SPI underrun data register

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UDRDR
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRDR
rw
Toggle fields

UDRDR

Bits 0-31: UDRDR.

I2SCFGR

All documented bits in this register must be configured when the I2S is disabled (SPE = 0).These bits are not used in SPI mode except for I2SMOD which needs to be set to 0 in SPI mode.

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/13 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MCKOE
rw 		ODD
rw 		I2SDIV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATFMT
rw 		WSINV
rw 		FIXCH
rw 		CKPOL
rw 		CHLEN
rw 		DATLEN
rw 		PCMSYNC
rw 		I2SSTD
rw 		I2SCFG
rw 		I2SMOD
rw
Toggle fields

I2SMOD

Bit 0: I2SMOD.

I2SCFG

Bits 1-3: I2SCFG.

I2SSTD

Bits 4-5: I2SSTD.

PCMSYNC

Bit 7: PCMSYNC.

DATLEN

Bits 8-9: DATLEN.

CHLEN

Bit 10: CHLEN.

CKPOL

Bit 11: CKPOL.

FIXCH

Bit 12: FIXCH.

WSINV

Bit 13: WSINV.

DATFMT

Bit 14: DATFMT.

I2SDIV

Bits 16-23: I2SDIV.

ODD

Bit 24: ODD.

MCKOE

Bit 25: MCKOE.

I2S_HWCFGR

SPI/I2S hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000000, access: read-only

5/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSCFG
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2SCFG
r 		CRCCFG
r 		RXFCFG
r 		TXFCFG
r
Toggle fields

TXFCFG

Bits 0-3: TXFCFG.

RXFCFG

Bits 4-7: RXFCFG.

CRCCFG

Bits 8-11: CRCCFG.

I2SCFG

Bits 12-15: I2SCFG.

DSCFG

Bits 16-19: DSCFG.

VERR

SPI/I2S version register

Offset: 0x3f4, size: 32, reset: 0x00000011, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SPI/I2S identification register

Offset: 0x3f8, size: 32, reset: 0x00130022, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SPI/I2S size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

STGENC

0x5c008000: STGENC

20/25 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CNTCR
0x4 CNTSR
0x8 CNTCVL
0xc CNTCVU
0x20 CNTFID0
0xfd0 PIDR4
0xfd4 PIDR5
0xfd8 PIDR6
0xfdc PIDR7
0xfe0 PIDR0
0xfe4 PIDR1
0xfe8 PIDR2
0xfec PIDR3
0xff0 CIDR0
0xff4 CIDR1
0xff8 CIDR2
0xffc CIDR3
Toggle registers

CNTCR

STGENC control register

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLTDBG
rw 		EN
rw
Toggle fields

EN

Bit 0: EN.

HLTDBG

Bit 1: HLTDBG.

CNTSR

STGENC status register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HLTDBG
r 		EN
r
Toggle fields

EN

Bit 0: EN.

HLTDBG

Bit 1: HLTDBG.

CNTCVL

the control interface must clear the STGENC_CNTCR.EN bit before writing to this register.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTCVL_L_32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTCVL_L_32
rw
Toggle fields

CNTCVL_L_32

Bits 0-31: CNTCVL_L_32.

CNTCVU

the control interface must clear the STGENC_CNTCR.EN bit before writing to this register.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTCVU_U_32
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTCVU_U_32
rw
Toggle fields

CNTCVU_U_32

Bits 0-31: CNTCVU_U_32.

CNTFID0

the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FREQ
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FREQ
rw
Toggle fields

FREQ

Bits 0-31: FREQ.

PIDR4

STGENC peripheral ID4 register

Offset: 0xfd0, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIZE
r 		DES_2
r
Toggle fields

DES_2

Bits 0-3: DES_2.

SIZE

Bits 4-7: SIZE.

PIDR5

STGENC peripheral ID5 register

Offset: 0xfd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR5
r
Toggle fields

PIDR5

Bits 0-31: PIDR5.

PIDR6

STGENC peripheral ID6 register

Offset: 0xfd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR6
r
Toggle fields

PIDR6

Bits 0-31: PIDR6.

PIDR7

STGENC peripheral ID7 register

Offset: 0xfdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR7
r
Toggle fields

PIDR7

Bits 0-31: PIDR7.

PIDR0

STGENC peripheral ID0 register

Offset: 0xfe0, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PART_0
r
Toggle fields

PART_0

Bits 0-7: PART_0.

PIDR1

STGENC peripheral ID1 register

Offset: 0xfe4, size: 32, reset: 0x000000B1, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DES_0
r 		PART_1
r
Toggle fields

PART_1

Bits 0-3: PART_1.

DES_0

Bits 4-7: DES_0.

PIDR2

STGENC peripheral ID2 register

Offset: 0xfe8, size: 32, reset: 0x0000001B, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVISION
r 		JEDEC
r 		DES_1
r
Toggle fields

DES_1

Bits 0-2: DES_1.

JEDEC

Bit 3: JEDEC.

REVISION

Bits 4-7: REVISION.

PIDR3

STGENC peripheral ID3 register

Offset: 0xfec, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVAND
r 		CMOD
r
Toggle fields

CMOD

Bits 0-3: CMOD.

REVAND

Bits 4-7: REVAND.

CIDR0

STGENC component ID0 register

Offset: 0xff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRMBL_0
r
Toggle fields

PRMBL_0

Bits 0-7: PRMBL_0.

CIDR1

STGENC component ID1 register

Offset: 0xff4, size: 32, reset: 0x000000F0, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLASS
r 		PRMBL_1
r
Toggle fields

PRMBL_1

Bits 0-3: PRMBL_1.

CLASS

Bits 4-7: CLASS.

CIDR2

STGENC component ID2 register

Offset: 0xff8, size: 32, reset: 0x00000050, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRMBL_2
r
Toggle fields

PRMBL_2

Bits 0-7: PRMBL_2.

CIDR3

STGENC component ID3 register

Offset: 0xffc, size: 32, reset: 0x000000B1, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRMBL_3
r
Toggle fields

PRMBL_3

Bits 0-7: PRMBL_3.

STGENR

0x5a005000: STGENR

20/20 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CNTCVL
0x4 CNTCVU
0xfd0 PIDR4
0xfd4 PIDR5
0xfd8 PIDR6
0xfdc PIDR7
0xfe0 PIDR0
0xfe4 PIDR1
0xfe8 PIDR2
0xfec PIDR3
0xff0 CIDR0
0xff4 CIDR1
0xff8 CIDR2
0xffc CIDR3
Toggle registers

CNTCVL

the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.

Offset: 0x0, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTCVL_L_32
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTCVL_L_32
r
Toggle fields

CNTCVL_L_32

Bits 0-31: CNTCVL_L_32.

CNTCVU

the control interface must clear the STGEN_CNTCR.EN bit before writing to this register.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTCVU_U_32
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNTCVU_U_32
r
Toggle fields

CNTCVU_U_32

Bits 0-31: CNTCVU_U_32.

PIDR4

STGENR peripheral ID4 register

Offset: 0xfd0, size: 32, reset: 0x00000004, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIZE
r 		DES_2
r
Toggle fields

DES_2

Bits 0-3: DES_2.

SIZE

Bits 4-7: SIZE.

PIDR5

STGENR peripheral ID5 register

Offset: 0xfd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR5
r
Toggle fields

PIDR5

Bits 0-31: PIDR5.

PIDR6

STGENR peripheral ID6 register

Offset: 0xfd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR6
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR6
r
Toggle fields

PIDR6

Bits 0-31: PIDR6.

PIDR7

STGENR peripheral ID7 register

Offset: 0xfdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PIDR7
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIDR7
r
Toggle fields

PIDR7

Bits 0-31: PIDR7.

PIDR0

STGENR peripheral ID0 register

Offset: 0xfe0, size: 32, reset: 0x00000001, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PART_0
r
Toggle fields

PART_0

Bits 0-7: PART_0.

PIDR1

STGENR peripheral ID1 register

Offset: 0xfe4, size: 32, reset: 0x000000B1, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DES_0
r 		PART_1
r
Toggle fields

PART_1

Bits 0-3: PART_1.

DES_0

Bits 4-7: DES_0.

PIDR2

STGENR peripheral ID2 register

Offset: 0xfe8, size: 32, reset: 0x0000001B, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVISION
r 		JEDEC
r 		DES_1
r
Toggle fields

DES_1

Bits 0-2: DES_1.

JEDEC

Bit 3: JEDEC.

REVISION

Bits 4-7: REVISION.

PIDR3

STGENR peripheral ID3 register

Offset: 0xfec, size: 32, reset: 0x00000000, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REVAND
r 		CMOD
r
Toggle fields

CMOD

Bits 0-3: CMOD.

REVAND

Bits 4-7: REVAND.

CIDR0

STGENR component ID0 register

Offset: 0xff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRMBL_0
r
Toggle fields

PRMBL_0

Bits 0-7: PRMBL_0.

CIDR1

STGENR component ID1 register

Offset: 0xff4, size: 32, reset: 0x000000F0, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLASS
r 		PRMBL_1
r
Toggle fields

PRMBL_1

Bits 0-3: PRMBL_1.

CLASS

Bits 4-7: CLASS.

CIDR2

STGENR component ID2 register

Offset: 0xff8, size: 32, reset: 0x00000050, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRMBL_2
r
Toggle fields

PRMBL_2

Bits 0-7: PRMBL_2.

CIDR3

STGENR component ID3 register

Offset: 0xffc, size: 32, reset: 0x000000B1, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRMBL_3
r
Toggle fields

PRMBL_3

Bits 0-7: PRMBL_3.

SYSCFG

0x50020000: SYSCFG

10/70 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BOOTR
0x4 PMCSETR
0x18 IOCTRLSETR
0x1c ICNR
0x20 CMPCR
0x24 CMPENSETR
0x28 CMPENCLRR
0x2c CBR
0x44 PMCCLRR
0x58 IOCTRLCLRR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

BOOTR

This register is used to know the state of BOOT pins and to control pull-up to reduce the static power consumption on the pin set to high level. )

Offset: 0x0, size: 32, reset: 0x00000000, access: Unspecified

3/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT2_PD
rw 		BOOT1_PD
rw 		BOOT0_PD
rw 		BOOT2
r 		BOOT1
r 		BOOT0
r
Toggle fields

BOOT0

Bit 0: BOOT0.

BOOT1

Bit 1: BOOT1.

BOOT2

Bit 2: BOOT2.

BOOT0_PD

Bit 4: BOOT0_PD.

BOOT1_PD

Bit 5: BOOT1_PD.

BOOT2_PD

Bit 6: BOOT2_PD.

PMCSETR

SYSCFG peripheral mode configuration set register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ANA1_SEL
rw 		ANA0_SEL
rw 		ETH_SEL
rw 		ETH_SELMII
rw 		ETH_REF_CLK_SEL
rw 		ETH_CLK_SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANASWVDD
rw 		EN_BOOSTER
rw 		I2C6_FMP
rw 		I2C5_FMP
rw 		I2C4_FMP
rw 		I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw
Toggle fields

I2C1_FMP

Bit 0: I2C1_FMP.

I2C2_FMP

Bit 1: I2C2_FMP.

I2C3_FMP

Bit 2: I2C3_FMP.

I2C4_FMP

Bit 3: I2C4_FMP.

I2C5_FMP

Bit 4: I2C5_FMP.

I2C6_FMP

Bit 5: I2C6_FMP.

EN_BOOSTER

Bit 8: EN_BOOSTER.

ANASWVDD

Bit 9: ANASWVDD.

ETH_CLK_SEL

Bit 16: ETH_CLK_SEL.

ETH_REF_CLK_SEL

Bit 17: ETH_REF_CLK_SEL.

ETH_SELMII

Bit 20: ETH_SELMII.

ETH_SEL

Bits 21-23: ETH_SEL.

ANA0_SEL

Bit 24: ANA0_SEL.

ANA1_SEL

Bit 25: ANA1_SEL.

IOCTRLSETR

SYSCFG IO control register

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSLVEN_SPI
rw 		HSLVEN_SDMMC
rw 		HSLVEN_ETH
rw 		HSLVEN_QUADSPI
rw 		HSLVEN_TRACE
rw
Toggle fields

HSLVEN_TRACE

Bit 0: HSLVEN_TRACE.

HSLVEN_QUADSPI

Bit 1: HSLVEN_QUADSPI.

HSLVEN_ETH

Bit 2: HSLVEN_ETH.

HSLVEN_SDMMC

Bit 3: HSLVEN_SDMMC.

HSLVEN_SPI

Bit 4: HSLVEN_SPI.

ICNR

SYSCFG interconnect control register

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AXI_M10
rw 		AXI_M9
rw 		AXI_M8
rw 		AXI_M7
rw 		AXI_M6
rw 		AXI_M5
rw 		AXI_M3
rw 		AXI_M2
rw 		AXI_M1
rw 		AXI_M0
rw
Toggle fields

AXI_M0

Bit 0: AXI_M0.

AXI_M1

Bit 1: AXI_M1.

AXI_M2

Bit 2: AXI_M2.

AXI_M3

Bit 3: AXI_M3.

AXI_M5

Bit 5: AXI_M5.

AXI_M6

Bit 6: AXI_M6.

AXI_M7

Bit 7: AXI_M7.

AXI_M8

Bit 8: AXI_M8.

AXI_M9

Bit 9: AXI_M9.

AXI_M10

Bit 10: AXI_M10.

CMPCR

SYSCFG compensation cell control register

Offset: 0x20, size: 32, reset: 0x00870000, access: Unspecified

3/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
APSRC
r 		ANSRC
r 		RAPSRC
rw 		RANSRC
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READY
r 		SW_CTRL
rw
Toggle fields

SW_CTRL

Bit 1: SW_CTRL.

READY

Bit 8: READY.

RANSRC

Bits 16-19: RANSRC.

RAPSRC

Bits 20-23: RAPSRC.

ANSRC

Bits 24-27: ANSRC.

APSRC

Bits 28-31: APSRC.

CMPENSETR

SYSCFG compensation cell enable set register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCU_EN
rw 		MPU_EN
rw
Toggle fields

MPU_EN

Bit 0: MPU_EN.

MCU_EN

Bit 1: MCU_EN.

CMPENCLRR

SYSCFG compensation cell enable set register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MCU_EN
rw 		MPU_EN
rw
Toggle fields

MPU_EN

Bit 0: MPU_EN.

MCU_EN

Bit 1: MCU_EN.

CBR

SYSCFG control timer break register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVDL
rw 		CLL
rw
Toggle fields

CLL

Bit 0: CLL.

PVDL

Bit 2: PVDL.

PMCCLRR

SYSCFG peripheral mode configuration clear register

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/14 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ANA1_SEL
rw 		ANA0_SEL
rw 		ETH_SEL
rw 		ETH_SELMII
rw 		ETH_REF_CLK_SEL
rw 		ETH_CLK_SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANASWVDD
rw 		EN_BOOSTER
rw 		I2C6_FMP
rw 		I2C5_FMP
rw 		I2C4_FMP
rw 		I2C3_FMP
rw 		I2C2_FMP
rw 		I2C1_FMP
rw
Toggle fields

I2C1_FMP

Bit 0: I2C1_FMP.

I2C2_FMP

Bit 1: I2C2_FMP.

I2C3_FMP

Bit 2: I2C3_FMP.

I2C4_FMP

Bit 3: I2C4_FMP.

I2C5_FMP

Bit 4: I2C5_FMP.

I2C6_FMP

Bit 5: I2C6_FMP.

EN_BOOSTER

Bit 8: EN_BOOSTER.

ANASWVDD

Bit 9: ANASWVDD.

ETH_CLK_SEL

Bit 16: ETH_CLK_SEL.

ETH_REF_CLK_SEL

Bit 17: ETH_REF_CLK_SEL.

ETH_SELMII

Bit 20: ETH_SELMII.

ETH_SEL

Bits 21-23: ETH_SEL.

ANA0_SEL

Bit 24: ANA0_SEL.

ANA1_SEL

Bit 25: ANA1_SEL.

IOCTRLCLRR

SYSCFG IO control register

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSLVEN_SPI
rw 		HSLVEN_SDMMC
rw 		HSLVEN_ETH
rw 		HSLVEN_QUADSPI
rw 		HSLVEN_TRACE
rw
Toggle fields

HSLVEN_TRACE

Bit 0: HSLVEN_TRACE.

HSLVEN_QUADSPI

Bit 1: HSLVEN_QUADSPI.

HSLVEN_ETH

Bit 2: HSLVEN_ETH.

HSLVEN_SDMMC

Bit 3: HSLVEN_SDMMC.

HSLVEN_SPI

Bit 4: HSLVEN_SPI.

VERR

SYSCFG version register

Offset: 0x3f4, size: 32, reset: 0x00000020, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

SYSCFG identification register

Offset: 0x3f8, size: 32, reset: 0x00030001, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

SYSCFG size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

TAMP

0x5c00a000: TAMP

41/128 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0xc FLTCR
0x10 ATCR1
0x14 ATSEEDR
0x18 ATOR
0x20 SMCR
0x2c IER
0x30 SR
0x34 MISR
0x38 SMISR
0x3c SCR
0x40 COUNTR
0x50 CFGR
0x100 BKP[0]R
0x104 BKP[1]R
0x108 BKP[2]R
0x10c BKP[3]R
0x110 BKP[4]R
0x114 BKP[5]R
0x118 BKP[6]R
0x11c BKP[7]R
0x120 BKP[8]R
0x124 BKP[9]R
0x128 BKP[10]R
0x12c BKP[11]R
0x130 BKP[12]R
0x134 BKP[13]R
0x138 BKP[14]R
0x13c BKP[15]R
0x140 BKP[16]R
0x144 BKP[17]R
0x148 BKP[18]R
0x14c BKP[19]R
0x150 BKP[20]R
0x154 BKP[21]R
0x158 BKP[22]R
0x15c BKP[23]R
0x160 BKP[24]R
0x164 BKP[25]R
0x168 BKP[26]R
0x16c BKP[27]R
0x170 BKP[28]R
0x174 BKP[29]R
0x178 BKP[30]R
0x17c BKP[31]R
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x0, size: 32, reset: 0xFFFF0000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8E
rw 		ITAMP5E
rw 		ITAMP4E
rw 		ITAMP3E
rw 		ITAMP2E
rw 		ITAMP1E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3E
rw 		TAMP2E
rw 		TAMP1E
rw
Toggle fields

TAMP1E

Bit 0: TAMP1E.

TAMP2E

Bit 1: TAMP2E.

TAMP3E

Bit 2: TAMP3E.

ITAMP1E

Bit 16: ITAMP1E.

ITAMP2E

Bit 17: ITAMP2E.

ITAMP3E

Bit 18: ITAMP3E.

ITAMP4E

Bit 19: ITAMP4E.

ITAMP5E

Bit 20: ITAMP5E.

ITAMP8E

Bit 23: ITAMP8E.

CR2

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3TRG
rw 		TAMP2TRG
rw 		TAMP1TRG
rw 		TAMP3MSK
rw 		TAMP2MSK
rw 		TAMP1MSK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3NOER
rw 		TAMP2NOER
rw 		TAMP1NOER
rw
Toggle fields

TAMP1NOER

Bit 0: TAMP1NOER.

TAMP2NOER

Bit 1: TAMP2NOER.

TAMP3NOER

Bit 2: TAMP3NOER.

TAMP1MSK

Bit 16: TAMP1MSK.

TAMP2MSK

Bit 17: TAMP2MSK.

TAMP3MSK

Bit 18: TAMP3MSK.

TAMP1TRG

Bit 24: TAMP1TRG.

TAMP2TRG

Bit 25: TAMP2TRG.

TAMP3TRG

Bit 26: TAMP3TRG.

FLTCR

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMPPUDIS
rw 		TAMPPRCH
rw 		TAMPFLT
rw 		TAMPFREQ
rw
Toggle fields

TAMPFREQ

Bits 0-2: TAMPFREQ.

TAMPFLT

Bits 3-4: TAMPFLT.

TAMPPRCH

Bits 5-6: TAMPPRCH.

TAMPPUDIS

Bit 7: TAMPPUDIS.

ATCR1

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x10, size: 32, reset: 0x00070000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLTEN
rw 		ATOSHARE
rw 		ATPER
rw 		ATCKSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATOSEL3
rw 		ATOSEL2
rw 		ATOSEL1
rw 		TAMP3AM
rw 		TAMP2AM
rw 		TAMP1AM
rw
Toggle fields

TAMP1AM

Bit 0: TAMP1AM.

TAMP2AM

Bit 1: TAMP2AM.

TAMP3AM

Bit 2: TAMP3AM.

ATOSEL1

Bits 8-9: ATOSEL1.

ATOSEL2

Bits 10-11: ATOSEL2.

ATOSEL3

Bits 12-13: ATOSEL3.

ATCKSEL

Bits 16-18: ATCKSEL.

ATPER

Bits 24-26: ATPER.

ATOSHARE

Bit 30: ATOSHARE.

FLTEN

Bit 31: FLTEN.

ATSEEDR

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEED
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEED
w
Toggle fields

SEED

Bits 0-31: SEED.

ATOR

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x18, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INITS
r 		SEEDF
r 		PRNG
r
Toggle fields

PRNG

Bits 0-7: PRNG.

SEEDF

Bit 14: SEEDF.

INITS

Bit 15: INITS.

SMCR

This register can be written only when the APB access is secure.

Offset: 0x20, size: 32, reset: 0x80000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMPDPROT
rw 		BKPWDPROT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKPRWDPROT
rw
Toggle fields

BKPRWDPROT

Bits 0-7: BKPRWDPROT.

BKPWDPROT

Bits 16-23: BKPWDPROT.

TAMPDPROT

Bit 31: TAMPDPROT.

IER

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8IE
rw 		ITAMP5IE
rw 		ITAMP4IE
rw 		ITAMP3IE
rw 		ITAMP2IE
rw 		ITAMP1IE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3IE
rw 		TAMP2IE
rw 		TAMP1IE
rw
Toggle fields

TAMP1IE

Bit 0: TAMP1IE.

TAMP2IE

Bit 1: TAMP2IE.

TAMP3IE

Bit 2: TAMP3IE.

ITAMP1IE

Bit 16: ITAMP1IE.

ITAMP2IE

Bit 17: ITAMP2IE.

ITAMP3IE

Bit 18: ITAMP3IE.

ITAMP4IE

Bit 19: ITAMP4IE.

ITAMP5IE

Bit 20: ITAMP5IE.

ITAMP8IE

Bit 23: ITAMP8IE.

SR

This register can be protected against non-secure access. Refer to Section51.3.3: TAMP secure protection modes.

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8F
r 		ITAMP5F
r 		ITAMP4F
r 		ITAMP3F
r 		ITAMP2F
r 		ITAMP1F
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3F
r 		TAMP2F
r 		TAMP1F
r
Toggle fields

TAMP1F

Bit 0: TAMP1F.

TAMP2F

Bit 1: TAMP2F.

TAMP3F

Bit 2: TAMP3F.

ITAMP1F

Bit 16: ITAMP1F.

ITAMP2F

Bit 17: ITAMP2F.

ITAMP3F

Bit 18: ITAMP3F.

ITAMP4F

Bit 19: ITAMP4F.

ITAMP5F

Bit 20: ITAMP5F.

ITAMP8F

Bit 23: ITAMP8F.

MISR

TAMP non-secure masked interrupt status register

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP5MF
r 		ITAMP4MF
r 		ITAMP3MF
r 		ITAMP2MF
r 		ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP4MF

Bit 19: ITAMP4MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SMISR

TAMP secure masked interrupt status register

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

9/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ITAMP8MF
r 		ITAMP5MF
r 		ITAMP4MF
r 		ITAMP3MF
r 		ITAMP2MF
r 		ITAMP1MF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP3MF
r 		TAMP2MF
r 		TAMP1MF
r
Toggle fields

TAMP1MF

Bit 0: TAMP1MF.

TAMP2MF

Bit 1: TAMP2MF.

TAMP3MF

Bit 2: TAMP3MF.

ITAMP1MF

Bit 16: ITAMP1MF.

ITAMP2MF

Bit 17: ITAMP2MF.

ITAMP3MF

Bit 18: ITAMP3MF.

ITAMP4MF

Bit 19: ITAMP4MF.

ITAMP5MF

Bit 20: ITAMP5MF.

ITAMP8MF

Bit 23: ITAMP8MF.

SCR

TAMP status clear register

Offset: 0x3c, size: 32, reset: 0x00000000, access: write-only

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CITAMP8F
w 		CITAMP5F
w 		CITAMP4F
w 		CITAMP3F
w 		CITAMP2F
w 		CITAMP1F
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTAMP3F
w 		CTAMP2F
w 		CTAMP1F
w
Toggle fields

CTAMP1F

Bit 0: CTAMP1F.

CTAMP2F

Bit 1: CTAMP2F.

CTAMP3F

Bit 2: CTAMP3F.

CITAMP1F

Bit 16: CITAMP1F.

CITAMP2F

Bit 17: CITAMP2F.

CITAMP3F

Bit 18: CITAMP3F.

CITAMP4F

Bit 19: CITAMP4F.

CITAMP5F

Bit 20: CITAMP5F.

CITAMP8F

Bit 23: CITAMP8F.

COUNTR

TAMP monotonic counter register

Offset: 0x40, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COUNT
r
Toggle fields

COUNT

Bits 0-31: COUNT.

CFGR

TAMP configuration register

Offset: 0x50, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUT3_RMP
rw
Toggle fields

OUT3_RMP

Bit 0: OUT3_RMP.

BKP[0]R

TAMP backup 0 register

Offset: 0x100, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[1]R

TAMP backup 1 register

Offset: 0x104, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[2]R

TAMP backup 2 register

Offset: 0x108, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[3]R

TAMP backup 3 register

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[4]R

TAMP backup 4 register

Offset: 0x110, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[5]R

TAMP backup 5 register

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[6]R

TAMP backup 6 register

Offset: 0x118, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[7]R

TAMP backup 7 register

Offset: 0x11c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[8]R

TAMP backup 8 register

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[9]R

TAMP backup 9 register

Offset: 0x124, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[10]R

TAMP backup 10 register

Offset: 0x128, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[11]R

TAMP backup 11 register

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[12]R

TAMP backup 12 register

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[13]R

TAMP backup 13 register

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[14]R

TAMP backup 14 register

Offset: 0x138, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[15]R

TAMP backup 15 register

Offset: 0x13c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[16]R

TAMP backup 16 register

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[17]R

TAMP backup 17 register

Offset: 0x144, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[18]R

TAMP backup 18 register

Offset: 0x148, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[19]R

TAMP backup 19 register

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[20]R

TAMP backup 20 register

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[21]R

TAMP backup 21 register

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[22]R

TAMP backup 22 register

Offset: 0x158, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[23]R

TAMP backup 23 register

Offset: 0x15c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[24]R

TAMP backup 24 register

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[25]R

TAMP backup 25 register

Offset: 0x164, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[26]R

TAMP backup 26 register

Offset: 0x168, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[27]R

TAMP backup 27 register

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[28]R

TAMP backup 28 register

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[29]R

TAMP backup 29 register

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[30]R

TAMP backup 30 register

Offset: 0x178, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

BKP[31]R

TAMP backup 31 register

Offset: 0x17c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP
rw
Toggle fields

BKP

Bits 0-31: BKP.

HWCFGR2

TAMP hardware configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000101, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRUST_ZONE
r 		OPTIONREG_OUT
r
Toggle fields

OPTIONREG_OUT

Bits 0-7: OPTIONREG_OUT.

TRUST_ZONE

Bits 8-11: TRUST_ZONE.

HWCFGR1

TAMP hardware configuration register 1

Offset: 0x3f0, size: 32, reset: 0x009D1320, access: read-only

4/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INT_TAMPER
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE_TAMPER
r 		TAMPER
r 		BACKUP_REGS
r
Toggle fields

BACKUP_REGS

Bits 0-7: BACKUP_REGS.

TAMPER

Bits 8-11: TAMPER.

ACTIVE_TAMPER

Bits 12-15: ACTIVE_TAMPER.

INT_TAMPER

Bits 16-31: INT_TAMPER.

VERR

TAMP version register

Offset: 0x3f4, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

TAMP identification register

Offset: 0x3f8, size: 32, reset: 0x00121033, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

TAMP size identification register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.

TIM1

0x44000000: TIM1

1/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE1
0x1c CCMR2ALTERNATE17
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
0x60 AF1
0x64 AF2
0x68 TISEL
Toggle registers

CR1

TIM1 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM1 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM1 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM1 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM1 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM1 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE1

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE17

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM1 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM1 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM1 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM1 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM1 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM1 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM1 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM1 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM1 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM1 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM1 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM1 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM1 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

AF1

TIM1 alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKINP
rw 		BKDF1BK0E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BKINE.

BKDF1BK0E

Bit 8: BKDF1BK0E.

BKINP

Bit 9: BKINP.

ETRSEL

Bits 14-17: ETRSEL.

AF2

TIM1 Alternate function register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2INP
rw 		BK2DF1BK1E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BK2INE.

BK2DF1BK1E

Bit 8: BK2DF1BK1E.

BK2INP

Bit 9: BK2INP.

TISEL

TIM1 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw 		TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TI3SEL

Bits 16-19: TI3SEL.

TI4SEL

Bits 24-27: TI4SEL.

TIM12

0x40006000: TIM12

1/59 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) _CR1
0x4 _CR2
0x8 _SMCR
0xc (16-bit) _DIER
0x10 _SR
0x14 (16-bit) _EGR
0x18 _CCMR1_input
0x18 _CCMR1_output
0x20 _CCER
0x24 _CNT
0x28 (16-bit) _PSC
0x2c (16-bit) _ARR
0x34 (16-bit) _CCR1
0x38 (16-bit) _CCR2
0x68 _TISEL
Toggle registers

_CR1

TIM12 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

_CR2

TIM12 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1S
rw 		MMS
rw
Toggle fields

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

_SMCR

TIM12 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_4
rw 		TS_3
rw 		SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

SMS_3

Bit 16: SMS_3.

TS_3

Bit 20: TS_3.

TS_4

Bit 21: TS_4.

_DIER

TIM12 interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

TIE

Bit 6: TIE.

_SR

TIM12 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		TIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

TIF

Bit 6: TIF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

_EGR

TIM12 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TG
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

TG

Bit 6: TG.

_CCMR1_input

TIM12 capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

_CCMR1_output

TIM12 capture/compare mode register 1

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1FE.

OC1M

Bits 4-6: OC1M.

CC2S

Bits 8-9: CC2S.

OC2FE

Bit 10: OC2FE.

OC2PE

Bit 11: OC2PE.

OC2M

Bits 12-14: OC2M.

OC1M_3

Bit 16: OC1M_3.

OC2M_3

Bit 24: OC2M_3.

_CCER

TIM12 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NP

Bit 7: CC2NP.

_CNT

TIM12 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

_PSC

TIM12 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

_ARR

TIM12 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

_CCR1

TIM12 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

_CCR2

TIM12 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

_TISEL

TIM12 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TIM13

0x40007000: TIM13

0/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) _CR1
0xc (16-bit) _DIER
0x10 (16-bit) _SR
0x14 (16-bit) _EGR
0x18 _CCMR1
0x20 (16-bit) _CCER
0x24 _CNT
0x28 (16-bit) _PSC
0x2c (16-bit) _ARR
0x34 (16-bit) _CCR1
0x68 (16-bit) _TISEL
Toggle registers

_CR1

TIM13 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

_DIER

TIM13 Interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

_SR

TIM13 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC1OF

Bit 9: CC1OF.

_EGR

TIM13 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

_CCMR1

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

OC1M3

Bit 16: OC1M3.

_CCER

TIM13 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NP

Bit 3: CC1NP.

_CNT

TIM13 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

_PSC

TIM13 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

_ARR

TIM13 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

_CCR1

TIM13 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

_TISEL

TIM13 timer input selection register

Offset: 0x68, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TIM14

0x40008000: TIM14

0/28 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) _CR1
0xc (16-bit) _DIER
0x10 (16-bit) _SR
0x14 (16-bit) _EGR
0x18 _CCMR1
0x20 (16-bit) _CCER
0x24 _CNT
0x28 (16-bit) _PSC
0x2c (16-bit) _ARR
0x34 (16-bit) _CCR1
0x68 (16-bit) _TISEL
Toggle registers

_CR1

TIM14 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

_DIER

TIM14 Interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

_SR

TIM14 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC1OF

Bit 9: CC1OF.

_EGR

TIM14 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

_CCMR1

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So one must take care that the same bit can have a different meaning for the input stage and for the output stage. Output compare mode

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC1M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

OC1FE

Bit 2: OC1FE.

OC1PE

Bit 3: OC1PE.

OC1M

Bits 4-6: OC1M.

OC1M3

Bit 16: OC1M3.

_CCER

TIM14 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NP

Bit 3: CC1NP.

_CNT

TIM14 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

_PSC

TIM14 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

_ARR

TIM14 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

_CCR1

TIM14 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

_TISEL

TIM14 timer input selection register

Offset: 0x68, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TIM15

0x44006000: TIM15

1/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) _CR1
0x4 (16-bit) _CR2
0x8 SMCR
0xc (16-bit) _DIER
0x10 (16-bit) _SR
0x14 EGR
0x18 CCMR1_Input
0x18 CCMR1_Output
0x20 (16-bit) _CCER
0x24 _CNT
0x28 (16-bit) _PSC
0x2c (16-bit) _ARR
0x30 (16-bit) _RCR
0x34 (16-bit) _CCR1
0x38 (16-bit) _CCR2
0x44 BDTR
0x48 (16-bit) _DCR
0x4c (16-bit) _DMAR
0x60 _AF1
0x68 _TISEL
Toggle registers

_CR1

TIM15 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

_CR2

TIM15 control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

SMCR

slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/5 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS_4_3
rw 		SMS_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: Slave mode selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

SMS_3

Bit 16: Slave mode selection - bit 3.

TS_4_3

Bits 20-21: Trigger selection.

_DIER

TIM15 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/11 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

_SR

TIM15 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/8 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2OF
rw 		CC1OF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG
w 		TG
w 		COMG
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

COMG

Bit 5: COMG.

TG

Bit 6: Trigger generation.

BG

Bit 7: BG.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/12 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC2M_3
rw 		OC1M_3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE
rw 		OC2M
rw 		OC2PE
rw 		OC2FE
rw 		CC2S
rw 		OC1CE
rw 		OC1M
rw 		OC1PE
rw 		OC1FE
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output compare 1 fast enable.

OC1PE

Bit 3: Output compare 1 preload enable.

OC1M

Bits 4-6: Output compare 1 mode.

OC1CE

Bit 7: Output compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output compare 2 fast enable.

OC2PE

Bit 11: Output compare 2 preload enable.

OC2M

Bits 12-14: Output compare 2 mode.

OC2CE

Bit 15: Output compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

_CCER

TIM15 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC2NP
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NP

Bit 7: CC2NP.

_CNT

TIM15 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

_PSC

TIM15 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

_ARR

TIM15 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

_RCR

TIM15 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: REP.

_CCR1

TIM15 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

_CCR2

TIM15 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BKDSRM

Bit 26: BKDSRM.

BKBID

Bit 28: BKBID.

_DCR

TIM15 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

_DMAR

TIM15 DMA address for full transfer

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMAB.

_AF1

TIM15 alternate register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKINP
rw 		BKDF1BK0E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BKINE.

BKDF1BK0E

Bit 8: BKDF1BK0E.

BKINP

Bit 9: BKINP.

_TISEL

TIM15 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TIM16

0x44007000: TIM16

1/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0xc (16-bit) DIER
0x10 (16-bit) SR
0x14 EGR
0x20 (16-bit) CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x44 BDTR
0x48 (16-bit) DCR
0x4c (16-bit) DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

TIM16/TIM17 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM16/TIM17 control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

DIER

TIM16/TIM17 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

COMIE

Bit 5: COMIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

COMDE

Bit 13: COMDE.

SR

TIM16/TIM17 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

COMIF

Bit 5: COMIF.

BIF

Bit 7: BIF.

CC1OF

Bit 9: CC1OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CCER

TIM16/TIM17 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CNT

TIM16/TIM17 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM16/TIM17 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM16/TIM17 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM16/TIM17 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: REP.

CCR1

TIM16/TIM17 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

BDTR

As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BKDSRM

Bit 26: BKDSRM.

BKBID

Bit 28: BKBID.

DCR

TIM16/TIM17 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM16/TIM17 DMA address for full transfer

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMAB.

AF1

TIM17 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKINP
rw 		BKDF1BK2E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BKINE.

BKDF1BK2E

Bit 8: BKDF1BK2E.

BKINP

Bit 9: BKINP.

TISEL

TIM17 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TIM17

0x44008000: TIM16

1/53 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 (16-bit) CR2
0xc (16-bit) DIER
0x10 (16-bit) SR
0x14 EGR
0x20 (16-bit) CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x44 BDTR
0x48 (16-bit) DCR
0x4c (16-bit) DMAR
0x60 AF1
0x68 TISEL
Toggle registers

CR1

TIM16/TIM17 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM16/TIM17 control register 2

Offset: 0x4, size: 16, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS1N
rw 		OIS1
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

DIER

TIM16/TIM17 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/7 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMDE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		COMIE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

COMIE

Bit 5: COMIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

COMDE

Bit 13: COMDE.

SR

TIM16/TIM17 status register

Offset: 0x10, size: 16, reset: 0x00000000, access: read-write

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1OF
rw 		BIF
rw 		COMIF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

COMIF

Bit 5: COMIF.

BIF

Bit 7: BIF.

CC1OF

Bit 9: CC1OF.

EGR

event generation register

Offset: 0x14, size: 32, reset: 0x00000000, access: write-only

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UG
w
Toggle fields

UG

Bit 0: Update generation.

CCER

TIM16/TIM17 capture/compare enable register

Offset: 0x20, size: 16, reset: 0x00000000, access: read-write

0/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CNT

TIM16/TIM17 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM16/TIM17 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM16/TIM17 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM16/TIM17 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-7: REP.

CCR1

TIM16/TIM17 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

BDTR

As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/11 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKBID
rw 		BKDSRM
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BKDSRM

Bit 26: BKDSRM.

BKBID

Bit 28: BKBID.

DCR

TIM16/TIM17 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM16/TIM17 DMA address for full transfer

Offset: 0x4c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-15: DMAB.

AF1

TIM17 alternate function register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKINP
rw 		BKDF1BK2E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BKINE.

BKDF1BK2E

Bit 8: BKDF1BK2E.

BKINP

Bit 9: BKINP.

TISEL

TIM17 input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TIM2

0x40000000: TIM2

1/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE2
0x1c CCMR2ALTERNATE18
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
Toggle registers

CR1

TIM2 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM2 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM2 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM2 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM2 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM2 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE2

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE18

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM2 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM2 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM2 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM2 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM2 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM2 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM2 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM2 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM2 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM2 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM2 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM2 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM2 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

TIM3

0x40001000: TIM3

1/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE3
0x1c CCMR2ALTERNATE19
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
Toggle registers

CR1

TIM3 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM3 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM3 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM3 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM3 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM3 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE3

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE19

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM3 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM3 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM3 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM3 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM3 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM3 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM3 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM3 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM3 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM3 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM3 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM3 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM3 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

TIM4

0x40002000: TIM4

1/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE4
0x1c CCMR2ALTERNATE20
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
Toggle registers

CR1

TIM4 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM4 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM4 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM4 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM4 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM4 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE4

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE20

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM4 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM4 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM4 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM4 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM4 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM4 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM4 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM4 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM4 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM4 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM4 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM4 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM4 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

TIM5

0x40003000: TIM5

1/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE5
0x1c CCMR2ALTERNATE21
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
Toggle registers

CR1

TIM5 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM5 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM5 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM5 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM5 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM5 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE5

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE21

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM5 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM5 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM5 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM5 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM5 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM5 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM5 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM5 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM5 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM5 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM5 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM5 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM5 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

TIM6

0x40004000: TIM6

1/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE6
0x1c CCMR2ALTERNATE22
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
Toggle registers

CR1

TIM6 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM6 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM6 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM6 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM6 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM6 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE6

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE22

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM6 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM6 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM6 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM6 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM6 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM6 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM6 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM6 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM6 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM6 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM6 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM6 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM6 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

TIM7

0x40005000: TIM7

1/148 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE7
0x1c CCMR2ALTERNATE23
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
Toggle registers

CR1

TIM7 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM7 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM7 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM7 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM7 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM7 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE7

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE23

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM7 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM7 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM7 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM7 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM7 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM7 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM7 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM7 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM7 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM7 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM7 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM7 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM7 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

TIM8

0x44001000: TIM8

1/159 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR1
0x4 CR2
0x8 SMCR
0xc (16-bit) DIER
0x10 SR
0x14 (16-bit) EGR
0x18 CCMR1ALTERNATE8
0x1c CCMR2ALTERNATE24
0x20 CCER
0x24 CNT
0x28 (16-bit) PSC
0x2c (16-bit) ARR
0x30 (16-bit) RCR
0x34 (16-bit) CCR1
0x38 (16-bit) CCR2
0x3c (16-bit) CCR3
0x40 (16-bit) CCR4
0x44 BDTR
0x48 (16-bit) DCR
0x4c DMAR
0x54 CCMR3
0x58 CCR5
0x5c (16-bit) CCR6
0x60 AF1
0x64 AF2
0x68 TISEL
Toggle registers

CR1

TIM8 control register 1

Offset: 0x0, size: 16, reset: 0x00000000, access: read-write

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UIFREMAP
rw 		CKD
rw 		ARPE
rw 		CMS
rw 		DIR
rw 		OPM
rw 		URS
rw 		UDIS
rw 		CEN
rw
Toggle fields

CEN

Bit 0: CEN.

UDIS

Bit 1: UDIS.

URS

Bit 2: URS.

OPM

Bit 3: OPM.

DIR

Bit 4: DIR.

CMS

Bits 5-6: CMS.

ARPE

Bit 7: ARPE.

CKD

Bits 8-9: CKD.

UIFREMAP

Bit 11: UIFREMAP.

CR2

TIM8 control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MMS2
rw 		OIS6
rw 		OIS5
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OIS4
rw 		OIS3N
rw 		OIS3
rw 		OIS2N
rw 		OIS2
rw 		OIS1N
rw 		OIS1
rw 		TI1S
rw 		MMS
rw 		CCDS
rw 		CCUS
rw 		CCPC
rw
Toggle fields

CCPC

Bit 0: CCPC.

CCUS

Bit 2: CCUS.

CCDS

Bit 3: CCDS.

MMS

Bits 4-6: MMS.

TI1S

Bit 7: TI1S.

OIS1

Bit 8: OIS1.

OIS1N

Bit 9: OIS1N.

OIS2

Bit 10: OIS2.

OIS2N

Bit 11: OIS2N.

OIS3

Bit 12: OIS3.

OIS3N

Bit 13: OIS3N.

OIS4

Bit 14: OIS4.

OIS5

Bit 16: OIS5.

OIS6

Bit 18: OIS6.

MMS2

Bits 20-23: MMS2.

SMCR

TIM8 slave mode control register

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS4
rw 		TS3
rw 		SMS3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP
rw 		ECE
rw 		ETPS
rw 		ETF
rw 		MSM
rw 		TS
rw 		SMS
rw
Toggle fields

SMS

Bits 0-2: SMS.

TS

Bits 4-6: TS.

MSM

Bit 7: MSM.

ETF

Bits 8-11: ETF.

ETPS

Bits 12-13: ETPS.

ECE

Bit 14: ECE.

ETP

Bit 15: ETP.

SMS3

Bit 16: SMS3.

TS3

Bit 20: TS3.

TS4

Bit 21: TS4.

DIER

TIM8 DMA/interrupt enable register

Offset: 0xc, size: 16, reset: 0x00000000, access: read-write

0/15 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDE
rw 		COMDE
rw 		CC4DE
rw 		CC3DE
rw 		CC2DE
rw 		CC1DE
rw 		UDE
rw 		BIE
rw 		TIE
rw 		COMIE
rw 		CC4IE
rw 		CC3IE
rw 		CC2IE
rw 		CC1IE
rw 		UIE
rw
Toggle fields

UIE

Bit 0: UIE.

CC1IE

Bit 1: CC1IE.

CC2IE

Bit 2: CC2IE.

CC3IE

Bit 3: CC3IE.

CC4IE

Bit 4: CC4IE.

COMIE

Bit 5: COMIE.

TIE

Bit 6: TIE.

BIE

Bit 7: BIE.

UDE

Bit 8: UDE.

CC1DE

Bit 9: CC1DE.

CC2DE

Bit 10: CC2DE.

CC3DE

Bit 11: CC3DE.

CC4DE

Bit 12: CC4DE.

COMDE

Bit 13: COMDE.

TDE

Bit 14: TDE.

SR

TIM8 status register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6IF
rw 		CC5IF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBIF
rw 		CC4OF
rw 		CC3OF
rw 		CC2OF
rw 		CC1OF
rw 		B2IF
rw 		BIF
rw 		TIF
rw 		COMIF
rw 		CC4IF
rw 		CC3IF
rw 		CC2IF
rw 		CC1IF
rw 		UIF
rw
Toggle fields

UIF

Bit 0: UIF.

CC1IF

Bit 1: CC1IF.

CC2IF

Bit 2: CC2IF.

CC3IF

Bit 3: CC3IF.

CC4IF

Bit 4: CC4IF.

COMIF

Bit 5: COMIF.

TIF

Bit 6: TIF.

BIF

Bit 7: BIF.

B2IF

Bit 8: B2IF.

CC1OF

Bit 9: CC1OF.

CC2OF

Bit 10: CC2OF.

CC3OF

Bit 11: CC3OF.

CC4OF

Bit 12: CC4OF.

SBIF

Bit 13: SBIF.

CC5IF

Bit 16: CC5IF.

CC6IF

Bit 17: CC6IF.

EGR

TIM8 event generation register

Offset: 0x14, size: 16, reset: 0x00000000, access: write-only

0/9 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B2G
w 		BG
w 		TG
w 		COMG
w 		CC4G
w 		CC3G
w 		CC2G
w 		CC1G
w 		UG
w
Toggle fields

UG

Bit 0: UG.

CC1G

Bit 1: CC1G.

CC2G

Bit 2: CC2G.

CC3G

Bit 3: CC3G.

CC4G

Bit 4: CC4G.

COMG

Bit 5: COMG.

TG

Bit 6: TG.

BG

Bit 7: BG.

B2G

Bit 8: B2G.

CCMR1ALTERNATE8

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x18, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC2F
rw 		IC2PSC
rw 		CC2S
rw 		IC1F
rw 		IC1PSC
rw 		CC1S
rw
Toggle fields

CC1S

Bits 0-1: CC1S.

IC1PSC

Bits 2-3: IC1PSC.

IC1F

Bits 4-7: IC1F.

CC2S

Bits 8-9: CC2S.

IC2PSC

Bits 10-11: IC2PSC.

IC2F

Bits 12-15: IC2F.

CCMR2ALTERNATE24

The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Input capture mode:

Offset: 0x1c, size: 32, reset: 0x00000000, access: read-write

0/6 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IC4F
rw 		IC4PSC
rw 		CC4S
rw 		IC3F
rw 		IC3PSC
rw 		CC3S
rw
Toggle fields

CC3S

Bits 0-1: CC3S.

IC3PSC

Bits 2-3: IC3PSC.

IC3F

Bits 4-7: IC3F.

CC4S

Bits 8-9: CC4S.

IC4PSC

Bits 10-11: IC4PSC.

IC4F

Bits 12-15: IC4F.

CCER

TIM8 capture/compare enable register

Offset: 0x20, size: 32, reset: 0x00000000, access: read-write

0/19 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CC6P
rw 		CC6E
rw 		CC5P
rw 		CC5E
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP
rw 		CC4P
rw 		CC4E
rw 		CC3NP
rw 		CC3NE
rw 		CC3P
rw 		CC3E
rw 		CC2NP
rw 		CC2NE
rw 		CC2P
rw 		CC2E
rw 		CC1NP
rw 		CC1NE
rw 		CC1P
rw 		CC1E
rw
Toggle fields

CC1E

Bit 0: CC1E.

CC1P

Bit 1: CC1P.

CC1NE

Bit 2: CC1NE.

CC1NP

Bit 3: CC1NP.

CC2E

Bit 4: CC2E.

CC2P

Bit 5: CC2P.

CC2NE

Bit 6: CC2NE.

CC2NP

Bit 7: CC2NP.

CC3E

Bit 8: CC3E.

CC3P

Bit 9: CC3P.

CC3NE

Bit 10: CC3NE.

CC3NP

Bit 11: CC3NP.

CC4E

Bit 12: CC4E.

CC4P

Bit 13: CC4P.

CC4NP

Bit 15: CC4NP.

CC5E

Bit 16: CC5E.

CC5P

Bit 17: CC5P.

CC6E

Bit 20: CC6E.

CC6P

Bit 21: CC6P.

CNT

TIM8 counter

Offset: 0x24, size: 32, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIFCPY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT
rw
Toggle fields

CNT

Bits 0-15: CNT.

UIFCPY

Bit 31: UIFCPY.

PSC

TIM8 prescaler

Offset: 0x28, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC
rw
Toggle fields

PSC

Bits 0-15: PSC.

ARR

TIM8 auto-reload register

Offset: 0x2c, size: 16, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR
rw
Toggle fields

ARR

Bits 0-15: ARR.

RCR

TIM8 repetition counter register

Offset: 0x30, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REP
rw
Toggle fields

REP

Bits 0-15: REP.

CCR1

TIM8 capture/compare register 1

Offset: 0x34, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1
rw
Toggle fields

CCR1

Bits 0-15: CCR1.

CCR2

TIM8 capture/compare register 2

Offset: 0x38, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2
rw
Toggle fields

CCR2

Bits 0-15: CCR2.

CCR3

TIM8 capture/compare register 3

Offset: 0x3c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3
rw
Toggle fields

CCR3

Bits 0-15: CCR3.

CCR4

TIM8 capture/compare register 4

Offset: 0x40, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4
rw
Toggle fields

CCR4

Bits 0-15: CCR4.

BDTR

As the bits BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Offset: 0x44, size: 32, reset: 0x00000000, access: read-write

0/16 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BK2BID
rw 		BKBID
rw 		BK2DSRM
rw 		BKDSRM
rw 		BK2P
rw 		BK2E
rw 		BK2F
rw 		BKF
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MOE
rw 		AOE
rw 		BKP
rw 		BKE
rw 		OSSR
rw 		OSSI
rw 		LOCK
rw 		DTG
rw
Toggle fields

DTG

Bits 0-7: DTG.

LOCK

Bits 8-9: LOCK.

OSSI

Bit 10: OSSI.

OSSR

Bit 11: OSSR.

BKE

Bit 12: BKE.

BKP

Bit 13: BKP.

AOE

Bit 14: AOE.

MOE

Bit 15: MOE.

BKF

Bits 16-19: BKF.

BK2F

Bits 20-23: BK2F.

BK2E

Bit 24: BK2E.

BK2P

Bit 25: BK2P.

BKDSRM

Bit 26: BKDSRM.

BK2DSRM

Bit 27: BK2DSRM.

BKBID

Bit 28: BKBID.

BK2BID

Bit 29: BK2BID.

DCR

TIM8 DMA control register

Offset: 0x48, size: 16, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBL
rw 		DBA
rw
Toggle fields

DBA

Bits 0-4: DBA.

DBL

Bits 8-12: DBL.

DMAR

TIM8 DMA address for full transfer

Offset: 0x4c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAB
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB
rw
Toggle fields

DMAB

Bits 0-31: DMAB.

CCMR3

The channels 5 and 6 can only be configured in output. Output compare mode:

Offset: 0x54, size: 32, reset: 0x00000000, access: read-write

0/10 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OC6M3
rw 		OC5M3
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC6CE
rw 		OC6M
rw 		OC6PE
rw 		OC6FE
rw 		OC5CE
rw 		OC5M
rw 		OC5PE
rw 		OC5FE
rw
Toggle fields

OC5FE

Bit 2: OC5FE.

OC5PE

Bit 3: OC5PE.

OC5M

Bits 4-6: OC5M.

OC5CE

Bit 7: OC5CE.

OC6FE

Bit 10: OC6FE.

OC6PE

Bit 11: OC6PE.

OC6M

Bits 12-14: OC6M.

OC6CE

Bit 15: OC6CE.

OC5M3

Bit 16: OC5M3.

OC6M3

Bit 24: OC6M3.

CCR5

TIM8 capture/compare register 5

Offset: 0x58, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GC5C3
rw 		GC5C2
rw 		GC5C1
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR5
rw
Toggle fields

CCR5

Bits 0-15: CCR5.

GC5C1

Bit 29: GC5C1.

GC5C2

Bit 30: GC5C2.

GC5C3

Bit 31: GC5C3.

CCR6

TIM8 capture/compare register 6

Offset: 0x5c, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR6
rw
Toggle fields

CCR6

Bits 0-15: CCR6.

AF1

TIM8 Alternate function option register 1

Offset: 0x60, size: 32, reset: 0x00000001, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETRSEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETRSEL
rw 		BKINP
rw 		BKDF1BK2E
rw 		BKINE
rw
Toggle fields

BKINE

Bit 0: BKINE.

BKDF1BK2E

Bit 8: BKDF1BK2E.

BKINP

Bit 9: BKINP.

ETRSEL

Bits 14-17: ETRSEL.

AF2

TIM8 Alternate function option register 2

Offset: 0x64, size: 32, reset: 0x00000001, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BK2INP
rw 		BK2DF1BK3E
rw 		BK2INE
rw
Toggle fields

BK2INE

Bit 0: BK2INE.

BK2DF1BK3E

Bit 8: BK2DF1BK3E.

BK2INP

Bit 9: BK2INP.

TISEL

TIM8 timer input selection register

Offset: 0x68, size: 32, reset: 0x00000000, access: read-write

0/4 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TI4SEL
rw 		TI3SEL
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TI2SEL
rw 		TI1SEL
rw
Toggle fields

TI1SEL

Bits 0-3: TI1SEL.

TI2SEL

Bits 8-11: TI2SEL.

TI3SEL

Bits 16-19: TI3SEL.

TI4SEL

Bits 24-27: TI4SEL.

TZC

0x5c006000: TZC

31/96 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 BUILD_CONFIG
0x4 ACTION
0x8 GATE_KEEPER
0xc SPECULATION_CTRL
0x10 INT_STATUS
0x14 INT_CLEAR
0x20 FAIL_ADDRESS_LOW0
0x24 FAIL_ADDRESS_HIGH0
0x28 FAIL_CONTROL0
0x2c FAIL_ID0
0x30 FAIL_ADDRESS_LOW1
0x34 FAIL_ADDRESS_HIGH1
0x38 FAIL_CONTROL1
0x3c FAIL_ID1
0x104 REGION_BASE_HIGH0
0x108 REGION_TOP_LOW0
0x10c REGION_TOP_HIGH0
0x110 REGION_ATTRIBUTE0
0x114 REGION_ID_ACCESS0
0x120 REGION_BASE_LOW1
0x124 REGION_BASE_HIGH1
0x128 REGION_TOP_LOW1
0x12c REGION_TOP_HIGH1
0x130 REGION_ATTRIBUTE1
0x134 REGION_ID_ACCESS1
0x140 REGION_BASE_LOW2
0x144 REGION_BASE_HIGH2
0x148 REGION_TOP_LOW2
0x14c REGION_TOP_HIGH2
0x150 REGION_ATTRIBUTE2
0x154 REGION_ID_ACCESS2
0x160 REGION_BASE_LOW3
0x164 REGION_BASE_HIGH3
0x168 REGION_TOP_LOW3
0x16c REGION_TOP_HIGH3
0x170 REGION_ATTRIBUTE3
0x174 REGION_ID_ACCESS3
0x180 REGION_BASE_LOW4
0x184 REGION_BASE_HIGH4
0x188 REGION_TOP_LOW4
0x18c REGION_TOP_HIGH4
0x190 REGION_ATTRIBUTE4
0x194 REGION_ID_ACCESS4
0x1a0 REGION_BASE_LOW5
0x1a4 REGION_BASE_HIGH5
0x1a8 REGION_TOP_LOW5
0x1ac REGION_TOP_HIGH5
0x1b0 REGION_ATTRIBUTE5
0x1b4 REGION_ID_ACCESS5
0x1c0 REGION_BASE_LOW6
0x1c4 REGION_BASE_HIGH6
0x1c8 REGION_TOP_LOW6
0x1cc REGION_TOP_HIGH6
0x1d0 REGION_ATTRIBUTE6
0x1d4 REGION_ID_ACCESS6
0x1e8 REGION_TOP_LOW7
0x1f0 REGION_ATTRIBUTE7
0x200 REGION_BASE_LOW8
0x204 REGION_BASE_HIGH8
0x210 REGION_ATTRIBUTE8
0x2e0 REGION_BASE_LOW7
0x2e4 REGION_BASE_HIGH7
0x2ec REGION_TOP_HIGH7
0x2f4 REGION_ID_ACCESS7
0x308 REGION_TOP_LOW8
0x30c REGION_TOP_HIGH8
0x314 REGION_ID_ACCESS8
0xfd0 PID4
0xfd4 PID5
0xfd8 PID6
0xfdc PID7
0xfe0 PID0
0xfe4 PID1
0xfe8 PID2
0xfec PID3
0xff0 CID0
0xff4 CID1
0xff8 CID2
0xffc CID3
Toggle registers

BUILD_CONFIG

Provides information about TZC configuration.

Offset: 0x0, size: 32, reset: 0x01001F08, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NO_OF_FILTERS
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRESS_WIDTH
r 		NO_OF_REGIONS
r
Toggle fields

NO_OF_REGIONS

Bits 0-4: NO_OF_REGIONS.

ADDRESS_WIDTH

Bits 8-13: ADDRESS_WIDTH.

NO_OF_FILTERS

Bits 24-25: NO_OF_FILTERS.

ACTION

Controls interrupt and bus error response behavior when regions permission failures occur.

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REACTION_VALUE
rw
Toggle fields

REACTION_VALUE

Bits 0-1: REACTION_VALUE.

GATE_KEEPER

Provides control and status for the gate keeper in each filter unit implemented.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

1/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPENSTAT
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPENREQ
rw
Toggle fields

OPENREQ

Bits 0-1: OPENREQ.

OPENSTAT

Bits 16-17: OPENSTAT.

SPECULATION_CTRL

Controls read and write access speculation.

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRITESPEC_DISABLE
rw 		READSPEC_DISABLE
rw
Toggle fields

READSPEC_DISABLE

Bit 0: READSPEC_DISABLE.

WRITESPEC_DISABLE

Bit 1: WRITESPEC_DISABLE.

INT_STATUS

Contains the status of the interrupt signal, TZCINT, that reports access security violations or region overlap errors.

Offset: 0x10, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVERLAP
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVERRUN
r 		STATUS
r
Toggle fields

STATUS

Bits 0-1: STATUS.

OVERRUN

Bits 8-9: OVERRUN.

OVERLAP

Bits 16-17: OVERLAP.

INT_CLEAR

Interrupt clear for each filter.

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLEAR
w
Toggle fields

CLEAR

Bits 0-1: CLEAR.

FAIL_ADDRESS_LOW0

Address low bits of the first failed access in the associated filter (0 to 1).

Offset: 0x20, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR_STATUS_LOW
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_STATUS_LOW
r
Toggle fields

ADDR_STATUS_LOW

Bits 0-31: ADDR_STATUS_LOW.

FAIL_ADDRESS_HIGH0

Address high bit of the first failed access in the associated filter (0 to 1). Not used with 32bit address.

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

Toggle fields

FAIL_CONTROL0

Status information about the first access that failed a region permission check in the associated filter (0 to 1).

Offset: 0x28, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
r 		NON_SECURE
r 		PRIVILEGE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRIVILEGE

Bit 20: PRIVILEGE.

NON_SECURE

Bit 21: NON_SECURE.

DIRECTION

Bit 24: DIRECTION.

FAIL_ID0

Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD).

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-10: ID.

FAIL_ADDRESS_LOW1

Address low bits of the first failed access in the associated filter (0 to 1).

Offset: 0x30, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR_STATUS_LOW
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_STATUS_LOW
r
Toggle fields

ADDR_STATUS_LOW

Bits 0-31: ADDR_STATUS_LOW.

FAIL_ADDRESS_HIGH1

Address high bit of the first failed access in the associated filter (0 to 1). Not used with 32bit address.

Offset: 0x34, size: 32, reset: 0x00000000, access: read-only

Toggle fields

FAIL_CONTROL1

Status information about the first access that failed a region permission check in the associated filter (0 to 1).

Offset: 0x38, size: 32, reset: 0x00000000, access: read-only

3/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIRECTION
r 		NON_SECURE
r 		PRIVILEGE
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Toggle fields

PRIVILEGE

Bit 20: PRIVILEGE.

NON_SECURE

Bit 21: NON_SECURE.

DIRECTION

Bit 24: DIRECTION.

FAIL_ID1

Contains the master AXI ARID or AWID of the first access that failed a region permission check in the associated filter unit. This occurs even if the ACTION register is set to not drive the interrupt signal. AXI ID mapping is described in Table4: NSAID definition table (TBD).

Offset: 0x3c, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-10: ID.

REGION_BASE_HIGH0

Base address high are not used with 32-bit address.

Offset: 0x104, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW0

Top address bits [31:12] for region 0.

Offset: 0x108, size: 32, reset: 0xFFFFFFFF, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
r
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH0

Top address high of region are not used with 32-bit address.

Offset: 0x10c, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE0

Region 0 attributes.

Offset: 0x110, size: 32, reset: 0x00000003, access: read-write

1/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
r
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS0

Region non-secure access based on NSAID.

Offset: 0x114, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_BASE_LOW1

Base address low for regions 1 to 8.

Offset: 0x120, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH1

Base address high are not used with 32-bit address.

Offset: 0x124, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW1

Top address bits [31:12] for region x.

Offset: 0x128, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH1

Top address high of region are not used with 32-bit address.

Offset: 0x12c, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE1

Region x attributes.

Offset: 0x130, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS1

Region non-secure access based on NSAID.

Offset: 0x134, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_BASE_LOW2

Base address low for regions 1 to 8.

Offset: 0x140, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH2

Base address high are not used with 32-bit address.

Offset: 0x144, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW2

Top address bits [31:12] for region x.

Offset: 0x148, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH2

Top address high of region are not used with 32-bit address.

Offset: 0x14c, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE2

Region x attributes.

Offset: 0x150, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS2

Region non-secure access based on NSAID.

Offset: 0x154, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_BASE_LOW3

Base address low for regions 1 to 8.

Offset: 0x160, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH3

Base address high are not used with 32-bit address.

Offset: 0x164, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW3

Top address bits [31:12] for region x.

Offset: 0x168, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH3

Top address high of region are not used with 32-bit address.

Offset: 0x16c, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE3

Region x attributes.

Offset: 0x170, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS3

Region non-secure access based on NSAID.

Offset: 0x174, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_BASE_LOW4

Base address low for regions 1 to 8.

Offset: 0x180, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH4

Base address high are not used with 32-bit address.

Offset: 0x184, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW4

Top address bits [31:12] for region x.

Offset: 0x188, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH4

Top address high of region are not used with 32-bit address.

Offset: 0x18c, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE4

Region x attributes.

Offset: 0x190, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS4

Region non-secure access based on NSAID.

Offset: 0x194, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_BASE_LOW5

Base address low for regions 1 to 8.

Offset: 0x1a0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH5

Base address high are not used with 32-bit address.

Offset: 0x1a4, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW5

Top address bits [31:12] for region x.

Offset: 0x1a8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH5

Top address high of region are not used with 32-bit address.

Offset: 0x1ac, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE5

Region x attributes.

Offset: 0x1b0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS5

Region non-secure access based on NSAID.

Offset: 0x1b4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_BASE_LOW6

Base address low for regions 1 to 8.

Offset: 0x1c0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH6

Base address high are not used with 32-bit address.

Offset: 0x1c4, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_LOW6

Top address bits [31:12] for region x.

Offset: 0x1c8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH6

Top address high of region are not used with 32-bit address.

Offset: 0x1cc, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE6

Region x attributes.

Offset: 0x1d0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_ID_ACCESS6

Region non-secure access based on NSAID.

Offset: 0x1d4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_TOP_LOW7

Top address bits [31:12] for region x.

Offset: 0x1e8, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_ATTRIBUTE7

Region x attributes.

Offset: 0x1f0, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_BASE_LOW8

Base address low for regions 1 to 8.

Offset: 0x200, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH8

Base address high are not used with 32-bit address.

Offset: 0x204, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ATTRIBUTE8

Region x attributes.

Offset: 0x210, size: 32, reset: 0x00000000, access: read-write

0/3 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S_WR_EN
rw 		S_RD_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FILTER_EN
rw
Toggle fields

FILTER_EN

Bits 0-1: FILTER_EN.

S_RD_EN

Bit 30: S_RD_EN.

S_WR_EN

Bit 31: S_WR_EN.

REGION_BASE_LOW7

Base address low for regions 1 to 8.

Offset: 0x2e0, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BASE_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE_ADDRESS_LOW
rw
Toggle fields

BASE_ADDRESS_LOW

Bits 12-31: BASE_ADDRESS_LOW.

REGION_BASE_HIGH7

Base address high are not used with 32-bit address.

Offset: 0x2e4, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_TOP_HIGH7

Top address high of region are not used with 32-bit address.

Offset: 0x2ec, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ID_ACCESS7

Region non-secure access based on NSAID.

Offset: 0x2f4, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

REGION_TOP_LOW8

Top address bits [31:12] for region x.

Offset: 0x308, size: 32, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TOP_ADDRESS_LOW
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOP_ADDRESS_LOW
rw
Toggle fields

TOP_ADDRESS_LOW

Bits 12-31: TOP_ADDRESS_LOW.

REGION_TOP_HIGH8

Top address high of region are not used with 32-bit address.

Offset: 0x30c, size: 32, reset: 0x00000000, access: read-only

Toggle fields

REGION_ID_ACCESS8

Region non-secure access based on NSAID.

Offset: 0x314, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSAID_WR_EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSAID_RD_EN
rw
Toggle fields

NSAID_RD_EN

Bits 0-15: NSAID_RD_EN.

NSAID_WR_EN

Bits 16-31: NSAID_WR_EN.

PID4

Peripheral ID 4.

Offset: 0xfd0, size: 32, reset: 0x00000004, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_4
r
Toggle fields

PER_ID_4

Bits 0-7: PER_ID_4.

PID5

Peripheral ID 5.

Offset: 0xfd4, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_5
r
Toggle fields

PER_ID_5

Bits 0-7: PER_ID_5.

PID6

Peripheral ID 6.

Offset: 0xfd8, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_6
r
Toggle fields

PER_ID_6

Bits 0-7: PER_ID_6.

PID7

Peripheral ID 7.

Offset: 0xfdc, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_7
r
Toggle fields

PER_ID_7

Bits 0-7: PER_ID_7.

PID0

Peripheral ID 0.

Offset: 0xfe0, size: 32, reset: 0x00000060, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_0
r
Toggle fields

PER_ID_0

Bits 0-7: PER_ID_0.

PID1

Peripheral ID 1.

Offset: 0xfe4, size: 32, reset: 0x000000B4, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_1
r
Toggle fields

PER_ID_1

Bits 0-7: PER_ID_1.

PID2

Peripheral ID 2.

Offset: 0xfe8, size: 32, reset: 0x0000002B, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_2
r
Toggle fields

PER_ID_2

Bits 0-7: PER_ID_2.

PID3

Peripheral ID 3.

Offset: 0xfec, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PER_ID_3
r
Toggle fields

PER_ID_3

Bits 0-7: PER_ID_3.

CID0

Component ID 0.

Offset: 0xff0, size: 32, reset: 0x0000000D, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_ID_0
r
Toggle fields

COMP_ID_0

Bits 0-7: COMP_ID_0.

CID1

Component ID 1.

Offset: 0xff4, size: 32, reset: 0x000000F0, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_ID_1
r
Toggle fields

COMP_ID_1

Bits 0-7: COMP_ID_1.

CID2

Component ID 2.

Offset: 0xff8, size: 32, reset: 0x00000005, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_ID_2
r
Toggle fields

COMP_ID_2

Bits 0-7: COMP_ID_2.

CID3

Component ID 3.

Offset: 0xffc, size: 32, reset: 0x000000B1, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP_ID_3
r
Toggle fields

COMP_ID_3

Bits 0-7: COMP_ID_3.

USART1

0x5c000000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART2

0x4000e000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART3

0x4000f000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART4

0x40010000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART5

0x40011000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART6

0x44003000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART7

0x40018000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USART8

0x40019000: Universal synchronous asynchronous receiver transmitter

43/140 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CR1
0x4 CR2
0x8 CR3
0xc BRR
0x10 GTPR
0x14 RTOR
0x18 RQR
0x1c ISR
0x20 ICR
0x24 RDR
0x28 TDR
0x2c PRESC
0x3ec HWCFGR2
0x3f0 HWCFGR1
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR1

Control register 1

Offset: 0x0, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RXFFIE
rw 		TXFEIE
rw 		FIFOEN
rw 		M1
rw 		EOBIE
rw 		RTOIE
rw 		DEAT
rw 		DEDT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8
rw 		CMIE
rw 		MME
rw 		M0
rw 		WAKE
rw 		PCE
rw 		PS
rw 		PEIE
rw 		TXEIE
rw 		TCIE
rw 		RXNEIE
rw 		IDLEIE
rw 		TE
rw 		RE
rw 		UESM
rw 		UE
rw
Toggle fields

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT

Bits 16-20: DEDT.

DEAT

Bits 21-25: DEAT.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/21 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD4_7
rw 		ADD0_3
rw 		RTOEN
rw 		ABRMOD
rw 		ABREN
rw 		MSBFIRST
rw 		TAINV
rw 		TXINV
rw 		RXINV
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWAP
rw 		LINEN
rw 		STOP
rw 		CLKEN
rw 		CPOL
rw 		CPHA
rw 		LBCL
rw 		LBDIE
rw 		LBDL
rw 		ADDM7
rw 		DIS_NSS
rw 		SLVEN
rw
Toggle fields

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD

Bits 21-22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/24 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFTCFG
rw 		RXFTIE
rw 		RXFTCFG
rw 		TCBGTIE
rw 		TXFTIE
rw 		WUFIE
rw 		WUS
rw 		SCARCNT
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEP
rw 		DEM
rw 		DDRE
rw 		OVRDIS
rw 		ONEBIT
rw 		CTSIE
rw 		CTSE
rw 		RTSE
rw 		DMAT
rw 		DMAR
rw 		SCEN
rw 		NACK
rw 		HDSEL
rw 		IRLP
rw 		IREN
rw 		EIE
rw
Toggle fields

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xc, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR_4_15
rw 		BRR_0_3
rw
Toggle fields

BRR_0_3

Bits 0-3: BRR_0_3.

BRR_4_15

Bits 4-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT
rw 		PSC
rw
Toggle fields

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN
rw 		RTO
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO
rw
Toggle fields

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, size: 32, reset: 0x00000000, access: write-only

0/5 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFRQ
w 		RXFRQ
w 		MMRQ
w 		SBKRQ
w 		ABRRQ
w
Toggle fields

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1c, size: 32, reset: 0x000000C0, access: read-only

28/28 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXFT
r 		RXFT
r 		TCBGT
r 		RXFF
r 		TXFE
r 		REACK
r 		TEACK
r 		WUF
r 		RWU
r 		SBKF
r 		CMF
r 		BUSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF
r 		ABRE
r 		UDR
r 		EOBF
r 		RTOF
r 		CTS
r 		CTSIF
r 		LBDF
r 		TXE
r 		TC
r 		RXNE
r 		IDLE
r 		ORE
r 		NF
r 		FE
r 		PE
r
Toggle fields

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, size: 32, reset: 0x00000000, access: write-only

0/15 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WUCF
w 		CMCF
w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UDRCF
w 		EOBCF
w 		RTOCF
w 		CTSCF
w 		LBDCF
w 		TCBGTCF
w 		TCCF
w 		TXFECF
w 		IDLECF
w 		ORECF
w 		NCF
w 		FECF
w 		PECF
w
Toggle fields

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, size: 32, reset: 0x00000000, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDR
r
Toggle fields

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR
rw
Toggle fields

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2c, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRESCALER
rw
Toggle fields

PRESCALER

Bits 0-3: Clock prescaler.

HWCFGR2

USART Hardware Configuration register 2

Offset: 0x3ec, size: 32, reset: 0x00000014, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

HWCFGR1

USART Hardware Configuration register 1

Offset: 0x3f0, size: 32, reset: 0x00000014, access: read-only

8/8 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CFG8
r 		CFG7
r 		CFG6
r 		CFG5
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG4
r 		CFG3
r 		CFG2
r 		CFG1
r
Toggle fields

CFG1

Bits 0-3: CFG1.

CFG2

Bits 4-7: CFG2.

CFG3

Bits 8-11: CFG3.

CFG4

Bits 12-15: CFG4.

CFG5

Bits 16-19: CFG5.

CFG6

Bits 20-23: CFG6.

CFG7

Bits 24-27: CFG7.

CFG8

Bits 28-31: CFG8.

VERR

EXTI IP Version register

Offset: 0x3f4, size: 32, reset: 0x00000023, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

EXTI Identification register

Offset: 0x3f8, size: 32, reset: 0x00130003, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IPID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IPID
r
Toggle fields

IPID

Bits 0-31: IP Identification.

SIDR

EXTI Size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: Size Identification.

USBPHYC

0x5a006000: USBPHYC

2/49 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 PLL
0x8 MISC
0x10c TUNE1
0x20c TUNE2
0xffc VERR
Toggle registers

PLL

This register is used to control the PLL of the HS PHY.

Offset: 0x0, size: 32, reset: 0xC0000000, access: read-write

0/9 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLDITHEN1
rw 		PLLDITHEN0
rw 		PLLFRACCTL
rw 		PLLSTRBYP
rw 		PLLSTRB
rw 		PLLEN
rw 		PLLFRACIN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLFRACIN
rw 		PLLODF
rw 		PLLNDIV
rw
Toggle fields

PLLNDIV

Bits 0-6: PLLNDIV.

PLLODF

Bits 7-9: PLLODF.

PLLFRACIN

Bits 10-25: PLLFRACIN.

PLLEN

Bit 26: PLLEN.

PLLSTRB

Bit 27: PLLSTRB.

PLLSTRBYP

Bit 28: PLLSTRBYP.

PLLFRACCTL

Bit 29: PLLFRACCTL.

PLLDITHEN0

Bit 30: PLLDITHEN0.

PLLDITHEN1

Bit 31: PLLDITHEN1.

MISC

This register is used to control the switch between controllers for the HS PHY.

Offset: 0x8, size: 32, reset: 0x00000000, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PPCKDIS
rw 		SWITHOST
rw
Toggle fields

SWITHOST

Bit 0: SWITHOST.

PPCKDIS

Bits 1-2: PPCKDIS.

TUNE1

This register is used to control the tune interface of the HS PHY, port #x.

Offset: 0x10c, size: 32, reset: 0x04070004, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STAGSEL
rw 		SHTCCTCTLPROT
rw 		HSFALLPREEM
rw 		HSRXOFF
rw 		HDRXGNEQEN
rw 		SQLCHCTL
rw 		OTPCOMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTPCOMP
rw 		HSDRVCHKZTRM
rw 		HSDRVCHKITRM
rw 		HSDRVRFRED
rw 		FSDRVRFADJ
rw 		HSDRVCURINCR
rw 		HSDRVDCLEV
rw 		HSDRVDCCUR
rw 		HSDRVSLEW
rw 		LFSCAPEN
rw 		INCURRINT
rw 		INCURREN
rw
Toggle fields

INCURREN

Bit 0: INCURREN.

INCURRINT

Bit 1: INCURRINT.

LFSCAPEN

Bit 2: LFSCAPEN.

HSDRVSLEW

Bit 3: HSDRVSLEW.

HSDRVDCCUR

Bit 4: HSDRVDCCUR.

HSDRVDCLEV

Bit 5: HSDRVDCLEV.

HSDRVCURINCR

Bit 6: HSDRVCURINCR.

FSDRVRFADJ

Bit 7: FSDRVRFADJ.

HSDRVRFRED

Bit 8: HSDRVRFRED.

HSDRVCHKITRM

Bits 9-12: HSDRVCHKITRM.

HSDRVCHKZTRM

Bits 13-14: HSDRVCHKZTRM.

OTPCOMP

Bits 15-19: OTPCOMP.

SQLCHCTL

Bits 20-21: SQLCHCTL.

HDRXGNEQEN

Bit 22: HDRXGNEQEN.

HSRXOFF

Bits 23-24: HSRXOFF.

HSFALLPREEM

Bit 25: HSFALLPREEM.

SHTCCTCTLPROT

Bit 26: SHTCCTCTLPROT.

STAGSEL

Bit 27: STAGSEL.

TUNE2

This register is used to control the tune interface of the HS PHY, port #x.

Offset: 0x20c, size: 32, reset: 0x04070004, access: read-write

0/18 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
STAGSEL
rw 		SHTCCTCTLPROT
rw 		HSFALLPREEM
rw 		HSRXOFF
rw 		HDRXGNEQEN
rw 		SQLCHCTL
rw 		OTPCOMP
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTPCOMP
rw 		HSDRVCHKZTRM
rw 		HSDRVCHKITRM
rw 		HSDRVRFRED
rw 		FSDRVRFADJ
rw 		HSDRVCURINCR
rw 		HSDRVDCLEV
rw 		HSDRVDCCUR
rw 		HSDRVSLEW
rw 		LFSCAPEN
rw 		INCURRINT
rw 		INCURREN
rw
Toggle fields

INCURREN

Bit 0: INCURREN.

INCURRINT

Bit 1: INCURRINT.

LFSCAPEN

Bit 2: LFSCAPEN.

HSDRVSLEW

Bit 3: HSDRVSLEW.

HSDRVDCCUR

Bit 4: HSDRVDCCUR.

HSDRVDCLEV

Bit 5: HSDRVDCLEV.

HSDRVCURINCR

Bit 6: HSDRVCURINCR.

FSDRVRFADJ

Bit 7: FSDRVRFADJ.

HSDRVRFRED

Bit 8: HSDRVRFRED.

HSDRVCHKITRM

Bits 9-12: HSDRVCHKITRM.

HSDRVCHKZTRM

Bits 13-14: HSDRVCHKZTRM.

OTPCOMP

Bits 15-19: OTPCOMP.

SQLCHCTL

Bits 20-21: SQLCHCTL.

HDRXGNEQEN

Bit 22: HDRXGNEQEN.

HSRXOFF

Bits 23-24: HSRXOFF.

HSFALLPREEM

Bit 25: HSFALLPREEM.

SHTCCTCTLPROT

Bit 26: SHTCCTCTLPROT.

STAGSEL

Bit 27: STAGSEL.

VERR

This register defines the version of this IP.

Offset: 0xffc, size: 32, reset: 0x00000010, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

VREFBUF

0x50025000: VREFBUF

1/5 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 CSR
0x4 CCR
Toggle registers

CSR

VREFBUF control and status register

Offset: 0x0, size: 32, reset: 0x00000002, access: Unspecified

1/4 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VRS
rw 		VRR
r 		HIZ
rw 		ENVR
rw
Toggle fields

ENVR

Bit 0: ENVR.

HIZ

Bit 1: HIZ.

VRR

Bit 3: VRR.

VRS

Bits 4-6: VRS.

CCR

VREFBUF calibration control register

Offset: 0x4, size: 32, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM
rw
Toggle fields

TRIM

Bits 0-5: TRIM.

WWDG1

0x4000a000: WWDG1

5/11 fields covered.

Toggle register map
Offset Name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0 (16-bit) CR
0x4 (16-bit) CFR
0x8 (16-bit) SR
0x3f0 HWCFGR
0x3f4 VERR
0x3f8 IPIDR
0x3fc SIDR
Toggle registers

CR

Control register

Offset: 0x0, size: 16, reset: 0x0000007F, access: read-write

0/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGA
rw 		T
rw
Toggle fields

T

Bits 0-6: T.

WDGA

Bit 7: WDGA.

CFR

Configuration register

Offset: 0x4, size: 16, reset: 0x0000007F, access: read-write

0/3 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDGTB
rw 		EWI
rw 		W
rw
Toggle fields

W

Bits 0-6: W.

EWI

Bit 9: EWI.

WDGTB

Bits 11-13: WDGTB.

SR

Status register

Offset: 0x8, size: 16, reset: 0x00000000, access: read-write

0/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWIF
rw
Toggle fields

EWIF

Bit 0: EWIF.

HWCFGR

WWDG hardware configuration register

Offset: 0x3f0, size: 32, reset: 0x00000FFF, access: read-only

1/1 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PREDIV
r
Toggle fields

PREDIV

Bits 0-15: PREDIV.

VERR

WWDG version register

Offset: 0x3f4, size: 32, reset: 0x00000021, access: read-only

2/2 fields covered.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAJREV
r 		MINREV
r
Toggle fields

MINREV

Bits 0-3: MINREV.

MAJREV

Bits 4-7: MAJREV.

IPIDR

WWDG ID register

Offset: 0x3f8, size: 32, reset: 0x00120051, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID
r
Toggle fields

ID

Bits 0-31: ID.

SIDR

WWDG size ID register

Offset: 0x3fc, size: 32, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SID
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SID
r
Toggle fields

SID

Bits 0-31: SID.