ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADEN+1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to 1..

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..

EOS

Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..

AWD1

Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1..

AWD2

Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it..

AWD3

Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1..

EOCAL

Bit 11: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it..

CCRDY

Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

EOSMPIE

Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

EOCIE

Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

EOSIE

Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

AWD1IE

Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

AWD2IE

Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

AWD3IE

Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

EOCALIE

Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

CCRDYIE

Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing)..

ADEN

Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command..

ADDIS

Bit 1: ADC disable command.

ADSTART

Bit 2: ADC start conversion command.

ADSTP

Bit 4: ADC stop conversion command.

ADVREGEN

Bit 28: ADC Voltage Regulator Enable.

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC..

DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333..

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN1=11. For more details, refer to Section113.6.5: Managing converted data using the DMA on page1333..

SCANDIR

Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared. Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion..

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332.

EXTSEL

Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table160: External triggers for details):.

EXTEN

Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger..

OVRMOD

Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed..

CONT

Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11..

WAIT

Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.^..

AUTOFF

Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.^..

DISCEN

Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN1=11 and CONT1=11..

CHSELRMOD

Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

AWD1SGL

Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels.

AWD1EN

Bit 23: Analog watchdog enable This bit is set and cleared by software..

AWD1CH

Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register..

OVSE

Bit 0: Oversampler Enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared..

OVSR

Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADEN bit is cleared..

OVSS

Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADEN bit is cleared..

TOVS

Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared..

LFTRIG

Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADEN bit is cleared..

CKMODE

Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10)..

SMP1

Bits 0-2: Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

SMP2

Bits 4-6: Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

SMPSEL0

Bit 8: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL1

Bit 9: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL2

Bit 10: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL3

Bit 11: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL4

Bit 12: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL5

Bit 13: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL6

Bit 14: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL7

Bit 15: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL8

Bit 16: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL9

Bit 17: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL10

Bit 18: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL11

Bit 19: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL12

Bit 20: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL13

Bit 21: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL14

Bit 22: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL15

Bit 23: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL16

Bit 24: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL17

Bit 25: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL18

Bit 26: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SMPSEL19

Bit 27: Channel-x sampling time selection (x1=119 to 0) These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

LT1

Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section113.8: Analog window watchdogs on page1337..

HT1

Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section113.8: Analog window watchdogs on page1337..

LT2

Bits 0-11: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section113.8: Analog window watchdogs on page1337..

HT2

Bits 16-27: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section113.8: Analog window watchdogs on page1337..

CHSEL0

Bit 0: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL1

Bit 1: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL2

Bit 2: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL3

Bit 3: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL4

Bit 4: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL5

Bit 5: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL6

Bit 6: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL7

Bit 7: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL8

Bit 8: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL9

Bit 9: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL10

Bit 10: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL11

Bit 11: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL12

Bit 12: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL13

Bit 13: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL14

Bit 14: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL15

Bit 15: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL16

Bit 16: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL17

Bit 17: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL18

Bit 18: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

CHSEL19

Bit 19: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing). Note: If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

SQ1

Bits 0-3: 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ2

Bits 4-7: 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ3

Bits 8-11: 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ4

Bits 12-15: 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ5

Bits 16-19: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ6

Bits 20-23: 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ7

Bits 24-27: 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

SQ8

Bits 28-31: 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

LT3

Bits 0-11: Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section113.8: Analog window watchdogs on page1337..

HT3

Bits 16-27: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section113.8: Analog window watchdogs on page1337..

DATA

Bits 0-15: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure141: Data alignment and resolution (oversampling disabled: OVSE = 0) on page1332. Just after a calibration is complete, DATA[6:0] contains the calibration factor..

AWD2CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD2CH19

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

AWD3CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

AWD3CH19

Bit 19: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

CALFACT

Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete,1they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new conversion is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)..

PRESC

Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL1=10, ADSTART1=10, ADSTP1=10, ADDIS1=10 and ADEN1=10)..

VREFEN

Bit 22: V_REFINT enable This bit is set and cleared by software to enable/disable the V_REFINT. Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

TSEN

Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing)..

VBATEN

Bit 24: V_BAT enable This bit is set and cleared by software to enable/disable the V_BAT channel. Note: The software is allowed to write this bit only when ADSTART1=10 (which ensures that no conversion is ongoing).

EN

Bit 0: Comparator 1 enable bit This bit is controlled by software (if not locked). It enables the comparator 1:.

INMSEL

Bits 4-7: Comparator 1 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 1: Refer to Table176: COMP1 inverting input assignment..

INPSEL

Bits 8-10: Comparator 1 signal selector for noninverting input This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 1 (also see the WINMODE bit): Refer to Table175: COMP1 noninverting input assignment..

WINMODE

Bit 11: Comparator 1 noninverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 1:.

WINOUT

Bit 14: Comparator 1 output selector This bit is controlled by software (if not locked). It selects the comparator 1 output:.

POLARITY

Bit 15: Comparator 1 polarity selector This bit is controlled by software (if not locked). It selects the comparator 1 output polarity:.

HYST

Bits 16-17: Comparator 1 hysteresis selector This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1:.

PWRMODE

Bits 18-19: Comparator 1 power mode selector This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1:.

BLANKSEL

Bits 20-24: Comparator 1 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: Others: Reserved, must not be used.

VALUE

Bit 30: Comparator 1 output status This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in Figure163..

LOCK

Bit 31: COMP_CSR register lock This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only..

EN

Bit 0: Comparator 2 enable bit This bit is controlled by software (if not locked). It enables the comparator 2:.

INMSEL

Bits 4-7: Comparator 2 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP_INM of the comparator 2: Refer to Table178: COMP2 inverting input assignment..

INPSEL

Bits 8-9: Comparator 2 signal selector for noninverting input This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP_INP of the comparator 2 (also see the WINMODE bit): Refer to Table177: COMP2 noninverting input assignment..

WINMODE

Bit 11: Comparator 2 noninverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP_INP input of the comparator 2:.

WINOUT

Bit 14: Comparator 2 output selector This bit is controlled by software (if not locked). It selects the comparator 2 output:.

POLARITY

Bit 15: Comparator 2 polarity selector This bit is controlled by software (if not locked). It selects the comparator 2 output polarity:.

HYST

Bits 16-17: Comparator 2 hysteresis selector This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2:.

PWRMODE

Bits 18-19: Comparator 2 power mode selector This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2:.

BLANKSEL

Bits 20-24: Comparator 2 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: Others: Reserved, must not be used.

VALUE

Bit 30: Comparator 2 output status This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in Figure163..

LOCK

Bit 31: COMP_CSR register lock This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only..

DR

Bits 0-31: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value..

IDR

Bits 0-31: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for four bytes. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.

RESET

Bit 0: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

REV_IN

Bits 5-6: Reverse input data This bitfield controls the reversal of the bit order of the input data.

REV_OUT

Bits 7-8: Reverse output data This bitfield controls the reversal of the bit order of the output data..

RTYPE_IN

Bit 9: Reverse type input This bit controls the reversal granularity of the input data..

RTYPE_OUT

Bit 10: Reverse type output This bit controls the reversal granularity of the output data..

CRC_INIT

Bits 0-31: Programmable initial CRC value This register is used to write the CRC initial value..

POL

Bits 0-31: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32 bits, the least significant bits have to be used to program the correct value..

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

TEN1

Bit 1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle..

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in Section114.4.2: DAC pins and internal signals for details on trigger configuration and mapping. Note: Only used if bit TEN11=11 (DAC channel1 trigger enabled)..

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN11=11 (DAC channel1 trigger enabled)..

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector.

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

CEN1

Bit 14: DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN11=10 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1..

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

CAL_FLAG1

Bit 14: DAC channel1 calibration offset status This bit is set and cleared by hardware.

BWST1

Bit 15: DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization)..

OTRIM1

Bits 0-4: DAC channel1 offset trimming value.

MODE1

Bits 0-2: DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN11=10 and bit CEN11=10 in the DAC_CR register). If EN11=11 or CEN11=11 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample & hold mode Note: This register can be modified only when EN11=10..

TSAMPLE1

Bits 0-9: DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST11=11, the write operation is ignored..

THOLD1

Bits 0-9: DAC channel1 hold time (only valid in Sample and hold mode) Hold time1=1(THOLD[9:0]) x LSI clock period Note: This register can be modified only when EN11=10..

TREFRESH1

Bits 0-7: DAC channel1 refresh time (only valid in Sample and hold mode) Refresh time1=1(TREFRESH[7:0]) x LSI clock period Note: This register can be modified only when EN11=10..

DEV_ID

Bits 0-11: Device identifier This field indicates the device ID..

REV_ID

Bits 16-31: Revision identifier This field indicates the revision of the device..

DBG_STOP

Bit 1: Debug Stop mode Debug options in Stop mode..

DBG_STANDBY

Bit 2: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode..

DBG_TIM2_STOP

Bit 0: TIM2 stop in debug.

DBG_TIM3_STOP

Bit 1: TIM3 stop in debug.

DBG_TIM4_STOP

Bit 2: TIM4 stop in debug.

DBG_TIM6_STOP

Bit 4: TIM6 stop in debug.

DBG_TIM7_STOP

Bit 5: TIM7 stop in debug.

DBG_RTC_STOP

Bit 10: RTC stop in debug.

DBG_WWDG_STOP

Bit 11: WWDG stop in debug.

DBG_IWDG_STOP

Bit 12: IWDG stop in debug.

DBG_I2C3_STOP

Bit 21: I2C3 SMBUS timeout stop in debug.

DBG_I2C1_STOP

Bit 22: I2C1 SMBUS timeout stop in debug.

DBG_LPTIM2_STOP

Bit 30: LPTIM2 stop in debug.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 stop in debug.

DBG_TIM1_STOP

Bit 11: TIM1 stop in debug.

DBG_TIM14_STOP

Bit 15: TIM14 stop in debug.

DBG_TIM15_STOP

Bit 16: TIM15 stop in debug.

DBG_TIM16_STOP

Bit 17: TIM16 stop in debug.

AP1_PRESENT

Bit 0: Identifies whether access port AP1 is present in device.

AP0_PRESENT

Bit 1: Identifies whether access port AP0 is present in device.

AP1_ENABLED

Bit 16: Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked).

AP0_ENABLED

Bit 17: Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked).

MESSAGE

Bits 0-31: Debug host to device mailbox message. During debug authentication the debug host communicates with the device via this register..

MESSAGE

Bits 0-31: Device to debug host mailbox message. During debug authentication the device communicates with the debug host via this register..

JEP106CON

Bits 0-3: JEP106 continuation code.

SIZE

Bits 4-7: register file size.

PARTNUM

Bits 0-7: part number bits [7:0].

PARTNUM

Bits 0-3: part number bits [11:8].

JEP106ID

Bits 4-7: JEP106 identity code bits [3:0].

JEP106ID

Bits 0-2: JEP106 identity code bits [6:4].

JEDEC

Bit 3: JEDEC assigned value.

REVISION

Bits 4-7: component revision number.

CMOD

Bits 0-3: customer modified.

REVAND

Bits 4-7: metal fix version.

PREAMBLE

Bits 0-7: component identification bits [7:0].

PREAMBLE

Bits 0-3: component identification bits [11:8].

CLASS

Bits 4-7: component identification bits [15:12] - component class.

PREAMBLE

Bits 0-7: component identification bits [23:16].

PREAMBLE

Bits 0-7: component identification bits [31:24].

GIF1

Bit 0: Global interrupt flag for channel 1.

TCIF1

Bit 1: Transfer complete (TC) flag for channel 1.

HTIF1

Bit 2: Half transfer (HT) flag for channel 1.

TEIF1

Bit 3: Transfer error (TE) flag for channel 1.

GIF2

Bit 4: Global interrupt flag for channel 2.

TCIF2

Bit 5: Transfer complete (TC) flag for channel 2.

HTIF2

Bit 6: Half transfer (HT) flag for channel 2.

TEIF2

Bit 7: Transfer error (TE) flag for channel 2.

GIF3

Bit 8: Global interrupt flag for channel 3.

TCIF3

Bit 9: Transfer complete (TC) flag for channel 3.

HTIF3

Bit 10: Half transfer (HT) flag for channel 3.

TEIF3

Bit 11: Transfer error (TE) flag for channel 3.

GIF4

Bit 12: global interrupt flag for channel 4.

TCIF4

Bit 13: Transfer complete (TC) flag for channel 4.

HTIF4

Bit 14: Half transfer (HT) flag for channel 4.

TEIF4

Bit 15: Transfer error (TE) flag for channel 4.

GIF5

Bit 16: global interrupt flag for channel 5.

TCIF5

Bit 17: Transfer complete (TC) flag for channel 5.

HTIF5

Bit 18: Half transfer (HT) flag for channel 5.

TEIF5

Bit 19: Transfer error (TE) flag for channel 5.

GIF6

Bit 20: Global interrupt flag for channel 6.

TCIF6

Bit 21: Transfer complete (TC) flag for channel 6.

HTIF6

Bit 22: Half transfer (HT) flag for channel 6.

TEIF6

Bit 23: Transfer error (TE) flag for channel 6.

GIF7

Bit 24: Global interrupt flag for channel 7.

TCIF7

Bit 25: Transfer complete (TC) flag for channel 7.

HTIF7

Bit 26: Half transfer (HT) flag for channel 7.

TEIF7

Bit 27: Transfer error (TE) flag for channel 7.

CGIF1

Bit 0: Global interrupt flag clear for channel 1.

CTCIF1

Bit 1: Transfer complete flag clear for channel 1.

CHTIF1

Bit 2: Half transfer flag clear for channel 1.

CTEIF1

Bit 3: Transfer error flag clear for channel 1.

CGIF2

Bit 4: Global interrupt flag clear for channel 2.

CTCIF2

Bit 5: Transfer complete flag clear for channel 2.

CHTIF2

Bit 6: Half transfer flag clear for channel 2.

CTEIF2

Bit 7: Transfer error flag clear for channel 2.

CGIF3

Bit 8: Global interrupt flag clear for channel 3.

CTCIF3

Bit 9: Transfer complete flag clear for channel 3.

CHTIF3

Bit 10: Half transfer flag clear for channel 3.

CTEIF3

Bit 11: Transfer error flag clear for channel 3.

CGIF4

Bit 12: Global interrupt flag clear for channel 4.

CTCIF4

Bit 13: Transfer complete flag clear for channel 4.

CHTIF4

Bit 14: Half transfer flag clear for channel 4.

CTEIF4

Bit 15: Transfer error flag clear for channel 4.

CGIF5

Bit 16: Global interrupt flag clear for channel 5.

CTCIF5

Bit 17: Transfer complete flag clear for channel 5.

CHTIF5

Bit 18: Half transfer flag clear for channel 5.

CTEIF5

Bit 19: Transfer error flag clear for channel 5.

CGIF6

Bit 20: Global interrupt flag clear for channel 6.

CTCIF6

Bit 21: Transfer complete flag clear for channel 6.

CHTIF6

Bit 22: Half transfer flag clear for channel 6.

CTEIF6

Bit 23: Transfer error flag clear for channel 6.

CGIF7

Bit 24: Global interrupt flag clear for channel 7.

CTCIF7

Bit 25: Transfer complete flag clear for channel 7.

CHTIF7

Bit 26: Half transfer flag clear for channel 7.

CTEIF7

Bit 27: Transfer error flag clear for channel 7.

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

NDT

Bits 0-15: Number of data to transfer.

PA

Bits 0-31: Peripheral address It contains the base address of the peripheral data register from/to which the data is read/written. When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned to a half-word address. When PSIZE[1:0] = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory destination address if DIR = 1 and the memory source address if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination address if DIR1= 1 and the peripheral source address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

MA

Bits 0-31: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned to a half-word address. When MSIZE[1:0] = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically aligned to a word address. In memory-to-memory mode, this bitfield identifies the memory source address if DIR = 1 and the memory destination address if DIR1=10. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source address if DIR1=11 and the peripheral destination address if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

EN

Bit 0: Channel enable When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by1setting the CTEIFx bit of the DMA_IFCR register). Note: This bit is set and cleared by software..

TCIE

Bit 1: Transfer complete interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

HTIE

Bit 2: Half transfer interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

TEIE

Bit 3: Transfer error interrupt enable Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

DIR

Bit 4: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode. Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register. This is still valid in a peripheral-to-peripheral mode. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

CIRC

Bit 5: Circular mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is not read-only when the channel is enabled (EN = 1)..

PINC

Bit 6: Peripheral increment mode Defines the increment mode for each DMA transfer to the identified peripheral. n memory-to-memory mode, this bit identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MINC

Bit 7: Memory increment mode Defines the increment mode for each DMA transfer to the identified memory. In memory-to-memory mode, this bit identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bit identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PSIZE

Bits 8-9: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MSIZE

Bits 10-11: Memory size Defines the data size of each DMA transfer to the identified memory. In memory-to-memory mode, this bitfield identifies the memory source if DIR = 1 and the memory destination if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral source if DIR = 1 and the peripheral destination if DIR = 0. Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

PL

Bits 12-13: Priority level Note: This bitfield is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

MEM2MEM

Bit 14: Memory-to-memory mode Note: This bit is set and cleared by software. It must not be written when the channel is enabled (EN = 1). It is read-only when the channel is enabled (EN = 1)..

NDT

Bits 0-15: Number of data to transfer.